Re: [PATCH 2/5] clk: qcom: sa8775p: Add UFS clock support

[Sumit Garg <sumit.garg@kernel.org>]

On Thu, Mar 19, 2026 at 03:07:39PM +0530, Balaji Selvanathan wrote:
> Add UFS clock support for SA8775P including register definitions,
> rate configuration, and gate clocks.
> 
> Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
> ---
>  drivers/clk/qcom/clock-sa8775p.c | 63 ++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 63 insertions(+)
>

Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

-Sumit

> diff --git a/drivers/clk/qcom/clock-sa8775p.c b/drivers/clk/qcom/clock-sa8775p.c
> index 4957abf6f58..7eec4aeae48 100644
> --- a/drivers/clk/qcom/clock-sa8775p.c
> +++ b/drivers/clk/qcom/clock-sa8775p.c
> @@ -19,6 +19,11 @@
>  #define USB30_PRIM_MASTER_CLK_CMD_RCGR		0x1b028
>  #define USB3_PRIM_PHY_AUX_CMD_RCGR		0x1b06c
>  
> +#define UFS_PHY_AXI_CLK_CMD_RCGR		0x8302c
> +#define UFS_PHY_ICE_CORE_CLK_CMD_RCGR		0x83074
> +#define UFS_PHY_PHY_AUX_CLK_CMD_RCGR		0x830a8
> +#define UFS_PHY_UNIPRO_CORE_CLK_CMD_RCGR	0x8308c
> +
>  #define GCC_QUPV3_WRAP0_S0_CLK_ENA_BIT BIT(10)
>  #define GCC_QUPV3_WRAP0_S1_CLK_ENA_BIT BIT(11)
>  #define GCC_QUPV3_WRAP0_S2_CLK_ENA_BIT BIT(12)
> @@ -44,9 +49,35 @@
>  
>  #define GCC_QUPV3_WRAP3_S0_CLK_ENA_BIT BIT(25)
>  
> +/* UFS AXI clock frequency table */
> +static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
> +	F(25000000, CFG_CLK_SRC_GPLL0_EVEN, 12, 0, 0),
> +	F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0),
> +	F(150000000, CFG_CLK_SRC_GPLL0, 4, 0, 0),
> +	F(300000000, CFG_CLK_SRC_GPLL0, 2, 0, 0),
> +	{ }
> +};
> +
> +/* UFS ICE CORE clock frequency table */
> +static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
> +	F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0),
> +	F(150000000, CFG_CLK_SRC_GPLL0, 4, 0, 0),
> +	F(300000000, CFG_CLK_SRC_GPLL0, 2, 0, 0),
> +	{ }
> +};
> +
> +/* UFS UNIPRO CORE clock frequency table */
> +static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = {
> +	F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0),
> +	F(150000000, CFG_CLK_SRC_GPLL0, 4, 0, 0),
> +	F(300000000, CFG_CLK_SRC_GPLL0, 2, 0, 0),
> +	{ }
> +};
> +
>  static ulong sa8775p_set_rate(struct clk *clk, ulong rate)
>  {
>  	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
> +	const struct freq_tbl *freq;
>  
>  	if (clk->id < priv->data->num_clks)
>  		debug("%s: %s, requested rate=%ld\n", __func__,
> @@ -63,6 +94,24 @@ static ulong sa8775p_set_rate(struct clk *clk, ulong rate)
>  				     5, 0, 0, CFG_CLK_SRC_GPLL0, 8);
>  		clk_rcg_set_rate(priv->base, USB3_PRIM_PHY_AUX_CMD_RCGR, 0, 0);
>  		return rate;
> +	case GCC_UFS_PHY_AXI_CLK:
> +		freq = qcom_find_freq(ftbl_gcc_ufs_phy_axi_clk_src, rate);
> +		clk_rcg_set_rate_mnd(priv->base, UFS_PHY_AXI_CLK_CMD_RCGR,
> +				     freq->pre_div, freq->m, freq->n, freq->src, 8);
> +		return freq->freq;
> +	case GCC_UFS_PHY_UNIPRO_CORE_CLK:
> +		freq = qcom_find_freq(ftbl_gcc_ufs_phy_unipro_core_clk_src, rate);
> +		clk_rcg_set_rate_mnd(priv->base, UFS_PHY_UNIPRO_CORE_CLK_CMD_RCGR,
> +				     freq->pre_div, freq->m, freq->n, freq->src, 8);
> +		return freq->freq;
> +	case GCC_UFS_PHY_ICE_CORE_CLK:
> +		freq = qcom_find_freq(ftbl_gcc_ufs_phy_ice_core_clk_src, rate);
> +		clk_rcg_set_rate_mnd(priv->base, UFS_PHY_ICE_CORE_CLK_CMD_RCGR,
> +				     freq->pre_div, freq->m, freq->n, freq->src, 8);
> +		return freq->freq;
> +	case GCC_UFS_PHY_PHY_AUX_CLK:
> +		clk_rcg_set_rate(priv->base, UFS_PHY_PHY_AUX_CLK_CMD_RCGR, 0, CFG_CLK_SRC_CXO);
> +		return 19200000;
>  	default:
>  		return 0;
>  	}
> @@ -106,6 +155,20 @@ static const struct gate_clk sa8775p_clks[] = {
>  
>  	/* QUP Wrapper 3 clocks */
>  	GATE_CLK(GCC_QUPV3_WRAP3_S0_CLK, 0x4b000, GCC_QUPV3_WRAP3_S0_CLK_ENA_BIT),
> +
> +	/* UFS PHY clocks */
> +	GATE_CLK(GCC_UFS_PHY_AXI_CLK, 0x83018, 1),
> +	GATE_CLK(GCC_AGGRE_UFS_PHY_AXI_CLK, 0x830d4, 1),
> +	GATE_CLK(GCC_UFS_PHY_AHB_CLK, 0x83020, 1),
> +	GATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x83064, 1),
> +	GATE_CLK(GCC_UFS_PHY_TX_SYMBOL_0_CLK, 0x83024, 1),
> +	GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_0_CLK, 0x83028, 1),
> +	GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_1_CLK, 0x830c0, 1),
> +	GATE_CLK(GCC_UFS_PHY_PHY_AUX_CLK, 0x830a4, 1),
> +	GATE_CLK(GCC_UFS_PHY_ICE_CORE_CLK, 0x8306c, 1),
> +
> +	/* EDP reference clock (used by UFS PHY) */
> +	GATE_CLK(GCC_EDP_REF_CLKREF_EN, 0x97448, 1),
>  };
>  
>  static int sa8775p_enable(struct clk *clk)
> 
> -- 
> 2.34.1
>