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dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1774686523; s=zmail; d=ziyao.cc; i=me@ziyao.cc; h=Date:Date:From:From:To:To:Cc:Cc:Subject:Subject:Message-ID:References:MIME-Version:Content-Type:In-Reply-To:Message-Id:Reply-To; bh=vZwdCGy13Tb2+/pER96TdA/awRVoabC6Q6dUQKgw42w=; b=a7GDuuPG0y5vxd66iRaU1MfOaExgkk36FBWkjyK1azRttsX3LQcyd/RB9VJgLYg7 UxJQ12NSh06VkdpOcerIiMFJFzxsPVNFGaUD3X4zaKd9X4yQkP+AYNqVdp337UV1TjC El46R54TJrdY2FtOOf5OWv2N2G4c2HQJWfGUggn4= Received: by mx.zohomail.com with SMTPS id 1774686520268677.9991877626416; Sat, 28 Mar 2026 01:28:40 -0700 (PDT) Date: Sat, 28 Mar 2026 08:28:28 +0000 From: Yao Zi To: Uros Stajic , "u-boot@lists.denx.de" Cc: Djordje Todorovic , Chao-ying Fu Subject: Re: [PATCH v6 1/7] riscv: Add initial support for P8700 SoC Message-ID: References: <20260327141029.628483-1-uros.stajic@htecgroup.com> <20260327141029.628483-2-uros.stajic@htecgroup.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260327141029.628483-2-uros.stajic@htecgroup.com> X-ZohoMailClient: External X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean On Fri, Mar 27, 2026 at 02:11:15PM +0000, Uros Stajic wrote: > From: Chao-ying Fu > > Add initial platform support for the P8700-F, a high-performance > multi-core RV64GC SoC with optional multi-cluster configuration and > hardware multithreading. > > This patch introduces the initial platform code necessary to support > the P8700 CPU in U-Boot. > > Signed-off-by: Chao-ying Fu > Signed-off-by: Uros Stajic > --- > arch/riscv/Kconfig | 8 ++ > arch/riscv/cpu/p8700/Kconfig | 14 +++ > arch/riscv/cpu/p8700/Makefile | 8 ++ > arch/riscv/cpu/p8700/cache.c | 93 +++++++++++++++++++ > arch/riscv/cpu/p8700/cpu.c | 105 ++++++++++++++++++++++ > arch/riscv/cpu/p8700/dram.c | 37 ++++++++ > arch/riscv/cpu/p8700/p8700.c | 12 +++ > arch/riscv/include/asm/arch-p8700/p8700.h | 101 +++++++++++++++++++++ > 8 files changed, 378 insertions(+) > create mode 100644 arch/riscv/cpu/p8700/Kconfig > create mode 100644 arch/riscv/cpu/p8700/Makefile > create mode 100644 arch/riscv/cpu/p8700/cache.c > create mode 100644 arch/riscv/cpu/p8700/cpu.c > create mode 100644 arch/riscv/cpu/p8700/dram.c > create mode 100644 arch/riscv/cpu/p8700/p8700.c > create mode 100644 arch/riscv/include/asm/arch-p8700/p8700.h > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > index 79867656b15..9e2cbe775d2 100644 > --- a/arch/riscv/Kconfig > +++ b/arch/riscv/Kconfig > @@ -132,6 +132,7 @@ source "arch/riscv/cpu/jh7110/Kconfig" > source "arch/riscv/cpu/k1/Kconfig" > source "arch/riscv/cpu/k230/Kconfig" > source "arch/riscv/cpu/th1520/Kconfig" > +source "arch/riscv/cpu/p8700/Kconfig" > > # architecture-specific options below > > @@ -442,6 +443,13 @@ config SBI > bool > default y if RISCV_SMODE || SPL_RISCV_SMODE > > +config RISCV_CM_BASE > + hex "RISCV CM Base Address" > + default 0x16100000 > + help > + The physical base address at which to map the Coherence Manager > + Global Configuration Registers (GCRs). > + Sorry for not raising this earlier: this sounds like a MIPS-specific component, would it make sense to move it into a MIPS/P8700-specific header? For example, arch/riscv/cpu/p8700/Kconfig. > choice > prompt "SBI support" > default SBI_V02 Regards, Yao Zi