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From: dmukhin@ford.com
To: Neil Armstrong <neil.armstrong@linaro.org>
Cc: dmukhin@ford.com, u-boot@lists.denx.de, sjg@chromium.org,
	trini@konsulko.com
Subject: Re: [PATCH v1 2/5] drivers: nvme: Implement NVMe flush command (0x0)
Date: Thu, 4 Jun 2026 20:43:08 -0700	[thread overview]
Message-ID: <aiJFzMdcCu5sAktz@kraken> (raw)
In-Reply-To: <162d730d-934a-42ea-adf6-18376971086e@linaro.org>

Hi Neil,

Thanks for your feedback!

Sorry, it took me a while to respond.

On Fri, May 29, 2026 at 09:54:32AM +0200, Neil Armstrong wrote:
[..]
> > 
> > > 
> > > The for NVMe, can it support write-through like SCSI FUA (Force Unit
> > > Access) which bypasses the cache on writes, with slower writes
> > > but safer and simpler than calling a flush before OS boot.
> > 
> > Yes, I've seen there was FUA patch [1], which was then reverted [2].
> > 
> > For our purposes, flush seems to be enough: the use case is
> > updating NVMe-backed boot counter from a custom bootflow.
> 
> OK the FUA was reverted because Bin's comment was not adressed:
> https://lore.kernel.org/u-boot/CAEUhbmU02GnqEEfuqNrSj8R5XEZkmkTUaLp1+BMbYQNdzTUZ7A@mail.gmail.com/
> 
> I would prefer having FUA added so all board could have this enabled
> and not have to update their boot flow to call flush, this was basically
> why the SCSI FUA was enabled.

I will take a look into FUA.

The problem I was solving is providing a guarantee that GPT headers
will be updated correctly on the NVMe device.

I have a new bootcount device which implements a counter backed by
GPT PTE flags (the top 16 bits) [1]

Patch [2] adds new APIs to update 16 bit flags in both primary and
backup GPT headers (the proposed write_gpt_pte() call).

This is where I originally used new flush command: to guarantee that
NVMe received all the updates before it is handed over to the OS.

[1] https://lore.kernel.org/u-boot/20260605033907.1909319-1-dmukhin@ford.com/
[2] https://lore.kernel.org/u-boot/20260605033907.1909319-3-dmukhin@ford.com/

> 
> As Bin's comment, perhaps a way would be to disable the Write Cache if
> the cache is present as init time (WCE), and it's even simpler, or
> get the enable state of the WC and use FUA if enabled.
> 
> Because the same question remains with the flush command, it's
> only valid if the WC is present and is enabled.
> 
> Thanks,
> Neil
> 
> > 
> > [1] https://lore.kernel.org/u-boot/20211019104049.v3.1.Ic581ec99f46b6dfa2e0b1922e670a333ac859e82@changeid/
> > [2] https://lore.kernel.org/u-boot/CAGi-RUL96GK5nfHx73UQQd_4sFByt3gNwqhFpHps+h58S20JwQ@mail.gmail.com/

--
Denis

  reply	other threads:[~2026-06-05  3:43 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-05-28  1:20 [PATCH v1 0/5] nvme: few fixups dmukhin
2026-05-28  1:20 ` [PATCH v1 1/5] drivers: nvme: Log I/O timeouts dmukhin
2026-05-28  9:11   ` Neil Armstrong
2026-05-29  3:25     ` dmukhin
2026-05-28  1:20 ` [PATCH v1 2/5] drivers: nvme: Implement NVMe flush command (0x0) dmukhin
2026-05-28  9:28   ` Neil Armstrong
2026-05-29  3:36     ` dmukhin
2026-05-29  7:54       ` Neil Armstrong
2026-06-05  3:43         ` dmukhin [this message]
2026-06-05  8:01           ` Neil Armstrong
2026-05-28  1:20 ` [PATCH v1 3/5] cmd: nvme: Add flush support dmukhin
2026-05-28  9:29   ` Neil Armstrong
2026-05-29  3:36     ` dmukhin
2026-05-28  1:20 ` [PATCH v1 4/5] drivers: nvme: Export nvme_shutdown symbol dmukhin
2026-05-28  1:20 ` [PATCH v1 5/5] docs: nvme: Update QEMU command for testing dmukhin

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