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charset=us-ascii Content-Disposition: inline In-Reply-To: <20261001152514.vkcl3mw7gaz67xqo@skbuf> X-BeenThere: u-boot@lists.u-boot-project.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.u-boot-project.org Hi Vladimir, On Thu, Oct 01, 2026 at 06:25:14PM +0300, Vladimir Oltean wrote: > "A reference clock from which 10.3125 GHz clock net can be derived" > sounds like it includes 156.25 MHz too, but the code is hardcoded for > 161.1328125 MHz. ok, so my draft for v6, I'll use: - PLLS needs a 161.1328125 MHz reference clock, for which 2x40g, 40g4x10g and 100g4x10g program it. It can come from the SD1 PLLS reference clock input, or from the PLLF one with SRDS_INTRA_REF_CLK_S1=1. A 156.25 MHz PLLS reference clock is not supported. With protocol 13 PLLS is not in use, so nothing checks that clock before these modes start it. Thanks, Vincent