Re: [PATCH v5 18/20] doc: arch: Add documentation for LoongArch

[Yao Zi <me@ziyao.cc>]

On Fri, Oct 16, 2026 at 09:35:16AM +0200, Heinrich Schuchardt wrote:
> On 10/16/26 08:54, Yao Zi wrote:
> > Add a brief introduction to LoongArch architecture, some notes on the
> > implementation, and the toolchain supporting status.
> > 
> > Signed-off-by: Yao Zi <me@ziyao.cc>
> > ---
> > 
> > New patch, no changes since v3
> > ---
> >   doc/arch/index.rst     |  1 +
> >   doc/arch/loongarch.rst | 30 ++++++++++++++++++++++++++++++
> >   2 files changed, 31 insertions(+)
> >   create mode 100644 doc/arch/loongarch.rst

...

> > diff --git a/doc/arch/loongarch.rst b/doc/arch/loongarch.rst
> > new file mode 100644
> > index 000000000000..d744db6a4999
> > --- /dev/null
> > +++ b/doc/arch/loongarch.rst
> > @@ -0,0 +1,30 @@
> > +.. SPDX-License-Identifier: GPL-2.0-or-later
> > +.. Copyright (C) 2026 Yao Zi <me@ziyao.cc>
> > +
> > +LoongArch
> > +=========
> > +
> > +LoongArch is a RISC ISA developed by Loongson Technology. It currently defines
> > +three variants: a reduced 32-bit version (LA32R), a standard 32-bit version
> > +(LA32S) for embedded devices, and a 64-bit version (LA64).
> > +
> > +Notes
> > +-----
> > +
> > +1. Currently U-Boot only runs on LA64 variant with the highest privilege level
> > +   (PLV0).
> > +
> > +2. LA64 is distinguished with 32-bit LoongArch with CONFIG_ARCH_LA64.
> 
> Thank you for the helpful documentation. Just some nits.
> 
> The prepositions should be
> 
> LA64 is distinguished from 32-bit LoongArch by CONFIG_ARCH_LA64.
> 
> Maybe:
> 
> "CONFIG_ARCH_LA64=y selects support for the LA64 instruction set
> architecture."
> 
> > +
> > +3. U-Boot expects hardware-maintained coherency between I-D cache. Cache
> 
> Maybe
> 
> "U-Boot requires hardware-maintained coherency of different levels of
> instruction and data caches."
> 
> > +   topology is probed through CPUCFG; L2 and L3 caches, if present, must be
> 
> Maybe
> 
> "It determines the cache topology by reading CPUCFG registers before
> enabling the caches."

I think it's too detailed and not very helpful to mention the order
between probing cache topology and enabling the cache? i.e., I would
prefer,

> It determines the cache topology by reading CPUCFG registers.

The rest of your suggestions look good to me, thanks.

> Best regards
> 
> Heinrich

Regards,
Yao Zi

> > +   unified or instruction-only. This is true for all commercial LA64 hardware.
> > +   Refer to arch/loongarch/lib/cache.c for further description.