* [U-Boot] [PATCH 1/5] ARM: cache: Move the cp15 CR register read before flushing the cache.
@ 2012-05-17 9:52 R Sricharan
2012-05-29 14:54 ` R, Sricharan
2012-07-07 12:00 ` Albert ARIBAUD
0 siblings, 2 replies; 6+ messages in thread
From: R Sricharan @ 2012-05-17 9:52 UTC (permalink / raw)
To: u-boot
The following is the cleanup sequence in arch/arm/cpu/armv7/cpu.c
int cleanup_before_linux(void)
{
...
...
dcache_disable();
v7_outer_cache_disable();
invalidate_dcache_all();
}
1) invalidate_dcache_all call expects that all the caches has been
flushed, invalidated and there are no dirty entries prior to its
execution. In the above sequence dcache_disable() flushes, invalidates
the caches and turns off the mmu. But after it cleanups the cache
and before the mmu is disabled there is a cp_delay() function which
has STR instruction. On certain cores like the cortex-a15, cache hit
and a write can happen to a cache line even when the dcache is
disabled. So the above mentioned STR instruction creates a dirty entry
after cleaning. The mmu gets disabled after this.
2) invalidate_dcache_all invalidates the cache lines. Again on
cores like cortex-a15, invalidate instruction flushes the dirty
line as well. So some times the dirty line from sequence 1
can corrupt the memory resulting in a crash.
Fixing this by moving the get_cr() and cp_delay() calls before
cleaning up the cache, thus avoiding the dirty entry.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
---
arch/arm/lib/cache-cp15.c | 6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index e6c3eae..939de10 100644
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -115,17 +115,17 @@ static void cache_disable(uint32_t cache_bit)
{
uint32_t reg;
+ reg = get_cr();
+ cp_delay();
+
if (cache_bit == CR_C) {
/* if cache isn;t enabled no need to disable */
- reg = get_cr();
if ((reg & CR_C) != CR_C)
return;
/* if disabling data cache, disable mmu too */
cache_bit |= CR_M;
flush_dcache_all();
}
- reg = get_cr();
- cp_delay();
set_cr(reg & ~cache_bit);
}
#endif
--
1.7.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 1/5] ARM: cache: Move the cp15 CR register read before flushing the cache.
2012-05-17 9:52 [U-Boot] [PATCH 1/5] ARM: cache: Move the cp15 CR register read before flushing the cache R Sricharan
@ 2012-05-29 14:54 ` R, Sricharan
2012-06-05 8:58 ` Sricharan R
2012-07-07 12:00 ` Albert ARIBAUD
1 sibling, 1 reply; 6+ messages in thread
From: R, Sricharan @ 2012-05-29 14:54 UTC (permalink / raw)
To: u-boot
Hi Albert,
Are you planning to take up the below patch ?
Thanks,
Sricharan
On Thu, May 17, 2012 at 3:22 PM, R Sricharan <r.sricharan@ti.com> wrote:
> The following is the cleanup sequence in arch/arm/cpu/armv7/cpu.c
>
> int cleanup_before_linux(void)
> {
> ?...
> ?...
> ?dcache_disable();
> ?v7_outer_cache_disable();
> ?invalidate_dcache_all();
> }
>
> ?1) invalidate_dcache_all call expects that all the caches has been
> ?flushed, invalidated and there are no dirty entries prior to its
> ?execution. ?In the above sequence dcache_disable() flushes, invalidates
> ?the caches and turns off the ?mmu. But after it cleanups the cache
> ?and before the mmu is disabled ?there is a cp_delay() function which
> ?has STR instruction. On certain cores like the cortex-a15, cache hit
> ?and a write can happen to a cache line even when the dcache is
> ?disabled. So the above mentioned STR instruction creates a dirty entry
> ?after cleaning. The mmu gets disabled after this.
>
> ?2) invalidate_dcache_all invalidates the cache lines. Again on
> ?cores like cortex-a15, invalidate instruction flushes the dirty
> ?line as well. So some times the dirty line from sequence 1
> ?can corrupt the memory resulting in a crash.
>
> ?Fixing this by moving the get_cr() and cp_delay() calls before
> ?cleaning up the cache, thus avoiding the dirty entry.
>
> Signed-off-by: R Sricharan <r.sricharan@ti.com>
> ---
> ?arch/arm/lib/cache-cp15.c | ? ?6 +++---
> ?1 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
> index e6c3eae..939de10 100644
> --- a/arch/arm/lib/cache-cp15.c
> +++ b/arch/arm/lib/cache-cp15.c
> @@ -115,17 +115,17 @@ static void cache_disable(uint32_t cache_bit)
> ?{
> ? ? ? ?uint32_t reg;
>
> + ? ? ? reg = get_cr();
> + ? ? ? cp_delay();
> +
> ? ? ? ?if (cache_bit == CR_C) {
> ? ? ? ? ? ? ? ?/* if cache isn;t enabled no need to disable */
> - ? ? ? ? ? ? ? reg = get_cr();
> ? ? ? ? ? ? ? ?if ((reg & CR_C) != CR_C)
> ? ? ? ? ? ? ? ? ? ? ? ?return;
> ? ? ? ? ? ? ? ?/* if disabling data cache, disable mmu too */
> ? ? ? ? ? ? ? ?cache_bit |= CR_M;
> ? ? ? ? ? ? ? ?flush_dcache_all();
> ? ? ? ?}
> - ? ? ? reg = get_cr();
> - ? ? ? cp_delay();
> ? ? ? ?set_cr(reg & ~cache_bit);
> ?}
> ?#endif
> --
> 1.7.1
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 1/5] ARM: cache: Move the cp15 CR register read before flushing the cache.
2012-05-29 14:54 ` R, Sricharan
@ 2012-06-05 8:58 ` Sricharan R
2012-06-05 20:25 ` Marek Vasut
0 siblings, 1 reply; 6+ messages in thread
From: Sricharan R @ 2012-06-05 8:58 UTC (permalink / raw)
To: u-boot
Ping..
Thanks,
Sricharan
> -----Original Message-----
> From: R, Sricharan [mailto:r.sricharan at ti.com]
> Sent: Tuesday, May 29, 2012 8:24 PM
> To: U-Boot at lists.denx.de; albert.u.boot at aribaud.net
> Cc: trini at ti.com
> Subject: Re: [U-Boot] [PATCH 1/5] ARM: cache: Move the cp15 CR register
> read before flushing the cache.
>
> Hi Albert,
> Are you planning to take up the below patch ?
>
> Thanks,
> Sricharan
>
> On Thu, May 17, 2012 at 3:22 PM, R Sricharan <r.sricharan@ti.com>
> wrote:
> > The following is the cleanup sequence in arch/arm/cpu/armv7/cpu.c
> >
> > int cleanup_before_linux(void)
> > {
> > ?...
> > ?...
> > ?dcache_disable();
> > ?v7_outer_cache_disable();
> > ?invalidate_dcache_all();
> > }
> >
> > ?1) invalidate_dcache_all call expects that all the caches has been
> > ?flushed, invalidated and there are no dirty entries prior to its
> > ?execution. ?In the above sequence dcache_disable() flushes,
> invalidates
> > ?the caches and turns off the ?mmu. But after it cleanups the cache
> > ?and before the mmu is disabled ?there is a cp_delay() function which
> > ?has STR instruction. On certain cores like the cortex-a15, cache hit
> > ?and a write can happen to a cache line even when the dcache is
> > ?disabled. So the above mentioned STR instruction creates a dirty
> entry
> > ?after cleaning. The mmu gets disabled after this.
> >
> > ?2) invalidate_dcache_all invalidates the cache lines. Again on
> > ?cores like cortex-a15, invalidate instruction flushes the dirty
> > ?line as well. So some times the dirty line from sequence 1
> > ?can corrupt the memory resulting in a crash.
> >
> > ?Fixing this by moving the get_cr() and cp_delay() calls before
> > ?cleaning up the cache, thus avoiding the dirty entry.
> >
> > Signed-off-by: R Sricharan <r.sricharan@ti.com>
> > ---
> > ?arch/arm/lib/cache-cp15.c | ? ?6 +++---
> > ?1 files changed, 3 insertions(+), 3 deletions(-)
> >
> > diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
> > index e6c3eae..939de10 100644
> > --- a/arch/arm/lib/cache-cp15.c
> > +++ b/arch/arm/lib/cache-cp15.c
> > @@ -115,17 +115,17 @@ static void cache_disable(uint32_t cache_bit)
> > ?{
> > ? ? ? ?uint32_t reg;
> >
> > + ? ? ? reg = get_cr();
> > + ? ? ? cp_delay();
> > +
> > ? ? ? ?if (cache_bit == CR_C) {
> > ? ? ? ? ? ? ? ?/* if cache isn;t enabled no need to disable */
> > - ? ? ? ? ? ? ? reg = get_cr();
> > ? ? ? ? ? ? ? ?if ((reg & CR_C) != CR_C)
> > ? ? ? ? ? ? ? ? ? ? ? ?return;
> > ? ? ? ? ? ? ? ?/* if disabling data cache, disable mmu too */
> > ? ? ? ? ? ? ? ?cache_bit |= CR_M;
> > ? ? ? ? ? ? ? ?flush_dcache_all();
> > ? ? ? ?}
> > - ? ? ? reg = get_cr();
> > - ? ? ? cp_delay();
> > ? ? ? ?set_cr(reg & ~cache_bit);
> > ?}
> > ?#endif
> > --
> > 1.7.1
> >
> > _______________________________________________
> > U-Boot mailing list
> > U-Boot at lists.denx.de
> > http://lists.denx.de/mailman/listinfo/u-boot
^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 1/5] ARM: cache: Move the cp15 CR register read before flushing the cache.
2012-06-05 8:58 ` Sricharan R
@ 2012-06-05 20:25 ` Marek Vasut
2012-06-07 5:05 ` R, Sricharan
0 siblings, 1 reply; 6+ messages in thread
From: Marek Vasut @ 2012-06-05 20:25 UTC (permalink / raw)
To: u-boot
Dear Sricharan R,
> Ping..
+1
> Thanks,
> Sricharan
>
> > -----Original Message-----
> > From: R, Sricharan [mailto:r.sricharan at ti.com]
> > Sent: Tuesday, May 29, 2012 8:24 PM
> > To: U-Boot at lists.denx.de; albert.u.boot at aribaud.net
> > Cc: trini at ti.com
> > Subject: Re: [U-Boot] [PATCH 1/5] ARM: cache: Move the cp15 CR register
> > read before flushing the cache.
> >
> > Hi Albert,
> >
> > Are you planning to take up the below patch ?
> >
> > Thanks,
> >
> > Sricharan
> >
> > On Thu, May 17, 2012 at 3:22 PM, R Sricharan <r.sricharan@ti.com>
> >
> > wrote:
> > > The following is the cleanup sequence in arch/arm/cpu/armv7/cpu.c
> > >
> > > int cleanup_before_linux(void)
> > > {
> > > ...
> > > ...
> > > dcache_disable();
> > > v7_outer_cache_disable();
> > > invalidate_dcache_all();
> > > }
> > >
> > > 1) invalidate_dcache_all call expects that all the caches has been
> > > flushed, invalidated and there are no dirty entries prior to its
> > > execution. In the above sequence dcache_disable() flushes,
> >
> > invalidates
> >
> > > the caches and turns off the mmu. But after it cleanups the cache
> > > and before the mmu is disabled there is a cp_delay() function which
> > > has STR instruction. On certain cores like the cortex-a15, cache hit
> > > and a write can happen to a cache line even when the dcache is
> > > disabled. So the above mentioned STR instruction creates a dirty
> >
> > entry
> >
> > > after cleaning. The mmu gets disabled after this.
> > >
> > > 2) invalidate_dcache_all invalidates the cache lines. Again on
> > > cores like cortex-a15, invalidate instruction flushes the dirty
> > > line as well. So some times the dirty line from sequence 1
> > > can corrupt the memory resulting in a crash.
> > >
> > > Fixing this by moving the get_cr() and cp_delay() calls before
> > > cleaning up the cache, thus avoiding the dirty entry.
> > >
> > > Signed-off-by: R Sricharan <r.sricharan@ti.com>
> > > ---
> > > arch/arm/lib/cache-cp15.c | 6 +++---
> > > 1 files changed, 3 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
> > > index e6c3eae..939de10 100644
> > > --- a/arch/arm/lib/cache-cp15.c
> > > +++ b/arch/arm/lib/cache-cp15.c
> > > @@ -115,17 +115,17 @@ static void cache_disable(uint32_t cache_bit)
> > > {
> > > uint32_t reg;
> > >
> > > + reg = get_cr();
> > > + cp_delay();
> > > +
> > > if (cache_bit == CR_C) {
> > > /* if cache isn;t enabled no need to disable */
> > > - reg = get_cr();
> > > if ((reg & CR_C) != CR_C)
> > > return;
> > > /* if disabling data cache, disable mmu too */
> > > cache_bit |= CR_M;
> > > flush_dcache_all();
> > > }
> > > - reg = get_cr();
> > > - cp_delay();
> > > set_cr(reg & ~cache_bit);
> > > }
> > > #endif
> > > --
> > > 1.7.1
> > >
> > > _______________________________________________
> > > U-Boot mailing list
> > > U-Boot at lists.denx.de
> > > http://lists.denx.de/mailman/listinfo/u-boot
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 1/5] ARM: cache: Move the cp15 CR register read before flushing the cache.
2012-06-05 20:25 ` Marek Vasut
@ 2012-06-07 5:05 ` R, Sricharan
0 siblings, 0 replies; 6+ messages in thread
From: R, Sricharan @ 2012-06-07 5:05 UTC (permalink / raw)
To: u-boot
Hi Marek Vasut,
>> Ping..
>
> +1
Thanks..
Thanks,
Sricharan
^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 1/5] ARM: cache: Move the cp15 CR register read before flushing the cache.
2012-05-17 9:52 [U-Boot] [PATCH 1/5] ARM: cache: Move the cp15 CR register read before flushing the cache R Sricharan
2012-05-29 14:54 ` R, Sricharan
@ 2012-07-07 12:00 ` Albert ARIBAUD
1 sibling, 0 replies; 6+ messages in thread
From: Albert ARIBAUD @ 2012-07-07 12:00 UTC (permalink / raw)
To: u-boot
Hi R Sricharan,
On Thu, 17 May 2012 15:22:54 +0530, R Sricharan <r.sricharan@ti.com>
wrote:
> The following is the cleanup sequence in arch/arm/cpu/armv7/cpu.c
>
> int cleanup_before_linux(void)
> {
> ...
> ...
> dcache_disable();
> v7_outer_cache_disable();
> invalidate_dcache_all();
> }
>
> 1) invalidate_dcache_all call expects that all the caches has been
> flushed, invalidated and there are no dirty entries prior to its
> execution. In the above sequence dcache_disable() flushes,
> invalidates the caches and turns off the mmu. But after it cleanups
> the cache and before the mmu is disabled there is a cp_delay()
> function which has STR instruction. On certain cores like the
> cortex-a15, cache hit and a write can happen to a cache line even
> when the dcache is disabled. So the above mentioned STR instruction
> creates a dirty entry after cleaning. The mmu gets disabled after
> this.
>
> 2) invalidate_dcache_all invalidates the cache lines. Again on
> cores like cortex-a15, invalidate instruction flushes the dirty
> line as well. So some times the dirty line from sequence 1
> can corrupt the memory resulting in a crash.
>
> Fixing this by moving the get_cr() and cp_delay() calls before
> cleaning up the cache, thus avoiding the dirty entry.
>
> Signed-off-by: R Sricharan <r.sricharan@ti.com>
> ---
Applied to u-boot-arm/master, thanks.
Amicalement,
--
Albert.
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2012-07-07 12:00 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2012-05-17 9:52 [U-Boot] [PATCH 1/5] ARM: cache: Move the cp15 CR register read before flushing the cache R Sricharan
2012-05-29 14:54 ` R, Sricharan
2012-06-05 8:58 ` Sricharan R
2012-06-05 20:25 ` Marek Vasut
2012-06-07 5:05 ` R, Sricharan
2012-07-07 12:00 ` Albert ARIBAUD
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox