[PATCH 0/3] clk: imx8mn: miscellaneous cleanups and bug fixes

[PATCH 0/3] clk: imx8mn: miscellaneous cleanups and bug fixes

[Dario Binacchi]

This series is a backport of the linux seris [1]. Like that series, this
one was also tested on the BSH SystemMaster (SMM) S2 board.

[1] https://lore.kernel.org/all/20221117113637.1978703-1-dario.binacchi@amarulasolutions.com


Dario Binacchi (3):
  clk: imx8mn: rename vpu_pll to m7_alt_pll
  clk: imx: rename video_pll1 to video_pll
  clk: imx8mn: fix imx8mn_enet_phy_sels clocks list

 drivers/clk/imx/clk-imx8mn.c | 22 +++++++++++-----------
 1 file changed, 11 insertions(+), 11 deletions(-)

-- 
2.32.0

[PATCH 1/3] clk: imx8mn: rename vpu_pll to m7_alt_pll

[Dario Binacchi]

[backport from linux commit a429c60baefd95ab43a2ce7f25d5b2d7a2e431df]

The IMX8MN platform does not have any video processing unit (VPU), and
indeed in the reference manual (document IMX8MNRM Rev 2, 07/2022) there
is no occurrence of its pll. From an analysis of the code and the RM
itself, I think vpu pll is used instead of m7 alternate pll, probably
for copy and paste of code taken from modules of similar architectures.

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
---

 drivers/clk/imx/clk-imx8mn.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index 35e0d935d390..86fe30ae6662 100644
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -83,7 +83,7 @@ static const char *imx8mn_i2c3_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_
 static const char *imx8mn_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
 					 "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
 
-static const char *imx8mn_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_160m", "vpu_pll_out",
+static const char *imx8mn_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_160m", "m7_alt_pll",
 					 "sys_pll2_125m", "sys_pll3_out", "sys_pll1_80m", "sys_pll2_166m", };
 
 static const char *imx8mn_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
-- 
2.32.0

[PATCH 2/3] clk: imx: rename video_pll1 to video_pll

[Dario Binacchi]

[backport from linux commit bedcf9d1dcf88ed38731f0ac9620e5a421e1e9d6]

Unlike audio_pll1 and audio_pll2, there is no video_pll2. Further, the
name used in the RM is video_pll. So, let's rename "video_pll1" to
"video_pll" to be consistent with the RM and avoid misunderstandings.

No functional changes intended.

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
---

 drivers/clk/imx/clk-imx8mn.c | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index 86fe30ae6662..a2c7c63ef74d 100644
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -28,20 +28,20 @@ static const char *imx8mn_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll
 					"sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "sys_pll3_out", };
 
 static const char *imx8mn_ahb_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_800m", "sys_pll1_400m",
-					"sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", };
+					"sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", "video_pll_out", };
 
 static const char *imx8mn_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_250m",
-					     "sys_pll2_200m", "audio_pll1_out", "video_pll1_out", "sys_pll3_out", };
+					     "sys_pll2_200m", "audio_pll1_out", "video_pll_out", "sys_pll3_out", };
 
 #ifndef CONFIG_SPL_BUILD
 static const char *imx8mn_enet_ref_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll2_50m", "sys_pll2_100m",
-					     "sys_pll1_160m", "audio_pll1_out", "video_pll1_out", "clk_ext4", };
+					     "sys_pll1_160m", "audio_pll1_out", "video_pll_out", "clk_ext4", };
 
 static const char *imx8mn_enet_timer_sels[] = {"clock-osc-24m", "sys_pll2_100m", "audio_pll1_out", "clk_ext1", "clk_ext2",
-					       "clk_ext3", "clk_ext4", "video_pll1_out", };
+					       "clk_ext3", "clk_ext4", "video_pll_out", };
 
 static const char *imx8mn_enet_phy_sels[] = {"clock-osc-24m", "sys_pll2_50m", "sys_pll2_125m", "sys_pll2_200m",
-					     "sys_pll2_500m", "video_pll1_out", "audio_pll2_out", };
+					     "sys_pll2_500m", "video_pll_out", "audio_pll2_out", };
 #endif
 
 static const char *imx8mn_nand_usdhc_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_200m",
@@ -72,16 +72,16 @@ static const char *imx8mn_ecspi3_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1
 #endif
 
 static const char *imx8mn_i2c1_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
-					 "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
+					 "video_pll_out", "audio_pll2_out", "sys_pll1_133m", };
 
 static const char *imx8mn_i2c2_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
-					 "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
+					 "video_pll_out", "audio_pll2_out", "sys_pll1_133m", };
 
 static const char *imx8mn_i2c3_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
-					 "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
+					 "video_pll_out", "audio_pll2_out", "sys_pll1_133m", };
 
 static const char *imx8mn_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
-					 "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
+					 "video_pll_out", "audio_pll2_out", "sys_pll1_133m", };
 
 static const char *imx8mn_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_160m", "m7_alt_pll",
 					 "sys_pll2_125m", "sys_pll3_out", "sys_pll1_80m", "sys_pll2_166m", };
@@ -94,7 +94,7 @@ static const char *imx8mn_qspi_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_
 
 static const char * const imx8mn_nand_sels[] = {"osc_24m", "sys_pll2_500m", "audio_pll1_out",
 						"sys_pll1_400m", "audio_pll2_out", "sys_pll3_out",
-						"sys_pll2_250m", "video_pll1_out", };
+						"sys_pll2_250m", "video_pll_out", };
 
 static const char * const imx8mn_usb_core_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m",
 						"sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
-- 
2.32.0

[PATCH 3/3] clk: imx8mn: fix imx8mn_enet_phy_sels clocks list

[Dario Binacchi]

[backport from linux commit 2626cf67f20b28446dfc3a5b9493dd535cdb747b]

According to the "Clock Root" table of the reference manual (document
IMX8MNRM Rev 2, 07/2022):

     Clock Root         offset     Source Select (CCM_TARGET_ROOTn[MUX])
        ...              ...                    ...
 ENET_PHY_REF_CLK_ROOT  0xAA80            000 - 24M_REF_CLK
                                          001 - SYSTEM_PLL2_DIV20
                                          010 - SYSTEM_PLL2_DIV8
                                          011 - SYSTEM_PLL2_DIV5
                                          100 - SYSTEM_PLL2_DIV2
                                          101 - AUDIO_PLL1_CLK
                                          110 - VIDEO_PLL_CLK
                                          111 - AUDIO_PLL2_CLK
        ...              ...                    ...

while the imx8mn_enet_phy_sels list didn't contained audio_pll1_out for
source select bits 101b.

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>

---

 drivers/clk/imx/clk-imx8mn.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index a2c7c63ef74d..692823e74b88 100644
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -41,7 +41,7 @@ static const char *imx8mn_enet_timer_sels[] = {"clock-osc-24m", "sys_pll2_100m",
 					       "clk_ext3", "clk_ext4", "video_pll_out", };
 
 static const char *imx8mn_enet_phy_sels[] = {"clock-osc-24m", "sys_pll2_50m", "sys_pll2_125m", "sys_pll2_200m",
-					     "sys_pll2_500m", "video_pll_out", "audio_pll2_out", };
+					     "sys_pll2_500m", "audio_pll1_out", "video_pll_out", "audio_pll2_out", };
 #endif
 
 static const char *imx8mn_nand_usdhc_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_200m",
-- 
2.32.0

Re: [PATCH 1/3] clk: imx8mn: rename vpu_pll to m7_alt_pll

[Sean Anderson]

On 12/19/22 06:31, Dario Binacchi wrote:
> [backport from linux commit a429c60baefd95ab43a2ce7f25d5b2d7a2e431df]
> 
> The IMX8MN platform does not have any video processing unit (VPU), and
> indeed in the reference manual (document IMX8MNRM Rev 2, 07/2022) there
> is no occurrence of its pll. From an analysis of the code and the RM
> itself, I think vpu pll is used instead of m7 alternate pll, probably
> for copy and paste of code taken from modules of similar architectures.
> 
> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
> ---
> 
>   drivers/clk/imx/clk-imx8mn.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
> index 35e0d935d390..86fe30ae6662 100644
> --- a/drivers/clk/imx/clk-imx8mn.c
> +++ b/drivers/clk/imx/clk-imx8mn.c
> @@ -83,7 +83,7 @@ static const char *imx8mn_i2c3_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_
>   static const char *imx8mn_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
>   					 "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
>   
> -static const char *imx8mn_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_160m", "vpu_pll_out",
> +static const char *imx8mn_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_160m", "m7_alt_pll",
>   					 "sys_pll2_125m", "sys_pll3_out", "sys_pll1_80m", "sys_pll2_166m", };
>   
>   static const char *imx8mn_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",

Acked-by: Sean Anderson <seanga2@gmail.com>

Re: [PATCH 2/3] clk: imx: rename video_pll1 to video_pll

[Sean Anderson]

On 12/19/22 06:31, Dario Binacchi wrote:
> [backport from linux commit bedcf9d1dcf88ed38731f0ac9620e5a421e1e9d6]
> 
> Unlike audio_pll1 and audio_pll2, there is no video_pll2. Further, the
> name used in the RM is video_pll. So, let's rename "video_pll1" to
> "video_pll" to be consistent with the RM and avoid misunderstandings.
> 
> No functional changes intended.
> 
> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
> ---
> 
>   drivers/clk/imx/clk-imx8mn.c | 20 ++++++++++----------
>   1 file changed, 10 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
> index 86fe30ae6662..a2c7c63ef74d 100644
> --- a/drivers/clk/imx/clk-imx8mn.c
> +++ b/drivers/clk/imx/clk-imx8mn.c
> @@ -28,20 +28,20 @@ static const char *imx8mn_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll
>   					"sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "sys_pll3_out", };
>   
>   static const char *imx8mn_ahb_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_800m", "sys_pll1_400m",
> -					"sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", };
> +					"sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", "video_pll_out", };
>   
>   static const char *imx8mn_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_250m",
> -					     "sys_pll2_200m", "audio_pll1_out", "video_pll1_out", "sys_pll3_out", };
> +					     "sys_pll2_200m", "audio_pll1_out", "video_pll_out", "sys_pll3_out", };
>   
>   #ifndef CONFIG_SPL_BUILD
>   static const char *imx8mn_enet_ref_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll2_50m", "sys_pll2_100m",
> -					     "sys_pll1_160m", "audio_pll1_out", "video_pll1_out", "clk_ext4", };
> +					     "sys_pll1_160m", "audio_pll1_out", "video_pll_out", "clk_ext4", };
>   
>   static const char *imx8mn_enet_timer_sels[] = {"clock-osc-24m", "sys_pll2_100m", "audio_pll1_out", "clk_ext1", "clk_ext2",
> -					       "clk_ext3", "clk_ext4", "video_pll1_out", };
> +					       "clk_ext3", "clk_ext4", "video_pll_out", };
>   
>   static const char *imx8mn_enet_phy_sels[] = {"clock-osc-24m", "sys_pll2_50m", "sys_pll2_125m", "sys_pll2_200m",
> -					     "sys_pll2_500m", "video_pll1_out", "audio_pll2_out", };
> +					     "sys_pll2_500m", "video_pll_out", "audio_pll2_out", };
>   #endif
>   
>   static const char *imx8mn_nand_usdhc_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_200m",
> @@ -72,16 +72,16 @@ static const char *imx8mn_ecspi3_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1
>   #endif
>   
>   static const char *imx8mn_i2c1_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
> -					 "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
> +					 "video_pll_out", "audio_pll2_out", "sys_pll1_133m", };
>   
>   static const char *imx8mn_i2c2_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
> -					 "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
> +					 "video_pll_out", "audio_pll2_out", "sys_pll1_133m", };
>   
>   static const char *imx8mn_i2c3_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
> -					 "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
> +					 "video_pll_out", "audio_pll2_out", "sys_pll1_133m", };
>   
>   static const char *imx8mn_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
> -					 "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
> +					 "video_pll_out", "audio_pll2_out", "sys_pll1_133m", };
>   
>   static const char *imx8mn_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_160m", "m7_alt_pll",
>   					 "sys_pll2_125m", "sys_pll3_out", "sys_pll1_80m", "sys_pll2_166m", };
> @@ -94,7 +94,7 @@ static const char *imx8mn_qspi_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_
>   
>   static const char * const imx8mn_nand_sels[] = {"osc_24m", "sys_pll2_500m", "audio_pll1_out",
>   						"sys_pll1_400m", "audio_pll2_out", "sys_pll3_out",
> -						"sys_pll2_250m", "video_pll1_out", };
> +						"sys_pll2_250m", "video_pll_out", };
>   
>   static const char * const imx8mn_usb_core_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m",
>   						"sys_pll2_100m", "sys_pll2_200m", "clk_ext2",

Acked-by: Sean Anderson <seanga2@gmail.com>

Re: [PATCH 3/3] clk: imx8mn: fix imx8mn_enet_phy_sels clocks list

[Sean Anderson]

On 12/19/22 06:31, Dario Binacchi wrote:
> [backport from linux commit 2626cf67f20b28446dfc3a5b9493dd535cdb747b]
> 
> According to the "Clock Root" table of the reference manual (document
> IMX8MNRM Rev 2, 07/2022):
> 
>       Clock Root         offset     Source Select (CCM_TARGET_ROOTn[MUX])
>          ...              ...                    ...
>   ENET_PHY_REF_CLK_ROOT  0xAA80            000 - 24M_REF_CLK
>                                            001 - SYSTEM_PLL2_DIV20
>                                            010 - SYSTEM_PLL2_DIV8
>                                            011 - SYSTEM_PLL2_DIV5
>                                            100 - SYSTEM_PLL2_DIV2
>                                            101 - AUDIO_PLL1_CLK
>                                            110 - VIDEO_PLL_CLK
>                                            111 - AUDIO_PLL2_CLK
>          ...              ...                    ...
> 
> while the imx8mn_enet_phy_sels list didn't contained audio_pll1_out for
> source select bits 101b.
> 
> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
> 
> ---
> 
>   drivers/clk/imx/clk-imx8mn.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
> index a2c7c63ef74d..692823e74b88 100644
> --- a/drivers/clk/imx/clk-imx8mn.c
> +++ b/drivers/clk/imx/clk-imx8mn.c
> @@ -41,7 +41,7 @@ static const char *imx8mn_enet_timer_sels[] = {"clock-osc-24m", "sys_pll2_100m",
>   					       "clk_ext3", "clk_ext4", "video_pll_out", };
>   
>   static const char *imx8mn_enet_phy_sels[] = {"clock-osc-24m", "sys_pll2_50m", "sys_pll2_125m", "sys_pll2_200m",
> -					     "sys_pll2_500m", "video_pll_out", "audio_pll2_out", };
> +					     "sys_pll2_500m", "audio_pll1_out", "video_pll_out", "audio_pll2_out", };
>   #endif
>   
>   static const char *imx8mn_nand_usdhc_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_200m",

Acked-by: Sean Anderson <seanga2@gmail.com>

Re: [PATCH 0/3] clk: imx8mn: miscellaneous cleanups and bug fixes

[Sean Anderson]

On Mon, 19 Dec 2022 12:31:23 +0100, Dario Binacchi wrote:
> This series is a backport of the linux seris [1]. Like that series, this
> one was also tested on the BSH SystemMaster (SMM) S2 board.
> 
> [1] https://lore.kernel.org/all/20221117113637.1978703-1-dario.binacchi@amarulasolutions.com
> 
> 
> Dario Binacchi (3):
>   clk: imx8mn: rename vpu_pll to m7_alt_pll
>   clk: imx: rename video_pll1 to video_pll
>   clk: imx8mn: fix imx8mn_enet_phy_sels clocks list
> 
> [...]

Applied, thanks!

[1/3] clk: imx8mn: rename vpu_pll to m7_alt_pll
      commit: 3724850d606e41c4e9014af20905742a477e6951
[2/3] clk: imx: rename video_pll1 to video_pll
      commit: 7b0ac6ac8b16c7ba4d90817938b34dcd60133248
[3/3] clk: imx8mn: fix imx8mn_enet_phy_sels clocks list
      commit: 67f46e29d2006ac56faa5a5ed70e43b317094d23

Best regards,
-- 
Sean Anderson <seanga2@gmail.com>