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From: "Chee, Tien Fong" <tien.fong.chee@altera.com>
To: Chen Huei Lok <chen.huei.lok@altera.com>, u-boot@lists.denx.de
Cc: Tom Rini <trini@konsulko.com>, Marek Vasut <marex@denx.de>,
	Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>,
	Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>,
	Boon Khai Ng <boon.khai.ng@altera.com>,
	Kok Kiang Hea <kok.kiang.hea@altera.com>
Subject: Re: [PATCH v4 06/15] ddr: altera: n5x: set DDR init progress bit for watchdog recovery
Date: Wed, 21 Oct 2026 10:18:00 +0800	[thread overview]
Message-ID: <baf2c25c-e788-449d-95dd-c8d0edddd80e@altera.com> (raw)
In-Reply-To: <20261016044047.21496-7-chen.huei.lok@altera.com>

On 16/10/2026 12:40 pm, Chen Huei Lok wrote:
> From: Tien Fong Chee <tien.fong.chee@altera.com>
>
> Bit[30] of the boot scratch cold 8 register tracks DDR init progress. SDM
> inspects it when the watchdog fires due to a DDR init hang, so that it can
> run a clean reset of the DDR subsystem before the next attempt.
>
> Set the bit when SDRAM init starts and clear it once the basic memory test
> has passed.
>
> Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
> Signed-off-by: Chen Huei Lok <chen.huei.lok@altera.com>
> ---
>   drivers/ddr/altera/sdram_n5x.c | 16 ++++++++++++++++
>   1 file changed, 16 insertions(+)
>
> diff --git a/drivers/ddr/altera/sdram_n5x.c b/drivers/ddr/altera/sdram_n5x.c
> index 4ac22c536fc..4da0617e37c 100644
> --- a/drivers/ddr/altera/sdram_n5x.c
> +++ b/drivers/ddr/altera/sdram_n5x.c
> @@ -420,6 +420,18 @@ enum data_process {
>   	LOADING
>   };
>   
> +void ddr_init_inprogress(bool start)
> +{
> +	if (start)
> +		setbits_le32(socfpga_get_sysmgr_addr() +
> +			     SYSMGR_SOC64_BOOT_SCRATCH_COLD8,
> +			     ALT_SYSMGR_SCRATCH_REG_8_DDR_PROGRESS_MASK);
> +	else
> +		clrbits_le32(socfpga_get_sysmgr_addr() +
> +			     SYSMGR_SOC64_BOOT_SCRATCH_COLD8,
> +			     ALT_SYSMGR_SCRATCH_REG_8_DDR_PROGRESS_MASK);
> +}
> +
>   bool is_ddr_retention_enabled(u32 reg)
>   {
>   	if (reg & ALT_SYSMGR_SCRATCH_REG_0_DDR_RETENTION_MASK)
> @@ -2820,6 +2832,7 @@ int sdram_mmr_init_full(struct udevice *dev)
>   
>   	if (!is_ddr_init_skipped(reg)) {
>   		printf("SDRAM init in progress ...\n");
> +		ddr_init_inprogress(true);
>   
>   		/*
>   		 * Polling reset complete, must be high to ensure DDR
> @@ -2970,6 +2983,9 @@ int sdram_mmr_init_full(struct udevice *dev)
>   
>   	sdram_size_check(&bd);
>   
> +	/* Marking end of ddr init with passing basic memory test */
> +	ddr_init_inprogress(false);
> +
>   	sdram_set_firewall(&bd);
>   
>   	if (is_ddr_retention_enabled(reg)) {


Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>

Best regards,
Tien Fong


  parent reply	other threads:[~2026-10-21  2:20 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <20261016044047.21496-1-chen.huei.lok@altera.com>
     [not found] ` <20261016044047.21496-2-chen.huei.lok@altera.com>
2026-10-21  1:55   ` [PATCH v4 01/15] misc: fs_loader: Add QSPI RAW offset loading support Chee, Tien Fong
     [not found] ` <20261016044047.21496-3-chen.huei.lok@altera.com>
2026-10-21  2:07   ` [PATCH v4 02/15] arm: dts: socfpga: n5x: add DDR retention calibration backup nodes Chee, Tien Fong
     [not found] ` <20261016044047.21496-4-chen.huei.lok@altera.com>
2026-10-21  2:09   ` [PATCH v4 03/15] arm: socfpga: n5x: enable QSPI mailbox before DDR init Chee, Tien Fong
     [not found] ` <20261016044047.21496-5-chen.huei.lok@altera.com>
2026-10-21  2:14   ` [PATCH v4 04/15] ddr: altera: n5x: Add self-refresh support in DDR4 Chee, Tien Fong
     [not found] ` <20261016044047.21496-6-chen.huei.lok@altera.com>
2026-10-21  2:16   ` [PATCH v4 05/15] configs: socfpga: n5x: enable required configs for DDR retention Chee, Tien Fong
     [not found] ` <20261016044047.21496-7-chen.huei.lok@altera.com>
2026-10-21  2:18   ` Chee, Tien Fong [this message]
     [not found] ` <20261016044047.21496-8-chen.huei.lok@altera.com>
2026-10-21  2:20   ` [PATCH v4 07/15] ddr: altera: n5x: re-init DDR when double-bit ECC error is detected Chee, Tien Fong
     [not found] ` <20261016044047.21496-9-chen.huei.lok@altera.com>
2026-10-21  2:21   ` [PATCH v4 08/15] ddr: altera: n5x: re-init DDR after watchdog reset from init hang Chee, Tien Fong
     [not found] ` <20261016044047.21496-10-chen.huei.lok@altera.com>
2026-10-21  2:22   ` [PATCH v4 09/15] ddr: altera: n5x: return error on invalid DDR controller type Chee, Tien Fong
     [not found] ` <20261016044047.21496-11-chen.huei.lok@altera.com>
2026-10-21  2:24   ` [PATCH v4 10/15] ddr: altera: n5x: use correct cast for reset status register read Chee, Tien Fong
     [not found] ` <20261016044047.21496-12-chen.huei.lok@altera.com>
2026-10-21  2:25   ` [PATCH v4 11/15] ddr: altera: n5x: fix debug log typo Chee, Tien Fong
     [not found] ` <20261016044047.21496-13-chen.huei.lok@altera.com>
2026-10-21  2:27   ` [PATCH v4 12/15] ddr: altera: n5x: rename is_ddr_init_skipped() and quieten reset log Chee, Tien Fong
     [not found] ` <20261016044047.21496-14-chen.huei.lok@altera.com>
2026-10-21  2:29   ` [PATCH v4 13/15] ddr: altera: n5x: drop always-false unsigned less-than-zero checks Chee, Tien Fong
     [not found] ` <20261016044047.21496-15-chen.huei.lok@altera.com>
2026-10-21  2:30   ` [PATCH v4 14/15] ddr: altera: n5x: reconfigure DDR when mem-clk handoff changes Chee, Tien Fong
     [not found] ` <20261016044047.21496-16-chen.huei.lok@altera.com>
2026-10-21  2:31   ` [PATCH v4 15/15] ddr: altera: n5x: Replay PIE handoff on DDR retention restore Chee, Tien Fong

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