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([2a0a:ef40:1d11:ab01:416b:3913:893e:bb4]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38dde7d3f8asm8357394f8f.21.2025.02.12.07.14.09 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 12 Feb 2025 07:14:10 -0800 (PST) Message-ID: Date: Wed, 12 Feb 2025 15:14:09 +0000 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/6] clk/qcom: add initial clock driver for ipq9574 To: Varadarajan Narayanan , trini@konsulko.com, neil.armstrong@linaro.org, sumit.garg@linaro.org, lukma@denx.de, seanga2@gmail.com, peng.fan@nxp.com, jh80.chung@samsung.com, ilias.apalodimas@linaro.org, sjg@chromium.org, Volodymyr_Babchuk@epam.com, lehmanju@devpi.de, pbrobinson@gmail.com, marek.vasut+renesas@mailbox.org, robert.marko@sartura.hr, u-boot@lists.denx.de, u-boot-qcom@groups.io References: <20250130053751.3148614-1-quic_varada@quicinc.com> <20250130053751.3148614-3-quic_varada@quicinc.com> Content-Language: en-US From: Caleb Connolly In-Reply-To: <20250130053751.3148614-3-quic_varada@quicinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean On 1/30/25 05:37, Varadarajan Narayanan wrote: > Add initial set of clocks and resets for enabling U-Boot on ipq9574 > based RDP platforms. What is RDP? > > Signed-off-by: Varadarajan Narayanan > --- > v2: Combined driver file and makefile/kconfig changes into one patch > --- > drivers/clk/qcom/Kconfig | 8 +++ > drivers/clk/qcom/Makefile | 1 + > drivers/clk/qcom/clock-ipq9574.c | 100 +++++++++++++++++++++++++++++++ > drivers/clk/qcom/clock-qcom.h | 1 + > 4 files changed, 110 insertions(+) > create mode 100644 drivers/clk/qcom/clock-ipq9574.c > > diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig > index cb867acc48..3ea01f3c96 100644 > --- a/drivers/clk/qcom/Kconfig > +++ b/drivers/clk/qcom/Kconfig > @@ -31,6 +31,14 @@ config CLK_QCOM_IPQ4019 > on the Snapdragon IPQ4019 SoC. This driver supports the clocks > and resets exposed by the GCC hardware block. > > +config CLK_QCOM_IPQ9574 > + bool "Qualcomm IPQ9574 GCC" > + select CLK_QCOM > + help > + Say Y here to enable support for the Global Clock Controller > + on the Snapdragon IPQ9574 SoC. This driver supports the clocks > + and resets exposed by the GCC hardware block. > + > config CLK_QCOM_QCM2290 > bool "Qualcomm QCM2290 GCC" > select CLK_QCOM > diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile > index 1bc0f15005..e13fc8c107 100644 > --- a/drivers/clk/qcom/Makefile > +++ b/drivers/clk/qcom/Makefile > @@ -7,6 +7,7 @@ obj-$(CONFIG_CLK_QCOM_SDM845) += clock-sdm845.o > obj-$(CONFIG_CLK_QCOM_APQ8016) += clock-apq8016.o > obj-$(CONFIG_CLK_QCOM_APQ8096) += clock-apq8096.o > obj-$(CONFIG_CLK_QCOM_IPQ4019) += clock-ipq4019.o > +obj-$(CONFIG_CLK_QCOM_IPQ9574) += clock-ipq9574.o > obj-$(CONFIG_CLK_QCOM_QCM2290) += clock-qcm2290.o > obj-$(CONFIG_CLK_QCOM_QCS404) += clock-qcs404.o > obj-$(CONFIG_CLK_QCOM_SA8775P) += clock-sa8775p.o > diff --git a/drivers/clk/qcom/clock-ipq9574.c b/drivers/clk/qcom/clock-ipq9574.c > new file mode 100644 > index 0000000000..06f2d2dd45 > --- /dev/null > +++ b/drivers/clk/qcom/clock-ipq9574.c > @@ -0,0 +1,100 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Clock drivers for Qualcomm ipq9574 > + * > + * (C) Copyright 2024 Linaro Ltd. > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include "clock-qcom.h" > + > +#define GCC_BLSP1_AHB_CBCR 0x1004 > +#define GCC_BLSP1_UART3_APPS_CMD_RCGR 0x402C > +#define GCC_BLSP1_UART3_APPS_CBCR 0x4054 > + > +#define GCC_SDCC1_APPS_CBCR 0x3302C > +#define GCC_SDCC1_AHB_CBCR 0x33034 > +#define GCC_SDCC1_APPS_CMD_RCGR 0x33004 > +#define GCC_SDCC1_ICE_CORE_CBCR 0x33030 > + > +static ulong ipq9574_set_rate(struct clk *clk, ulong rate) > +{ > + struct msm_clk_priv *priv = dev_get_priv(clk->dev); > + > + switch (clk->id) { > + case GCC_BLSP1_UART3_APPS_CLK: > + clk_rcg_set_rate_mnd(priv->base, GCC_BLSP1_UART3_APPS_CMD_RCGR, > + 0, 144, 15625, CFG_CLK_SRC_GPLL0, 16); > + return rate; > + case GCC_SDCC1_APPS_CLK: > + clk_rcg_set_rate_mnd(priv->base, GCC_SDCC1_APPS_CMD_RCGR, > + 11, 0, 0, CFG_CLK_SRC_GPLL2, 16); > + return rate; > + default: > + return -EINVAL; > + } > +} > + > +static int ipq9574_enable(struct clk *clk) > +{ > + struct msm_clk_priv *priv = dev_get_priv(clk->dev); > + > + //printk("--> %s: %d\n", __func__, clk->id); Remove or demote to debug, with gate_clk you can include the clock name as well. > + switch (clk->id) { > + case GCC_BLSP1_UART3_APPS_CLK: > + clk_enable_cbc(priv->base + GCC_BLSP1_UART3_APPS_CBCR); > + break; > + case GCC_BLSP1_AHB_CLK: > + clk_enable_cbc(priv->base + GCC_BLSP1_AHB_CBCR); > + break; > + case GCC_SDCC1_AHB_CLK: > + clk_enable_cbc(priv->base + GCC_SDCC1_AHB_CBCR); > + break; > + case GCC_SDCC1_APPS_CLK: > + clk_enable_cbc(priv->base + GCC_SDCC1_APPS_CBCR); > + break; > + case GCC_SDCC1_ICE_CORE_CLK: > + clk_enable_cbc(priv->base + GCC_SDCC1_ICE_CORE_CBCR); > + break; > + default: > + return -EINVAL; > + } Please use the gate_clk API for these, refer to clock-sdm845.c for reference. With that: Reviewed-by: Caleb Connolly Kind regards, > + > + return 0; > +} > + > +static const struct qcom_reset_map ipq9574_gcc_resets[] = { > + [GCC_SDCC_BCR] = { 0x33000 }, > +}; > + > +static struct msm_clk_data ipq9574_gcc_data = { > + .resets = ipq9574_gcc_resets, > + .num_resets = ARRAY_SIZE(ipq9574_gcc_resets), > + .enable = ipq9574_enable, > + .set_rate = ipq9574_set_rate, > +}; > + > +static const struct udevice_id gcc_ipq9574_of_match[] = { > + { > + .compatible = "qcom,ipq9574-gcc", > + .data = (ulong)&ipq9574_gcc_data, > + }, > + { } > +}; > + > +U_BOOT_DRIVER(gcc_ipq9574) = { > + .name = "gcc_ipq9574", > + .id = UCLASS_NOP, > + .of_match = gcc_ipq9574_of_match, > + .bind = qcom_cc_bind, > + .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF, > +}; > diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h > index ff336dea39..e038dc421e 100644 > --- a/drivers/clk/qcom/clock-qcom.h > +++ b/drivers/clk/qcom/clock-qcom.h > @@ -11,6 +11,7 @@ > #define CFG_CLK_SRC_CXO (0 << 8) > #define CFG_CLK_SRC_GPLL0 (1 << 8) > #define CFG_CLK_SRC_GPLL0_AUX2 (2 << 8) > +#define CFG_CLK_SRC_GPLL2 (2 << 8) > #define CFG_CLK_SRC_GPLL9 (2 << 8) > #define CFG_CLK_SRC_GPLL0_ODD (3 << 8) > #define CFG_CLK_SRC_GPLL6 (4 << 8) -- Caleb (they/them)