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Fri, 28 Mar 2025 14:55:16 +0000 Message-ID: Date: Fri, 28 Mar 2025 15:55:05 +0100 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] ufs: amd-versal2: Use raw read/write for SLCR/CACHE registers From: Michal Simek To: u-boot@lists.denx.de, git@xilinx.com Cc: Venkatesh Yadav Abbarapu , Bhupesh Sharma , Ilias Apalodimas , Neha Malcom Francis , Neil Armstrong , Prasad Kummari , Simon Glass , Tom Rini References: Content-Language: en-US Autocrypt: addr=michal.simek@amd.com; keydata= xsFNBFFuvDEBEAC9Amu3nk79+J+4xBOuM5XmDmljuukOc6mKB5bBYOa4SrWJZTjeGRf52VMc howHe8Y9nSbG92obZMqsdt+d/hmRu3fgwRYiiU97YJjUkCN5paHXyBb+3IdrLNGt8I7C9RMy svSoH4WcApYNqvB3rcMtJIna+HUhx8xOk+XCfyKJDnrSuKgx0Svj446qgM5fe7RyFOlGX/wF Ae63Hs0RkFo3I/+hLLJP6kwPnOEo3lkvzm3FMMy0D9VxT9e6Y3afe1UTQuhkg8PbABxhowzj SEnl0ICoqpBqqROV/w1fOlPrm4WSNlZJunYV4gTEustZf8j9FWncn3QzRhnQOSuzTPFbsbH5 WVxwDvgHLRTmBuMw1sqvCc7CofjsD1XM9bP3HOBwCxKaTyOxbPJh3D4AdD1u+cF/lj9Fj255 Es9aATHPvoDQmOzyyRNTQzupN8UtZ+/tB4mhgxWzorpbdItaSXWgdDPDtssJIC+d5+hskys8 B3jbv86lyM+4jh2URpnL1gqOPwnaf1zm/7sqoN3r64cml94q68jfY4lNTwjA/SnaS1DE9XXa XQlkhHgjSLyRjjsMsz+2A4otRLrBbumEUtSMlPfhTi8xUsj9ZfPIUz3fji8vmxZG/Da6jx/c a0UQdFFCL4Ay/EMSoGbQouzhC69OQLWNH3rMQbBvrRbiMJbEZwARAQABzSlNaWNoYWwgU2lt ZWsgKEFNRCkgPG1pY2hhbC5zaW1la0BhbWQuY29tPsLBlAQTAQgAPgIbAwULCQgHAgYVCgkI CwIEFgIDAQIeAQIXgBYhBGc1DJv1zO6bU2Q1ajd8fyH+PR+RBQJkK9VOBQkWf4AXAAoJEDd8 fyH+PR+ROzEP/1IFM7J4Y58SKuvdWDddIvc7JXcal5DpUtMdpuV+ZiHSOgBQRqvwH4CVBK7p ktDCWQAoWCg0KhdGyBjfyVVpm+Gw4DkZovcvMGUlvY5p5w8XxTE5Xx+cj/iDnj83+gy+0Oyz VFU9pew9rnT5YjSRFNOmL2dsorxoT1DWuasDUyitGy9iBegj7vtyAsvEObbGiFcKYSjvurkm MaJ/AwuJehZouKVfWPY/i4UNsDVbQP6iwO8jgPy3pwjt4ztZrl3qs1gV1F4Zrak1k6qoDP5h 19Q5XBVtq4VSS4uLKjofVxrw0J+sHHeTNa3Qgk9nXJEvH2s2JpX82an7U6ccJSdNLYbogQAS BW60bxq6hWEY/afbT+tepEsXepa0y04NjFccFsbECQ4DA3cdA34sFGupUy5h5la/eEf3/8Kd BYcDd+aoxWliMVmL3DudM0Fuj9Hqt7JJAaA0Kt3pwJYwzecl/noK7kFhWiKcJULXEbi3Yf/Y pwCf691kBfrbbP9uDmgm4ZbWIT5WUptt3ziYOWx9SSvaZP5MExlXF4z+/KfZAeJBpZ95Gwm+ FD8WKYjJChMtTfd1VjC4oyFLDUMTvYq77ABkPeKB/WmiAoqMbGx+xQWxW113wZikDy+6WoCS MPXfgMPWpkIUnvTIpF+m1Nyerqf71fiA1W8l0oFmtCF5oTMkzsFNBFFuvDEBEACXqiX5h4IA 03fJOwh+82aQWeHVAEDpjDzK5hSSJZDE55KP8br1FZrgrjvQ9Ma7thSu1mbr+ydeIqoO1/iM fZA+DDPpvo6kscjep11bNhVa0JpHhwnMfHNTSHDMq9OXL9ZZpku/+OXtapISzIH336p4ZUUB 5asad8Ux70g4gmI92eLWBzFFdlyR4g1Vis511Nn481lsDO9LZhKyWelbif7FKKv4p3FRPSbB vEgh71V3NDCPlJJoiHiYaS8IN3uasV/S1+cxVbwz2WcUEZCpeHcY2qsQAEqp4GM7PF2G6gtz IOBUMk7fjku1mzlx4zP7uj87LGJTOAxQUJ1HHlx3Li+xu2oF9Vv101/fsCmptAAUMo7KiJgP Lu8TsP1migoOoSbGUMR0jQpUcKF2L2jaNVS6updvNjbRmFojK2y6A/Bc6WAKhtdv8/e0/Zby iVA7/EN5phZ1GugMJxOLHJ1eqw7DQ5CHcSQ5bOx0Yjmhg4PT6pbW3mB1w+ClAnxhAbyMsfBn XxvvcjWIPnBVlB2Z0YH/gizMDdM0Sa/HIz+q7JR7XkGL4MYeAM15m6O7hkCJcoFV7LMzkNKk OiCZ3E0JYDsMXvmh3S4EVWAG+buA+9beElCmXDcXPI4PinMPqpwmLNcEhPVMQfvAYRqQp2fg 1vTEyK58Ms+0a9L1k5MvvbFg9QARAQABwsF8BBgBCAAmAhsMFiEEZzUMm/XM7ptTZDVqN3x/ If49H5EFAmQr1YsFCRZ/gFoACgkQN3x/If49H5H6BQ//TqDpfCh7Fa5v227mDISwU1VgOPFK eo/+4fF/KNtAtU/VYmBrwT/N6clBxjJYY1i60ekFfAEsCb+vAr1W9geYYpuA+lgR3/BOkHlJ eHf4Ez3D71GnqROIXsObFSFfZWGEgBtHBZ694hKwFmIVCg+lqeMV9nPQKlvfx2n+/lDkspGi epDwFUdfJLHOYxFZMQsFtKJX4fBiY85/U4X2xSp02DxQZj/N2lc9OFrKmFJHXJi9vQCkJdIj S6nuJlvWj/MZKud5QhlfZQsixT9wCeOa6Vgcd4vCzZuptx8gY9FDgb27RQxh/b1ZHalO1h3z kXyouA6Kf54Tv6ab7M/fhNqznnmSvWvQ4EWeh8gddpzHKk8ixw9INBWkGXzqSPOztlJbFiQ3 YPi6o9Pw/IxdQJ9UZ8eCjvIMpXb4q9cZpRLT/BkD4ttpNxma1CUVljkF4DuGydxbQNvJFBK8 ywyA0qgv+Mu+4r/Z2iQzoOgE1SymrNSDyC7u0RzmSnyqaQnZ3uj7OzRkq0fMmMbbrIvQYDS/ y7RkYPOpmElF2pwWI/SXKOgMUgigedGCl1QRUio7iifBmXHkRrTgNT0PWQmeGsWTmfRit2+i l2dpB2lxha72cQ6MTEmL65HaoeANhtfO1se2R9dej57g+urO9V2v/UglZG1wsyaP/vOrgs+3 3i3l5DA= In-Reply-To: Content-Type: text/plain; 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Replace > these raw reads/writes with the xilinx_pm_request() API with the > correct arguments once the PM related changes are done. > > Signed-off-by: Venkatesh Yadav Abbarapu > Signed-off-by: Michal Simek > --- > > arch/arm/mach-versal2/include/mach/hardware.h | 6 ++ > drivers/firmware/firmware-zynqmp.c | 28 ++++++++ > drivers/ufs/ufs-amd-versal2.c | 66 ++++--------------- > include/zynqmp_firmware.h | 4 ++ > 4 files changed, 52 insertions(+), 52 deletions(-) > > diff --git a/arch/arm/mach-versal2/include/mach/hardware.h b/arch/arm/mach-versal2/include/mach/hardware.h > index a961032b4d5b..7ca2bbb7550f 100644 > --- a/arch/arm/mach-versal2/include/mach/hardware.h > +++ b/arch/arm/mach-versal2/include/mach/hardware.h > @@ -97,3 +97,9 @@ enum versal2_platform { > #define MIO_PIN_12 0xF1060030 > #define BANK0_OUTPUT 0xF1020040 > #define BANK0_TRI 0xF1060200 > + > +#define PMXC_EFUSE_CACHE_BASE_ADDRESS 0xF1250000 > +#define PMXC_SLCR_BASE_ADDRESS 0xF1061000 > +#define PMXC_UFS_CAL_1_OFFSET 0xBE8 > +#define PMXC_SRAM_CSR 0x4C > +#define PMXC_TX_RX_CFG_RDY 0x54 > diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c > index 584397ba29a3..2940181e83e9 100644 > --- a/drivers/firmware/firmware-zynqmp.c > +++ b/drivers/firmware/firmware-zynqmp.c > @@ -5,6 +5,8 @@ > * Copyright (C) 2018-2019 Xilinx, Inc. > */ > > +#include > +#include > #include > #include > #include > @@ -169,6 +171,32 @@ unsigned int zynqmp_firmware_version(void) > return pm_api_version; > }; > > +#if defined(CONFIG_ARCH_VERSAL2) > +int zynqmp_pm_ufs_get_txrx_cfgrdy(u32 *value) > +{ > + *value = readl(PMXC_SLCR_BASE_ADDRESS + PMXC_TX_RX_CFG_RDY); > + return 0; > +} > + > +int zynqmp_pm_ufs_sram_csr_read(u32 *value) > +{ > + *value = readl(PMXC_SLCR_BASE_ADDRESS + PMXC_SRAM_CSR); > + return 0; > +} > + > +int zynqmp_pm_ufs_sram_csr_write(u32 *value) > +{ > + writel(*value, PMXC_SLCR_BASE_ADDRESS + PMXC_SRAM_CSR); > + return 0; > +} > + > +int zynqmp_pm_ufs_cal_reg(u32 *value) > +{ > + *value = readl(PMXC_EFUSE_CACHE_BASE_ADDRESS + PMXC_UFS_CAL_1_OFFSET); > + return 0; > +} > +#endif > + > int zynqmp_pm_set_gem_config(u32 node, enum pm_gem_config_type config, u32 value) > { > int ret; > diff --git a/drivers/ufs/ufs-amd-versal2.c b/drivers/ufs/ufs-amd-versal2.c > index bfd844e41938..1c5ed538370e 100644 > --- a/drivers/ufs/ufs-amd-versal2.c > +++ b/drivers/ufs/ufs-amd-versal2.c > @@ -19,8 +19,6 @@ > #include "ufshcd-dwc.h" > #include "ufshci-dwc.h" > > -#define VERSAL2_UFS_DEVICE_ID 4 > - > #define SRAM_CSR_INIT_DONE_MASK BIT(0) > #define SRAM_CSR_EXT_LD_DONE_MASK BIT(1) > #define SRAM_CSR_BYPASS_MASK BIT(2) > @@ -32,19 +30,12 @@ > > #define TIMEOUT_MICROSEC 1000000L > > -#define IOCTL_UFS_TXRX_CFGRDY_GET 40 > -#define IOCTL_UFS_SRAM_CSR_SEL 41 > - > -#define PM_UFS_SRAM_CSR_WRITE 0 > -#define PM_UFS_SRAM_CSR_READ 1 > - > struct ufs_versal2_priv { > struct ufs_hba *hba; > struct reset_ctl *rstc; > struct reset_ctl *rstphy; > u32 phy_mode; > u32 host_clk; > - u32 pd_dev_id; > u8 attcompval0; > u8 attcompval1; > u8 ctlecompval0; > @@ -102,41 +93,6 @@ static int ufs_versal2_phy_reg_read(struct ufs_hba *hba, u32 addr, u32 *val) > return 0; > } > > -int versal2_pm_ufs_get_txrx_cfgrdy(u32 node_id, u32 *value) > -{ > - u32 ret_payload[PAYLOAD_ARG_CNT]; > - int ret; > - > - if (!value) > - return -EINVAL; > - > - ret = xilinx_pm_request(PM_IOCTL, node_id, IOCTL_UFS_TXRX_CFGRDY_GET, > - 0, 0, ret_payload); > - *value = ret_payload[1]; > - > - return ret; > -} > - > -int versal2_pm_ufs_sram_csr_sel(u32 node_id, u32 type, u32 *value) > -{ > - u32 ret_payload[PAYLOAD_ARG_CNT]; > - int ret; > - > - if (!value) > - return -EINVAL; > - > - if (type == PM_UFS_SRAM_CSR_READ) { > - ret = xilinx_pm_request(PM_IOCTL, node_id, IOCTL_UFS_SRAM_CSR_SEL, > - type, 0, ret_payload); > - *value = ret_payload[1]; > - } else { > - ret = xilinx_pm_request(PM_IOCTL, node_id, IOCTL_UFS_SRAM_CSR_SEL, > - type, *value, 0); > - } > - > - return ret; > -} > - > static int ufs_versal2_enable_phy(struct ufs_hba *hba) > { > u32 offset, reg; > @@ -281,7 +237,7 @@ static int ufs_versal2_phy_init(struct ufs_hba *hba) > time_left = TIMEOUT_MICROSEC; > do { > time_left--; > - ret = versal2_pm_ufs_get_txrx_cfgrdy(priv->pd_dev_id, ®); > + ret = zynqmp_pm_ufs_get_txrx_cfgrdy(®); > if (ret) > return ret; > > @@ -312,8 +268,7 @@ static int ufs_versal2_phy_init(struct ufs_hba *hba) > time_left = TIMEOUT_MICROSEC; > do { > time_left--; > - ret = versal2_pm_ufs_sram_csr_sel(priv->pd_dev_id, > - PM_UFS_SRAM_CSR_READ, ®); > + ret = zynqmp_pm_ufs_sram_csr_read(®); > if (ret) > return ret; > > @@ -341,10 +296,10 @@ static int ufs_versal2_init(struct ufs_hba *hba) > struct ufs_versal2_priv *priv = dev_get_priv(hba->dev); > struct clk clk; > unsigned long core_clk_rate = 0; > + u32 cal; > int ret = 0; > > priv->phy_mode = UFSHCD_DWC_PHY_MODE_ROM; > - priv->pd_dev_id = VERSAL2_UFS_DEVICE_ID; > > ret = clk_get_by_name(hba->dev, "core_clk", &clk); > if (ret) { > @@ -371,6 +326,15 @@ static int ufs_versal2_init(struct ufs_hba *hba) > return PTR_ERR(priv->rstphy); > } > > + ret = zynqmp_pm_ufs_cal_reg(&cal); > + if (ret) > + return ret; > + > + priv->attcompval0 = (u8)cal; > + priv->attcompval1 = (u8)(cal >> 8); > + priv->ctlecompval0 = (u8)(cal >> 16); > + priv->ctlecompval1 = (u8)(cal >> 24); > + > return ret; > } > > @@ -397,8 +361,7 @@ static int ufs_versal2_hce_enable_notify(struct ufs_hba *hba, > return ret; > } > > - ret = versal2_pm_ufs_sram_csr_sel(priv->pd_dev_id, > - PM_UFS_SRAM_CSR_READ, &sram_csr); > + ret = zynqmp_pm_ufs_sram_csr_read(&sram_csr); > if (ret) > return ret; > > @@ -410,8 +373,7 @@ static int ufs_versal2_hce_enable_notify(struct ufs_hba *hba, > return -EINVAL; > } > > - ret = versal2_pm_ufs_sram_csr_sel(priv->pd_dev_id, > - PM_UFS_SRAM_CSR_WRITE, &sram_csr); > + ret = zynqmp_pm_ufs_sram_csr_write(&sram_csr); > if (ret) > return ret; > > diff --git a/include/zynqmp_firmware.h b/include/zynqmp_firmware.h > index 82781dfd16bc..dc06abc52fce 100644 > --- a/include/zynqmp_firmware.h > +++ b/include/zynqmp_firmware.h > @@ -458,6 +458,10 @@ int zynqmp_mmio_read(const u32 address, u32 *value); > int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value); > int zynqmp_pm_feature(const u32 api_id); > u32 zynqmp_pm_get_bootmode_reg(void); > +int zynqmp_pm_ufs_get_txrx_cfgrdy(u32 *value); > +int zynqmp_pm_ufs_sram_csr_read(u32 *value); > +int zynqmp_pm_ufs_sram_csr_write(u32 *value); > +int zynqmp_pm_ufs_cal_reg(u32 *value); > u32 zynqmp_pm_get_pmc_multi_boot_reg(void); > > /* Type of Config Object */ Applied. M