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a="146996921" X-IronPort-AV: E=Sophos;i="6.24,200,1774306800"; d="scan'208";a="146996921" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO MUCSE819.infineon.com) ([172.23.29.45]) by smtp11.infineon.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jun 2026 09:57:08 +0200 Received: from MUCSE815.infineon.com (172.23.29.41) by MUCSE819.infineon.com (172.23.29.45) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.37; Fri, 12 Jun 2026 09:57:08 +0200 Received: from MUCSE815.infineon.com ([fe80::ed10:a720:3031:ca14]) by MUCSE815.infineon.com ([fe80::ed10:a720:3031:ca14%12]) with mapi id 15.02.2562.037; Fri, 12 Jun 2026 09:57:08 +0200 From: To: , CC: , , , , , , , , , , , Subject: RE: [PATCH v5 1/7] mtd: spi-nor-ids: Correct flash flags for ESMT/EON flashes Thread-Topic: [PATCH v5 1/7] mtd: spi-nor-ids: Correct flash flags for ESMT/EON flashes Thread-Index: AQHc+XpCcpgAaEuKrESE2niT6yo2XbY6gmIw Date: Fri, 12 Jun 2026 07:57:08 +0000 Message-ID: References: <64ce1a920dc067717de2b39d2e7a5098e6853aab.1781164951.git.weijie.gao@mediatek.com> In-Reply-To: <64ce1a920dc067717de2b39d2e7a5098e6853aab.1781164951.git.weijie.gao@mediatek.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.161.6.196] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-Mailman-Approved-At: Fri, 12 Jun 2026 14:36:02 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Hi, >=20 > All currently supported ESMT/EON flashes supports 4KB sector and dual/qua= d > read. >=20 > Link: https://www.esmt.com.tw/upload/pdf/ESMT/datasheets/EN25Q80B.pdf > Link: https://www.esmt.com.tw/upload/pdf/ESMT/datasheets/EN25QH128A%20(2T= C).pdf > Link: https://www.esmt.com.tw/upload/pdf/ESMT/datasheets/EN25S64A(2SC).pd= f > Signed-off-by: Weijie Gao > --- > v5: not changed > v3-v4: updated commit message > v2: not changed > --- > drivers/mtd/spi/spi-nor-ids.c | 12 ++++++------ > 1 file changed, 6 insertions(+), 6 deletions(-) >=20 > diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.= c > index c0fa98424aa..7d96adab4fd 100644 > --- a/drivers/mtd/spi/spi-nor-ids.c > +++ b/drivers/mtd/spi/spi-nor-ids.c > @@ -90,12 +90,12 @@ const struct flash_info spi_nor_ids[] =3D { > #endif > #ifdef CONFIG_SPI_FLASH_EON /* EON */ > /* EON -- en25xxx */ > - { INFO("en25q80b", 0x1c3014, 0, 64 * 1024, 16, SECT_4K) }, > - { INFO("en25q32b", 0x1c3016, 0, 64 * 1024, 64, 0) }, > - { INFO("en25q64", 0x1c3017, 0, 64 * 1024, 128, SECT_4K) }, > - { INFO("en25q128b", 0x1c3018, 0, 64 * 1024, 256, 0) }, > - { INFO("en25qh128", 0x1c7018, 0, 64 * 1024, 256, 0) }, > - { INFO("en25s64", 0x1c3817, 0, 64 * 1024, 128, SECT_4K) }, > + { INFO("en25q80b", 0x1c3014, 0, 64 * 1024, 16, SECT_4K | SPI_= NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, > + { INFO("en25q32b", 0x1c3016, 0, 64 * 1024, 64, SECT_4K | SPI_= NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, > + { INFO("en25q64", 0x1c3017, 0, 64 * 1024, 128, SECT_4K | SPI_= NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, > + { INFO("en25q128b", 0x1c3018, 0, 64 * 1024, 256, SECT_4K | SPI_= NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, > + { INFO("en25qh128", 0x1c7018, 0, 64 * 1024, 256, SECT_4K | SPI_= NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, > + { INFO("en25s64", 0x1c3817, 0, 64 * 1024, 128, SECT_4K | SPI_= NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, If SPI_NOR_QUAD_READ is given, the driver assumes the chip supports Quad Output Read (1-1-4, 6Bh) and Quad Page Program (1-1-4, 32h). Except en25qh128, those chips don't support 1-1-4 read/program per datashee= ts. They do support Quad I/O Read (1-4-4, EBh). If you want to enable it, write fixup otherwise just drop the SPI_NOR_QUAD_READ flag, please. Thanks, Takahiro