[RFC PATCH v4 1/2] arch: riscv: cpu: Add callback to init each core

[Sean Anderson <seanga2@gmail.com>]

On 4/13/21 9:05 PM, Rick Chen wrote:
> Hi Sean,
> 
>> On 4/13/21 12:12 AM, Rick Chen wrote:
>>> Hi Sean
>>>
>>>> On 4/12/21 10:39 PM, Rick Chen wrote:
>>>>> Hi Green,
>>>>>
>>>>>> From: Green Wan [mailto:green.wan at sifive.com]
>>>>>> Sent: Monday, April 12, 2021 10:33 AM
>>>>>> To: Sean Anderson
>>>>>> Cc: Rick Chen; Rick Jian-Zhi Chen(???); Bin Meng; U-Boot Mailing List; Paul Walmsley; Pragnesh Patel; Simon Glass; Atish Patra; Leo Yu-Chi Liang(???); Brad Kim
>>>>>> Subject: Re: [RFC PATCH v4 1/2] arch: riscv: cpu: Add callback to init each core
>>>>>>
>>>>>> Hi Bin and Sean,
>>>>>>
>>>>>> While we keep the consistency of cache control discussion going, later
>>>>>> today I'd like to send the v5 patch which is not directly relevant to
>>>>>> cache control.
>>>>>
>>>>> I will prefer not to mix cache control issue into this patch.
>>>>> Like I said, this callback is a init for all harts before lottery.
>>>>
>>>> Yes, but enabling caches is a very similar thing (this proposal even
>>>> uses it to turn on caches, among other things). At the moment we have
>>>> two calls to enable caches at almost the same time as what Green
>>>> proposes. These calls only translate into work done on one platform. I
>>>> think having one call (or perhaps two) for this purpose would help
>>>> reduce codepaths across different platforms going forward.
>>>>
>>>
>>> Maybe we can add two callbacks (early_lottery_init and
>>> late_lottery_init) before and after lottery individually for all
>>> scenarios.
>>
>> Yes, that is a possibility. But do we actually need that flexibility?
>> This comes back around to my original question: why does ax25 disable
>> cache on all harts before jumping to Linux?
> 
> clarify your above expressions:
> only disable main hart (not all harts) before jumping to Linux.
> 
> Why you think it is a question to disable cache before jumping to Linux.
> You can find many same cache flow in cleanup_before_linux of /arch/arm
> Are they all the questions ?

Well, for example K210 cannot disable cache (or rather, cache is a
property of memory address), so cache is always enabled. And this series
from Green suggests that the FU740 also cannot disable cache once
enabled, and he would like to enable it on all harts very early in boot.
So does it matter whether cache is enabled or disabled?

Alternatively, why is cache only enabled on the main hart on ax25? Would
it be OK to enable it on all harts (and then later disable it on all
harts)?

--Sean

> 
> Thanks,
> Rick
> 
>>
>> And of course, does this actually need to be done before the lottery?
>>
>> --Sean
>>