Re: [PATCH] riscv: Exclude ACLINT for TARGET_XILINX_MBV

[Michal Simek <michal.simek@amd.com>]

On 5/1/26 12:33, Yao Zi wrote:
> On Thu, Apr 30, 2026 at 01:58:28PM +0200, Michal Simek wrote:
>> The Xilinx MicroBlaze V platform does not have an ACLINT (Advanced
>> Core Local Interruptor) hardware block. The timer functionality is
>> provided through a different mechanism.
>>
>> Exclude both RISCV_ACLINT and SPL_RISCV_ACLINT from being implied
>> for TARGET_XILINX_MBV while keeping the default behavior for other
>> generic RISC-V targets that do have ACLINT hardware.
>>
>>     spl/u-boot-spl: all -1382 data -360 rodata -200 text -822
>>
>> Signed-off-by: Michal Simek <michal.simek@amd.com>
>> ---
>>
>>   arch/riscv/cpu/generic/Kconfig | 4 ++--
>>   1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/riscv/cpu/generic/Kconfig b/arch/riscv/cpu/generic/Kconfig
>> index 2baba2299238..8d53c69ba38c 100644
>> --- a/arch/riscv/cpu/generic/Kconfig
>> +++ b/arch/riscv/cpu/generic/Kconfig
>> @@ -10,8 +10,8 @@ config GENERIC_RISCV
>>   	imply CPU
>>   	imply CPU_RISCV
>>   	imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
>> -	imply RISCV_ACLINT if RISCV_MMODE
>> -	imply SPL_RISCV_ACLINT if SPL_RISCV_MMODE
>> +	imply RISCV_ACLINT if RISCV_MMODE && !TARGET_XILINX_MBV
>> +	imply SPL_RISCV_ACLINT if SPL_RISCV_MMODE && !TARGET_XILINX_MBV
> 
> Would it be a better idea to make (SPL_)RISCV_ACLINT visible and
> override them in your platform defconfigs? This avoids introducing
> platform-specific conditions in a "generic" CPU Kconfig.

No issue with it. I sent v2 with this.

Thanks,
Michal