From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3E3E7C77B78 for ; Wed, 3 May 2023 09:30:37 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 307B9846EA; Wed, 3 May 2023 11:30:35 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="Gp/sklGd"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 144ED84729; Wed, 3 May 2023 11:30:34 +0200 (CEST) Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id ABA15846DC for ; Wed, 3 May 2023 11:30:31 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-kumar1@ti.com Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 3439USw2089319; Wed, 3 May 2023 04:30:28 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1683106228; bh=kdUuBHzKGmUWkNXIUPp3Ip2JodicZCNoT2oPtGVZQsU=; h=Date:Subject:To:CC:References:From:In-Reply-To; b=Gp/sklGdhN9Dk+RMdfXTF26A5lLJqAMYhbYVwbgEK4qLqEmqlQhXkqYFzg2rng35Y JHU4wBE7kfXGLRCWkSR7/HJ1J2d2AviZjGz/z6HaKZ5fWawJUEuXGCFkuoe330VALf gRYb6r62cRi9liORfABj6JKjjeUqGk5oZOMXdUa4= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 3439USvX005215 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 3 May 2023 04:30:28 -0500 Received: from DFLE115.ent.ti.com (10.64.6.36) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 3 May 2023 04:30:28 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 3 May 2023 04:30:27 -0500 Received: from [172.24.216.133] (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 3439UNgu025304; Wed, 3 May 2023 04:30:24 -0500 Message-ID: Date: Wed, 3 May 2023 15:00:22 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.10.1 Subject: Re: [PATCH v2] arch: arm: mach-k3: Delete tifs node in DT fixup To: Nishanth Menon CC: Andrew Davis , Neha Malcom Francis , "Dasan, Nikhil" , "trini@konsulko.com" , "u-boot@lists.denx.de" , "Raghavendra, Vignesh" , References: <20230419061352.3156023-1-u-kumar1@ti.com> <20230420081128.3617214-1-u-kumar1@ti.com> <217dded4-57ba-515f-dec9-77a63aebc303@ti.com> <77206a56-a0e9-ad4f-2c73-1f3b1109c649@ti.com> <92bbfb51-a605-27c9-9fd1-65a921532fdb@ti.com> <89918e21335c4fa18ae0d2447bea192b@ti.com> <4b016f2b-678a-43ff-bca0-9c2aee50eb02@ti.com> <1e92f584-6c59-6db4-ac59-4f6fe76c441e@ti.com> <29a1e2f6-36c5-42f6-5213-46a237ebf241@ti.com> <6198aa4e-126e-7b58-792f-36cb799a52af@ti.com> <20230502230022.5pjywy6h7oqrkmwh@elusive> Content-Language: en-US From: "Kumar, Udit" In-Reply-To: <20230502230022.5pjywy6h7oqrkmwh@elusive> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Hi Nishanth, On 5/3/2023 4:30 AM, Nishanth Menon wrote: > On 12:57-20230502, Kumar, Udit wrote: >> On 5/1/2023 8:16 PM, Andrew Davis wrote: >>> On 4/26/23 9:13 AM, Kumar, Udit wrote: >>>> Hi Neha, >>>> >>>> On 4/26/2023 5:31 PM, Neha Malcom Francis wrote: >>>>> Hi Udit >>>>> >>>>> On 26/04/23 16:09, Kumar, Udit wrote: >>>>>> Hi Neha, >>>>>> >>>>>>> Hi Udit, >>>>>> [..] >>>>>> [..] >>>>>> >>>>> What I mean to ask is, why aren't there tifs or l3cache subnodes >>>>> in j721e, j7200 and am65? >>>>> >>>> I think,  above platform is doing in right way, >>>> >>>> AFAIK,  if we have to provide then we can provide size of this. >>>> >>>> l3-cache can not be addressable. >>>> >>> >>> So the history here is we used to have the SRAM node in DT sized >>> to the actual size in hardware. L3 cache size can be set at boot >>> time (in SYSFW board-config file), and that uses up some of the >>> SRAM, so the end address moves in. We could represent this as >>> a reserved node inside the full SRAM node, or by shrinking the >>> SRAM node and hiding this. Same story for TIFS and ATF, they >>> use some variable amount of the end of SRAM. >>> >> Ah, I have other view. >> >> We shrunk SRAM size already, having reserved node on top of SRAM >> >> is good as removing this. > How about we do this: > a) Start by discussing in k.org with a patch as to how we think it > should be and what the rationale is. ok > b) SRAM size fixup is a consequence of firmware being flexible.. Since, > the tifs reserved sram etc, base description exists even after > "hardware reconfiguration", u-boot may adjust, but not delete such nodes. > "reserved" is part of complete description and indication that this > specific OS is not supposed to use this region. That region is protected by > firewall and mechanisms to make such access fail, but that is the > point of "reserved" nodes. you mean , keep full view of SRAM and update size of reserved node. BTW, L3-cache and tifs will be reserved by default. > c) Standardize this across the SoCs that use MSMC (WITHOUT BREAKING > FORWARD AND BACKWARD COMPATIBILITY of u-boot vs dtb). >