[U-Boot] [PATCH v4 1/4] arm: socfpga: rst: add register definition for cold reset

[U-Boot] [PATCH v4 1/4] arm: socfpga: rst: add register definition for cold reset

[Simon Goldschmidt]

This adds a define for the bit in rstmgr's ctrl regiser that issues
a cold reset (we had a define for the warm reset bit only) in preparation
for a proper sysrese driver.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Series changes: 2
- separate this patch to the register descriptions from the actual
  sysreset driver patch
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/mach-socfpga/include/mach/reset_manager.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index 42beaecdd6..6ad037e325 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -11,6 +11,7 @@ void reset_cpu(ulong addr);
 void socfpga_per_reset(u32 reset, int set);
 void socfpga_per_reset_all(void);
 
+#define RSTMGR_CTRL_SWCOLDRSTREQ_LSB 0
 #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1
 
 /*
-- 
2.20.1

[U-Boot] [PATCH v4 2/4] sysreset: socfpga: gen5: add sysreset driver

[Simon Goldschmidt]

This adds a UCLASS_SYSRESET sysreset driver for socfgpa gen5.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
---

Changes in v4:
- change BIT() instead of open coded shift
- add drivers/sysreset/sysreset_socfpga.c to MAINTAINERS

Changes in v3:
- moved socfpga gen5 sysreset driver to extra patch

Changes in v2: None

 MAINTAINERS                         |  1 +
 drivers/sysreset/Kconfig            |  7 ++++
 drivers/sysreset/Makefile           |  1 +
 drivers/sysreset/sysreset_socfpga.c | 56 +++++++++++++++++++++++++++++
 4 files changed, 65 insertions(+)
 create mode 100644 drivers/sysreset/sysreset_socfpga.c

diff --git a/MAINTAINERS b/MAINTAINERS
index bc67c49965..8031cc92f5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -94,6 +94,7 @@ M:	Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
 S:	Maintainted
 T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-socfpga.git
 F:	arch/arm/mach-socfpga/
+F:	drivers/sysreset/sysreset_socfpga.c
 
 ARM AMLOGIC SOC SUPPORT
 M:	Neil Armstrong <narmstrong@baylibre.com>
diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig
index a69b74cee2..4ca635742f 100644
--- a/drivers/sysreset/Kconfig
+++ b/drivers/sysreset/Kconfig
@@ -55,6 +55,13 @@ config SYSRESET_PSCI
 	  Enable PSCI SYSTEM_RESET function call.  To use this, PSCI firmware
 	  must be running on your system.
 
+config SYSRESET_SOCFPGA
+	bool "Enable support for Intel SOCFPGA family"
+	depends on ARCH_SOCFPGA && (TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10)
+	help
+	  This enables the system reset driver support for Intel SOCFPGA SoCs
+	  (Cyclone 5, Arria 5 and Arria 10).
+
 config SYSRESET_TI_SCI
 	bool "TI System Control Interface (TI SCI) system reset driver"
 	depends on TI_SCI_PROTOCOL
diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
index 8e1c845dfe..180e46301d 100644
--- a/drivers/sysreset/Makefile
+++ b/drivers/sysreset/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_SYSRESET_GPIO) += sysreset_gpio.o
 obj-$(CONFIG_SYSRESET_MCP83XX) += sysreset_mpc83xx.o
 obj-$(CONFIG_SYSRESET_MICROBLAZE) += sysreset_microblaze.o
 obj-$(CONFIG_SYSRESET_PSCI) += sysreset_psci.o
+obj-$(CONFIG_SYSRESET_SOCFPGA) += sysreset_socfpga.o
 obj-$(CONFIG_SYSRESET_TI_SCI) += sysreset-ti-sci.o
 obj-$(CONFIG_SYSRESET_SYSCON) += sysreset_syscon.o
 obj-$(CONFIG_SYSRESET_WATCHDOG) += sysreset_watchdog.o
diff --git a/drivers/sysreset/sysreset_socfpga.c b/drivers/sysreset/sysreset_socfpga.c
new file mode 100644
index 0000000000..d6c26a5b23
--- /dev/null
+++ b/drivers/sysreset/sysreset_socfpga.c
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Pepperl+Fuchs
+ * Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <sysreset.h>
+#include <asm/io.h>
+#include <asm/arch/reset_manager.h>
+
+struct socfpga_sysreset_data {
+	struct socfpga_reset_manager *rstmgr_base;
+};
+
+static int socfpga_sysreset_request(struct udevice *dev,
+				    enum sysreset_t type)
+{
+	struct socfpga_sysreset_data *data = dev_get_priv(dev);
+
+	switch (type) {
+	case SYSRESET_WARM:
+		writel(BIT(RSTMGR_CTRL_SWWARMRSTREQ_LSB),
+		       &data->rstmgr_base->ctrl);
+		break;
+	case SYSRESET_COLD:
+		writel(BIT(RSTMGR_CTRL_SWCOLDRSTREQ_LSB),
+		       &data->rstmgr_base->ctrl);
+		break;
+	default:
+		return -EPROTONOSUPPORT;
+	}
+	return -EINPROGRESS;
+}
+
+static int socfpga_sysreset_probe(struct udevice *dev)
+{
+	struct socfpga_sysreset_data *data = dev_get_priv(dev);
+
+	data->rstmgr_base = devfdt_get_addr_ptr(dev);
+	return 0;
+}
+
+static struct sysreset_ops socfpga_sysreset = {
+	.request = socfpga_sysreset_request,
+};
+
+U_BOOT_DRIVER(sysreset_socfpga) = {
+	.id	= UCLASS_SYSRESET,
+	.name	= "socfpga_sysreset",
+	.priv_auto_alloc_size = sizeof(struct socfpga_sysreset_data),
+	.ops	= &socfpga_sysreset,
+	.probe	= socfpga_sysreset_probe,
+};
-- 
2.20.1

[U-Boot] [PATCH v4 3/4] sysreset: socfpga: stratix10: add sysreset driver

[Simon Goldschmidt]

This adds a UCLASS_SYSRESET sysreset driver for socfgpa stratix10.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
---

Changes in v4:
- adapt MAINTAINERS to the new file

Changes in v3:
- moved socfpga stratix sysreset driver to extra patch

Changes in v2: None

 MAINTAINERS                             |  2 +-
 drivers/sysreset/Kconfig                |  7 ++++++
 drivers/sysreset/Makefile               |  1 +
 drivers/sysreset/sysreset_socfpga_s10.c | 29 +++++++++++++++++++++++++
 4 files changed, 38 insertions(+), 1 deletion(-)
 create mode 100644 drivers/sysreset/sysreset_socfpga_s10.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 8031cc92f5..495510863f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -94,7 +94,7 @@ M:	Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
 S:	Maintainted
 T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-socfpga.git
 F:	arch/arm/mach-socfpga/
-F:	drivers/sysreset/sysreset_socfpga.c
+F:	drivers/sysreset/sysreset_socfpga*
 
 ARM AMLOGIC SOC SUPPORT
 M:	Neil Armstrong <narmstrong@baylibre.com>
diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig
index 4ca635742f..90c41ab44d 100644
--- a/drivers/sysreset/Kconfig
+++ b/drivers/sysreset/Kconfig
@@ -62,6 +62,13 @@ config SYSRESET_SOCFPGA
 	  This enables the system reset driver support for Intel SOCFPGA SoCs
 	  (Cyclone 5, Arria 5 and Arria 10).
 
+config SYSRESET_SOCFPGA_S10
+	bool "Enable support for Intel SOCFPGA Stratix 10"
+	depends on ARCH_SOCFPGA && TARGET_SOCFPGA_STRATIX10
+	help
+	  This enables the system reset driver support for Intel SOCFPGA
+	  Stratix SoCs.
+
 config SYSRESET_TI_SCI
 	bool "TI System Control Interface (TI SCI) system reset driver"
 	depends on TI_SCI_PROTOCOL
diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
index 180e46301d..cf01492295 100644
--- a/drivers/sysreset/Makefile
+++ b/drivers/sysreset/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_SYSRESET_MCP83XX) += sysreset_mpc83xx.o
 obj-$(CONFIG_SYSRESET_MICROBLAZE) += sysreset_microblaze.o
 obj-$(CONFIG_SYSRESET_PSCI) += sysreset_psci.o
 obj-$(CONFIG_SYSRESET_SOCFPGA) += sysreset_socfpga.o
+obj-$(CONFIG_SYSRESET_SOCFPGA_S10) += sysreset_socfpga_s10.o
 obj-$(CONFIG_SYSRESET_TI_SCI) += sysreset-ti-sci.o
 obj-$(CONFIG_SYSRESET_SYSCON) += sysreset_syscon.o
 obj-$(CONFIG_SYSRESET_WATCHDOG) += sysreset_watchdog.o
diff --git a/drivers/sysreset/sysreset_socfpga_s10.c b/drivers/sysreset/sysreset_socfpga_s10.c
new file mode 100644
index 0000000000..9837aadf64
--- /dev/null
+++ b/drivers/sysreset/sysreset_socfpga_s10.c
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Pepperl+Fuchs
+ * Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <sysreset.h>
+#include <asm/arch/mailbox_s10.h>
+
+static int socfpga_sysreset_request(struct udevice *dev,
+				    enum sysreset_t type)
+{
+	puts("Mailbox: Issuing mailbox cmd REBOOT_HPS\n");
+	mbox_reset_cold();
+	return -EINPROGRESS;
+}
+
+static struct sysreset_ops socfpga_sysreset = {
+	.request = socfpga_sysreset_request,
+};
+
+U_BOOT_DRIVER(sysreset_socfpga) = {
+	.id	= UCLASS_SYSRESET,
+	.name	= "socfpga_sysreset",
+	.ops	= &socfpga_sysreset,
+};
-- 
2.20.1

[U-Boot] [PATCH v4 4/4] sysreset: add support for socfpga sysreset

[Simon Goldschmidt]

This moves sysreset support for socfgpa from ad-hoc code in mach-socfpga
to a UCLASS_SYSRESET based dm driver.

A side effect is that gen5 and a10 can now select between cold and warm
reset.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
---

Changes in v4:
- adapt to patch that separates drivers/sysreset from drivers/misc
  for SPL: select SPL_SYSRESET, not SPL_DRIVERS_MISC_SUPPORT

Changes in v3:
- this patch enables the new drivers and drops the ad-hoc code

Changes in v2:
- adapt to patch that separates drivers/sysreset from drivers/misc
  for SPL: select SPL_SYSRESET_SUPPORT, not SPL_DRIVERS_MISC_SUPPORT
- separate gen5/a10 driver from s10 driver
- as sysreset is a function of rstmgr, bind the sysreset drivers
  from rstmgr to get the base address instead of hardcoding it

 arch/arm/Kconfig                      |  4 +++
 arch/arm/mach-socfpga/Makefile        |  1 -
 arch/arm/mach-socfpga/reset_manager.c | 41 ---------------------------
 drivers/reset/reset-socfpga.c         | 19 +++++++++++++
 4 files changed, 23 insertions(+), 42 deletions(-)
 delete mode 100644 arch/arm/mach-socfpga/reset_manager.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 5ab9cbe832..d1da98e111 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -894,10 +894,14 @@ config ARCH_SOCFPGA
 	select SPL_OF_CONTROL
 	select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10
 	select SPL_SERIAL_SUPPORT
+	select SPL_SYSRESET
 	select SPL_WATCHDOG_SUPPORT
 	select SUPPORT_SPL
 	select SYS_NS16550
 	select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
+	select SYSRESET
+	select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
+	select SYSRESET_SOCFPGA_STRATIX10 if TARGET_SOCFPGA_STRATIX10
 	imply CMD_DM
 	imply CMD_MTDPARTS
 	imply CRC32_VERIFY
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index e66720447f..fc1181cb27 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -8,7 +8,6 @@
 obj-y	+= board.o
 obj-y	+= clock_manager.o
 obj-y	+= misc.o
-obj-y	+= reset_manager.o
 
 ifdef CONFIG_TARGET_SOCFPGA_GEN5
 obj-y	+= clock_manager_gen5.o
diff --git a/arch/arm/mach-socfpga/reset_manager.c b/arch/arm/mach-socfpga/reset_manager.c
deleted file mode 100644
index e0a01ed07a..0000000000
--- a/arch/arm/mach-socfpga/reset_manager.c
+++ /dev/null
@@ -1,41 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- *  Copyright (C) 2013 Altera Corporation <www.altera.com>
- */
-
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/reset_manager.h>
-
-#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
-#include <asm/arch/mailbox_s10.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if !defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
-static const struct socfpga_reset_manager *reset_manager_base =
-		(void *)SOCFPGA_RSTMGR_ADDRESS;
-#endif
-
-/*
- * Write the reset manager register to cause reset
- */
-void reset_cpu(ulong addr)
-{
-	/* request a warm reset */
-#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
-	puts("Mailbox: Issuing mailbox cmd REBOOT_HPS\n");
-	mbox_reset_cold();
-#else
-	writel(1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB,
-	       &reset_manager_base->ctrl);
-#endif
-	/*
-	 * infinite loop here as watchdog will trigger and reset
-	 * the processor
-	 */
-	while (1)
-		;
-}
diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c
index ee4cbcb02f..822a3fe265 100644
--- a/drivers/reset/reset-socfpga.c
+++ b/drivers/reset/reset-socfpga.c
@@ -14,6 +14,7 @@
 
 #include <common.h>
 #include <dm.h>
+#include <dm/lists.h>
 #include <dm/of_access.h>
 #include <reset-uclass.h>
 #include <linux/bitops.h>
@@ -130,6 +131,23 @@ static int socfpga_reset_remove(struct udevice *dev)
 	return 0;
 }
 
+static int socfpga_reset_bind(struct udevice *dev)
+{
+	int ret;
+	struct udevice *sys_child;
+
+	/*
+	 * The sysreset driver does not have a device node, so bind it here.
+	 * Bind it to the node, too, so that it can get its base address.
+	 */
+	ret = device_bind_driver_to_node(dev, "socfpga_sysreset", "sysreset",
+					 dev->node, &sys_child);
+	if (ret)
+		debug("Warning: No sysreset driver: ret=%d\n", ret);
+
+	return 0;
+}
+
 static const struct udevice_id socfpga_reset_match[] = {
 	{ .compatible = "altr,rst-mgr" },
 	{ /* sentinel */ },
@@ -139,6 +157,7 @@ U_BOOT_DRIVER(socfpga_reset) = {
 	.name = "socfpga-reset",
 	.id = UCLASS_RESET,
 	.of_match = socfpga_reset_match,
+	.bind = socfpga_reset_bind,
 	.probe = socfpga_reset_probe,
 	.priv_auto_alloc_size = sizeof(struct socfpga_reset_data),
 	.ops = &socfpga_reset_ops,
-- 
2.20.1

[U-Boot] [PATCH v4 1/4] arm: socfpga: rst: add register definition for cold reset

[Marek Vasut]

On 7/15/19 9:47 PM, Simon Goldschmidt wrote:
> This adds a define for the bit in rstmgr's ctrl regiser that issues
> a cold reset (we had a define for the warm reset bit only) in preparation
> for a proper sysrese driver.
> 

Applied all four, thanks.

-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v4 1/4] arm: socfpga: rst: add register definition for cold reset

[Simon Goldschmidt]

Am 21.07.2019 um 12:45 schrieb Marek Vasut:
> On 7/15/19 9:47 PM, Simon Goldschmidt wrote:
>> This adds a define for the bit in rstmgr's ctrl regiser that issues
>> a cold reset (we had a define for the warm reset bit only) in preparation
>> for a proper sysrese driver.
>>
> 
> Applied all four, thanks.
> 

Where did you push these? I see them at gitlab but not on github, is 
your github mirror dead then?

Regards,
Simon

[U-Boot] [PATCH v4 1/4] arm: socfpga: rst: add register definition for cold reset

[Marek Vasut]

On 7/23/19 8:37 PM, Simon Goldschmidt wrote:
> Am 21.07.2019 um 12:45 schrieb Marek Vasut:
>> On 7/15/19 9:47 PM, Simon Goldschmidt wrote:
>>> This adds a define for the bit in rstmgr's ctrl regiser that issues
>>> a cold reset (we had a define for the warm reset bit only) in
>>> preparation
>>> for a proper sysrese driver.
>>>
>>
>> Applied all four, thanks.
>>
> 
> Where did you push these? I see them at gitlab but not on github, is
> your github mirror dead then?

https://github.com/marex/u-boot-socfpga/commits/master lists them just
fine. Note that gitlab is the primary repo.

[U-Boot] [PATCH v4 1/4] arm: socfpga: rst: add register definition for cold reset

[Simon Goldschmidt]

Am 23.07.2019 um 21:09 schrieb Marek Vasut:
> On 7/23/19 8:37 PM, Simon Goldschmidt wrote:
>> Am 21.07.2019 um 12:45 schrieb Marek Vasut:
>>> On 7/15/19 9:47 PM, Simon Goldschmidt wrote:
>>>> This adds a define for the bit in rstmgr's ctrl regiser that issues
>>>> a cold reset (we had a define for the warm reset bit only) in
>>>> preparation
>>>> for a proper sysrese driver.
>>>>
>>>
>>> Applied all four, thanks.
>>>
>>
>> Where did you push these? I see them at gitlab but not on github, is
>> your github mirror dead then?
> 
> https://github.com/marex/u-boot-socfpga/commits/master lists them just
> fine. Note that gitlab is the primary repo.
> 

Hmm, right. Sorry, I must have done something wrong.

I have been using github as upstream because of denx.de performance 
issues. I have now switched to gitlab, let's see if performance stays as 
good as it is now :-)

Regards,
Simon

[U-Boot] [PATCH v4 1/4] arm: socfpga: rst: add register definition for cold reset

[Marek Vasut]

On 7/23/19 9:12 PM, Simon Goldschmidt wrote:
> Am 23.07.2019 um 21:09 schrieb Marek Vasut:
>> On 7/23/19 8:37 PM, Simon Goldschmidt wrote:
>>> Am 21.07.2019 um 12:45 schrieb Marek Vasut:
>>>> On 7/15/19 9:47 PM, Simon Goldschmidt wrote:
>>>>> This adds a define for the bit in rstmgr's ctrl regiser that issues
>>>>> a cold reset (we had a define for the warm reset bit only) in
>>>>> preparation
>>>>> for a proper sysrese driver.
>>>>>
>>>>
>>>> Applied all four, thanks.
>>>>
>>>
>>> Where did you push these? I see them at gitlab but not on github, is
>>> your github mirror dead then?
>>
>> https://github.com/marex/u-boot-socfpga/commits/master lists them just
>> fine. Note that gitlab is the primary repo.
>>
> 
> Hmm, right. Sorry, I must have done something wrong.
> 
> I have been using github as upstream

It never was upstream, please don't use it as such. It's a necessary
mirror for the travis CI, that's all.

[U-Boot] [PATCH v4 1/4] arm: socfpga: rst: add register definition for cold reset

[Simon Goldschmidt]

Am 23.07.2019 um 21:26 schrieb Marek Vasut:
> On 7/23/19 9:12 PM, Simon Goldschmidt wrote:
>> Am 23.07.2019 um 21:09 schrieb Marek Vasut:
>>> On 7/23/19 8:37 PM, Simon Goldschmidt wrote:
>>>> Am 21.07.2019 um 12:45 schrieb Marek Vasut:
>>>>> On 7/15/19 9:47 PM, Simon Goldschmidt wrote:
>>>>>> This adds a define for the bit in rstmgr's ctrl regiser that issues
>>>>>> a cold reset (we had a define for the warm reset bit only) in
>>>>>> preparation
>>>>>> for a proper sysrese driver.
>>>>>>
>>>>>
>>>>> Applied all four, thanks.
>>>>>
>>>>
>>>> Where did you push these? I see them at gitlab but not on github, is
>>>> your github mirror dead then?
>>>
>>> https://github.com/marex/u-boot-socfpga/commits/master lists them just
>>> fine. Note that gitlab is the primary repo.
>>>
>>
>> Hmm, right. Sorry, I must have done something wrong.
>>
>> I have been using github as upstream
> 
> It never was upstream, please don't use it as such. It's a necessary
> mirror for the travis CI, that's all.
> 

Noted. Given the bad connectivity to the old denx git, I sometimes had 
no other option. I hope that's better now.

Regards,
Simon

[U-Boot] [PATCH v4 1/4] arm: socfpga: rst: add register definition for cold reset

[Marek Vasut]

On 7/23/19 9:27 PM, Simon Goldschmidt wrote:
> Am 23.07.2019 um 21:26 schrieb Marek Vasut:
>> On 7/23/19 9:12 PM, Simon Goldschmidt wrote:
>>> Am 23.07.2019 um 21:09 schrieb Marek Vasut:
>>>> On 7/23/19 8:37 PM, Simon Goldschmidt wrote:
>>>>> Am 21.07.2019 um 12:45 schrieb Marek Vasut:
>>>>>> On 7/15/19 9:47 PM, Simon Goldschmidt wrote:
>>>>>>> This adds a define for the bit in rstmgr's ctrl regiser that issues
>>>>>>> a cold reset (we had a define for the warm reset bit only) in
>>>>>>> preparation
>>>>>>> for a proper sysrese driver.
>>>>>>>
>>>>>>
>>>>>> Applied all four, thanks.
>>>>>>
>>>>>
>>>>> Where did you push these? I see them at gitlab but not on github, is
>>>>> your github mirror dead then?
>>>>
>>>> https://github.com/marex/u-boot-socfpga/commits/master lists them just
>>>> fine. Note that gitlab is the primary repo.
>>>>
>>>
>>> Hmm, right. Sorry, I must have done something wrong.
>>>
>>> I have been using github as upstream
>>
>> It never was upstream, please don't use it as such. It's a necessary
>> mirror for the travis CI, that's all.
>>
> 
> Noted. Given the bad connectivity to the old denx git, I sometimes had
> no other option. I hope that's better now.

I never had those problems, but the gitlab instance is on a different
server. If you have connectivity issues, please report them.