Re: [PATCH v1 4/8] clk: imx: Add i.MXRT11xx pllv3 variant

[Sean Anderson <seanga2@gmail.com>]

On 3/17/22 2:32 PM, Jesse Taube wrote:
> The i.MXRT11 series has two new pll types but are variants of existing.
> This patch adds the ability to read one of the pll types' frequency
> as it can't be changed unlike the generic pll it also has the
> division factors swapped.
> 
> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
> ---
>   drivers/clk/imx/clk-pllv3.c | 44 +++++++++++++++++++++++++++++++++++++
>   drivers/clk/imx/clk.h       |  1 +
>   2 files changed, 45 insertions(+)
> 
> diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c
> index 077757efcb..511c973e5c 100644
> --- a/drivers/clk/imx/clk-pllv3.c
> +++ b/drivers/clk/imx/clk-pllv3.c
> @@ -21,6 +21,7 @@
>   #define UBOOT_DM_CLK_IMX_PLLV3_USB	"imx_clk_pllv3_usb"
>   #define UBOOT_DM_CLK_IMX_PLLV3_AV	"imx_clk_pllv3_av"
>   #define UBOOT_DM_CLK_IMX_PLLV3_ENET     "imx_clk_pllv3_enet"
> +#define UBOOT_DM_CLK_IMX_PLLV3_GENV2	"imx_clk_pllv3_genericv2"
>   
>   #define PLL_NUM_OFFSET		0x10
>   #define PLL_DENOM_OFFSET	0x20
> @@ -42,6 +43,30 @@ struct clk_pllv3 {
>   
>   #define to_clk_pllv3(_clk) container_of(_clk, struct clk_pllv3, clk)
>   
> +static ulong clk_pllv3_genericv2_get_rate(struct clk *clk)
> +{
> +	struct clk_pllv3 *pll = to_clk_pllv3(dev_get_clk_ptr(clk->dev));
> +	unsigned long parent_rate = clk_get_parent_rate(clk);
> +
> +	u32 div = (readl(pll->base) >> pll->div_shift) & pll->div_mask;
> +
> +	return (div == 0) ? parent_rate * 22 : parent_rate * 20;
> +}
> +
> +static ulong clk_pllv3_genericv2_set_rate(struct clk *clk, ulong rate)
> +{
> +	struct clk_pllv3 *pll = to_clk_pllv3(clk);
> +	unsigned long parent_rate = clk_get_parent_rate(clk);
> +
> +	u32 div = (readl(pll->base) >> pll->div_shift) & pll->div_mask;
> +	u32 val = (div == 0) ? parent_rate * 22 : parent_rate * 20;
> +
> +	if (rate == val)
> +		return 0;
> +
> +	return -EINVAL;
> +}
> +
>   static ulong clk_pllv3_generic_get_rate(struct clk *clk)
>   {
>   	struct clk_pllv3 *pll = to_clk_pllv3(dev_get_clk_ptr(clk->dev));
> @@ -120,6 +145,13 @@ static const struct clk_ops clk_pllv3_generic_ops = {
>   	.set_rate	= clk_pllv3_generic_set_rate,
>   };
>   
> +static const struct clk_ops clk_pllv3_genericv2_ops = {
> +	.get_rate	= clk_pllv3_genericv2_get_rate,
> +	.enable		= clk_pllv3_generic_enable,
> +	.disable	= clk_pllv3_generic_disable,
> +	.set_rate	= clk_pllv3_genericv2_set_rate,
> +};
> +
>   static ulong clk_pllv3_sys_get_rate(struct clk *clk)
>   {
>   	struct clk_pllv3 *pll = to_clk_pllv3(clk);
> @@ -269,6 +301,11 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
>   		pll->div_shift = 0;
>   		pll->powerup_set = false;
>   		break;
> +	case IMX_PLLV3_GENERICV2:
> +		drv_name = UBOOT_DM_CLK_IMX_PLLV3_GENV2;
> +		pll->div_shift = 0;
> +		pll->powerup_set = false;
> +		break;
>   	case IMX_PLLV3_SYS:
>   		drv_name = UBOOT_DM_CLK_IMX_PLLV3_SYS;
>   		pll->div_shift = 0;
> @@ -313,6 +350,13 @@ U_BOOT_DRIVER(clk_pllv3_generic) = {
>   	.flags = DM_FLAG_PRE_RELOC,
>   };
>   
> +U_BOOT_DRIVER(clk_pllv3_genericv2) = {
> +	.name	= UBOOT_DM_CLK_IMX_PLLV3_GENV2,
> +	.id	= UCLASS_CLK,
> +	.ops	= &clk_pllv3_genericv2_ops,
> +	.flags = DM_FLAG_PRE_RELOC,
> +};
> +
>   U_BOOT_DRIVER(clk_pllv3_sys) = {
>   	.name	= UBOOT_DM_CLK_IMX_PLLV3_SYS,
>   	.id	= UCLASS_CLK,
> diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
> index 60f287046b..10670252b1 100644
> --- a/drivers/clk/imx/clk.h
> +++ b/drivers/clk/imx/clk.h
> @@ -10,6 +10,7 @@
>   
>   enum imx_pllv3_type {
>   	IMX_PLLV3_GENERIC,
> +	IMX_PLLV3_GENERICV2,
>   	IMX_PLLV3_SYS,
>   	IMX_PLLV3_USB,
>   	IMX_PLLV3_USB_VF610,
> 

Acked-by: Sean Anderson <seanga2@gmail.com>