* [U-Boot] [PATCH v3 0/2] 85xx: Support for XPedite5200
@ 2008-12-01 19:47 Peter Tyser
2008-12-01 19:47 ` [U-Boot] [PATCH v3 1/2] 85xx: Add PORDEVSR_PCI1 define Peter Tyser
0 siblings, 1 reply; 9+ messages in thread
From: Peter Tyser @ 2008-12-01 19:47 UTC (permalink / raw)
To: u-boot
These 2 patches add support for the XPedite5200 SBC -
a MPC8548-based PMC card made by Extreme Engineering
Solutions.
The patches require the following 2 patches to be applied first:
- pca953x: Add support for PCA953x I2C gpio devices
- XPedite5370 board support
changes since v1:
- Change alignment by spaces to alignment by tabs
- Fixed typos in host_agent_cfg/io_port_cfg
- Fixed variable declaration in code
- Fixed some lines longer than 80 chars
- Cleaned up environment configuration defines
- Fixed multiline comment style
changes since v2:
- Removed CONFIG_L1_INIT_RAM reference
Best,
Peter
Peter Tyser (2):
85xx: Add PORDEVSR_PCI1 define
XPedite5200 board support
MAINTAINERS | 1 +
MAKEALL | 1 +
Makefile | 3 +
board/xes/common/Makefile | 3 +-
board/xes/common/actl_nand.c | 65 ++++
board/xes/common/fsl_85xx_pci.c | 103 +++++++-
board/xes/xpedite5200/Makefile | 55 ++++
board/xes/xpedite5200/config.mk | 34 +++
board/xes/xpedite5200/ddr.c | 91 ++++++
board/xes/xpedite5200/law.c | 51 ++++
board/xes/xpedite5200/tlb.c | 85 ++++++
board/xes/xpedite5200/u-boot.lds | 145 +++++++++
board/xes/xpedite5200/xpedite5200.c | 125 ++++++++
include/asm-ppc/immap_85xx.h | 1 +
include/configs/XPEDITE5200.h | 546 +++++++++++++++++++++++++++++++++++
15 files changed, 1304 insertions(+), 5 deletions(-)
create mode 100644 board/xes/common/actl_nand.c
create mode 100644 board/xes/xpedite5200/Makefile
create mode 100644 board/xes/xpedite5200/config.mk
create mode 100644 board/xes/xpedite5200/ddr.c
create mode 100644 board/xes/xpedite5200/law.c
create mode 100644 board/xes/xpedite5200/tlb.c
create mode 100644 board/xes/xpedite5200/u-boot.lds
create mode 100644 board/xes/xpedite5200/xpedite5200.c
create mode 100644 include/configs/XPEDITE5200.h
^ permalink raw reply [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH v3 1/2] 85xx: Add PORDEVSR_PCI1 define
2008-12-01 19:47 [U-Boot] [PATCH v3 0/2] 85xx: Support for XPedite5200 Peter Tyser
@ 2008-12-01 19:47 ` Peter Tyser
2008-12-01 19:47 ` [U-Boot] [PATCH v3 2/2] XPedite5200 board support Peter Tyser
` (2 more replies)
0 siblings, 3 replies; 9+ messages in thread
From: Peter Tyser @ 2008-12-01 19:47 UTC (permalink / raw)
To: u-boot
Add define used to determine if PCI1 interface is in PCI or PCIX mode.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
---
include/asm-ppc/immap_85xx.h | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h
index 75b451d..cb6e3d8 100644
--- a/include/asm-ppc/immap_85xx.h
+++ b/include/asm-ppc/immap_85xx.h
@@ -1569,6 +1569,7 @@ typedef struct ccsr_gur {
#define MPC85xx_PORDEVSR_SGMII3_DIS 0x08000000
#define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000
#define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000
+#define MPC85xx_PORDEVSR_PCI1 0x00800000
#define MPC85xx_PORDEVSR_IO_SEL 0x00780000
#define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000
#define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000
--
1.6.0.2.GIT
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH v3 2/2] XPedite5200 board support
2008-12-01 19:47 ` [U-Boot] [PATCH v3 1/2] 85xx: Add PORDEVSR_PCI1 define Peter Tyser
@ 2008-12-01 19:47 ` Peter Tyser
2008-12-01 20:17 ` Jon Loeliger
2008-12-03 10:35 ` [U-Boot] Problem in Optimizing the Boot Loader in Start.s of MPC85xx Vignesh Kumar B
2008-12-04 20:58 ` [U-Boot] [PATCH v3 1/2] 85xx: Add PORDEVSR_PCI1 define Andy Fleming
2 siblings, 1 reply; 9+ messages in thread
From: Peter Tyser @ 2008-12-01 19:47 UTC (permalink / raw)
To: u-boot
Initial support for Extreme Engineering Solutions XPedite5200 -
a MPC8548-based PMC single board computer.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
---
MAINTAINERS | 1 +
MAKEALL | 1 +
Makefile | 3 +
board/xes/common/Makefile | 3 +-
board/xes/common/actl_nand.c | 65 ++++
board/xes/common/fsl_85xx_pci.c | 103 +++++++-
board/xes/xpedite5200/Makefile | 55 ++++
board/xes/xpedite5200/config.mk | 34 +++
board/xes/xpedite5200/ddr.c | 91 ++++++
board/xes/xpedite5200/law.c | 51 ++++
board/xes/xpedite5200/tlb.c | 85 ++++++
board/xes/xpedite5200/u-boot.lds | 145 +++++++++
board/xes/xpedite5200/xpedite5200.c | 125 ++++++++
include/configs/XPEDITE5200.h | 546 +++++++++++++++++++++++++++++++++++
14 files changed, 1303 insertions(+), 5 deletions(-)
create mode 100644 board/xes/common/actl_nand.c
create mode 100644 board/xes/xpedite5200/Makefile
create mode 100644 board/xes/xpedite5200/config.mk
create mode 100644 board/xes/xpedite5200/ddr.c
create mode 100644 board/xes/xpedite5200/law.c
create mode 100644 board/xes/xpedite5200/tlb.c
create mode 100644 board/xes/xpedite5200/u-boot.lds
create mode 100644 board/xes/xpedite5200/xpedite5200.c
create mode 100644 include/configs/XPEDITE5200.h
diff --git a/MAINTAINERS b/MAINTAINERS
index ee98824..551f370 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -413,6 +413,7 @@ Rune Torgersen <runet@innovsys.com>
Peter Tyser <ptyser@xes-inc.com>
+ XPEDITE5200 MPC8548
XPEDITE5370 MPC8572
David Updegraff <dave@cray.com>
diff --git a/MAKEALL b/MAKEALL
index 1328514..216e4cd 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -376,6 +376,7 @@ LIST_85xx=" \
TQM8548 \
TQM8555 \
TQM8560 \
+ XPEDITE5200 \
XPEDITE5370 \
"
diff --git a/Makefile b/Makefile
index ae3ec22..20e6954 100644
--- a/Makefile
+++ b/Makefile
@@ -2454,6 +2454,9 @@ TQM8560_config: unconfig
echo "#define CONFIG_BOARDNAME \"TQM$${CTYPE}\"">>$(obj)include/config.h;
@$(MKCONFIG) -a TQM85xx ppc mpc85xx tqm85xx tqc
+XPEDITE5200_config: unconfig
+ @$(MKCONFIG) $(@:_config=) ppc mpc85xx xpedite5200 xes
+
XPEDITE5370_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc85xx xpedite5370 xes
diff --git a/board/xes/common/Makefile b/board/xes/common/Makefile
index c5cd633..e7620f4 100644
--- a/board/xes/common/Makefile
+++ b/board/xes/common/Makefile
@@ -29,9 +29,10 @@ endif
LIB = $(obj)lib$(VENDOR).a
+COBJS-$(CONFIG_FSL_PCI_INIT) += fsl_85xx_pci.o
COBJS-$(CONFIG_MPC8572) += fsl_8572_clk.o
COBJS-$(CONFIG_MPC85xx) += fsl_85xx_ddr.o
-COBJS-$(CONFIG_FSL_PCI_INIT) += fsl_85xx_pci.o
+COBJS-$(CONFIG_NAND_ACTL) += actl_nand.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
diff --git a/board/xes/common/actl_nand.c b/board/xes/common/actl_nand.c
new file mode 100644
index 0000000..465aeb0
--- /dev/null
+++ b/board/xes/common/actl_nand.c
@@ -0,0 +1,65 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ *
+ * This driver support NAND devices which have address lines
+ * connected as ALE and CLE inputs.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <nand.h>
+#include <asm/io.h>
+
+/*
+ * Hardware specific access to control-lines
+ */
+static void nand_addr_hwcontrol(struct mtd_info *mtd, int cmd, uint ctrl)
+{
+ struct nand_chip *this = mtd->priv;
+ ulong IO_ADDR_W;
+
+ if (ctrl & NAND_CTRL_CHANGE) {
+ IO_ADDR_W = (ulong)this->IO_ADDR_W;
+
+ IO_ADDR_W &= ~(CONFIG_SYS_NAND_ACTL_CLE |
+ CONFIG_SYS_NAND_ACTL_ALE |
+ CONFIG_SYS_NAND_ACTL_NCE);
+ if (ctrl & NAND_CLE)
+ IO_ADDR_W |= CONFIG_SYS_NAND_ACTL_CLE;
+ if (ctrl & NAND_ALE)
+ IO_ADDR_W |= CONFIG_SYS_NAND_ACTL_ALE;
+ if (ctrl & NAND_NCE)
+ IO_ADDR_W |= CONFIG_SYS_NAND_ACTL_NCE;
+
+ this->IO_ADDR_W = (void *)IO_ADDR_W;
+ }
+
+ if (cmd != NAND_CMD_NONE)
+ writeb(cmd, this->IO_ADDR_W);
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+ nand->ecc.mode = NAND_ECC_SOFT;
+ nand->cmd_ctrl = nand_addr_hwcontrol;
+ nand->chip_delay = CONFIG_SYS_NAND_ACTL_DELAY;
+
+ return 0;
+}
diff --git a/board/xes/common/fsl_85xx_pci.c b/board/xes/common/fsl_85xx_pci.c
index b604bcc..545310b 100644
--- a/board/xes/common/fsl_85xx_pci.c
+++ b/board/xes/common/fsl_85xx_pci.c
@@ -33,6 +33,9 @@ extern void fsl_pci_init(struct pci_controller *hose);
int first_free_busno = 0;
+#ifdef CONFIG_PCI1
+static struct pci_controller pci1_hose;
+#endif
#ifdef CONFIG_PCIE1
static struct pci_controller pcie1_hose;
#endif
@@ -43,6 +46,7 @@ static struct pci_controller pcie2_hose;
static struct pci_controller pcie3_hose;
#endif
+#ifdef CONFIG_MPC8572
/* Correlate host/agent POR bits to usable info. Table 4-14 */
struct host_agent_cfg_t {
uchar pcie_root[3];
@@ -80,6 +84,38 @@ struct io_port_cfg_t {
{{0, 0, 0}, 4},
{{8, 0, 0}, 0},
};
+#elif defined CONFIG_MPC8548
+/* Correlate host/agent POR bits to usable info. Table 4-12 */
+struct host_agent_cfg_t {
+ uchar pci_host[2];
+ uchar pcie_root[1];
+ uchar rio_host;
+} host_agent_cfg[8] = {
+ {{1, 1}, {0}, 0},
+ {{1, 1}, {1}, 0},
+ {{1, 1}, {0}, 1},
+ {{0, 0}, {0}, 0}, /* reserved */
+ {{0, 1}, {1}, 0},
+ {{1, 1}, {1}, 0},
+ {{0, 1}, {1}, 1},
+ {{1, 1}, {1}, 1}
+};
+
+/* Correlate port width POR bits to usable info. Table 4-13 */
+struct io_port_cfg_t {
+ uchar pcie_width[1];
+ uchar rio_width;
+} io_port_cfg[8] = {
+ {{0}, 0},
+ {{0}, 0},
+ {{0}, 0},
+ {{4}, 4},
+ {{4}, 4},
+ {{0}, 4},
+ {{0}, 4},
+ {{8}, 0},
+};
+#endif
void pci_init_board(void)
{
@@ -93,9 +129,65 @@ void pci_init_board(void)
uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
struct pci_region *r;
- debug(" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
- devdisr, io_sel, host_agent);
+#ifdef CONFIG_PCI1
+ uint pci_spd_norm = (gur->pordevsr & MPC85xx_PORDEVSR_PCI1_SPD);
+ uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;
+ uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
+ uint pcix = gur->pordevsr & MPC85xx_PORDEVSR_PCI1;
+ uint freq = CONFIG_SYS_CLK_FREQ / 1000 / 1000;
+
+ width = 0; /* Silence compiler warning... */
+ io_sel &= 0xf; /* Silence compiler warning... */
+ pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
+ hose = &pci1_hose;
+ host = host_agent_cfg[host_agent].pci_host[0];
+ r = hose->regions;
+
+
+ if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
+ printf("\n PCI1: %d bit %s, %s %d MHz, %s, %s\n",
+ pci_32 ? 32 : 64,
+ pcix ? "PCIX" : "PCI",
+ pci_spd_norm ? ">=" : "<=",
+ pcix ? freq * 2 : freq,
+ host ? "host" : "agent",
+ pci_arb ? "arbiter" : "external-arbiter");
+ /* inbound */
+ r += fsl_pci_setup_inbound_windows(r);
+
+ /* outbound memory */
+ pci_set_region(r++,
+ CONFIG_SYS_PCI1_MEM_BASE,
+ CONFIG_SYS_PCI1_MEM_PHYS,
+ CONFIG_SYS_PCI1_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ /* outbound io */
+ pci_set_region(r++,
+ CONFIG_SYS_PCI1_IO_BASE,
+ CONFIG_SYS_PCI1_IO_PHYS,
+ CONFIG_SYS_PCI1_IO_SIZE,
+ PCI_REGION_IO);
+
+ hose->region_count = r - hose->regions;
+
+ hose->first_busno = first_free_busno;
+ pci_setup_indirect(hose, (int)&pci->cfg_addr,
+ (int)&pci->cfg_data);
+
+ fsl_pci_init(hose);
+
+ first_free_busno = hose->last_busno+1;
+ printf(" PCI1 on bus %02x - %02x\n",
+ hose->first_busno, hose->last_busno);
+ } else {
+ printf(" PCI1: disabled\n");
+ }
+#elif defined CONFIG_MPC8548
+ /* PCI1 not present on MPC8572 */
+ gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
+#endif
#ifdef CONFIG_PCIE1
pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
hose = &pcie1_hose;
@@ -138,7 +230,7 @@ void pci_init_board(void)
fsl_pci_init(hose);
- first_free_busno = hose->last_busno+1;
+ first_free_busno = hose->last_busno + 1;
printf(" PCIE1 on bus %02x - %02x\n",
hose->first_busno, hose->last_busno);
}
@@ -190,7 +282,6 @@ void pci_init_board(void)
first_free_busno = hose->last_busno+1;
printf(" PCIE2 on bus %02x - %02x\n",
hose->first_busno, hose->last_busno);
-
}
#else
gur->devdisr |= MPC85xx_DEVDISR_PCIE1; /* disable */
@@ -252,6 +343,10 @@ extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
void ft_board_pci_setup(void *blob, bd_t *bd)
{
+ /* TODO - make node name (eg pci0) dynamic */
+#ifdef CONFIG_PCI1
+ ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
+#endif
#ifdef CONFIG_PCIE1
ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
#endif
diff --git a/board/xes/xpedite5200/Makefile b/board/xes/xpedite5200/Makefile
new file mode 100644
index 0000000..02fe8fc
--- /dev/null
+++ b/board/xes/xpedite5200/Makefile
@@ -0,0 +1,55 @@
+#
+# Copyright 2008 Extreme Engineering Solutions, Inc.
+# Copyright 2004 Freescale Semiconductor.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS-y += $(BOARD).o
+COBJS-y += ddr.o
+COBJS-y += law.o
+COBJS-y += tlb.o
+
+SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(OBJS) $(SOBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/xes/xpedite5200/config.mk b/board/xes/xpedite5200/config.mk
new file mode 100644
index 0000000..be5a5c3
--- /dev/null
+++ b/board/xes/xpedite5200/config.mk
@@ -0,0 +1,34 @@
+#
+# Copyright 2008 Extreme Engineering Solutions, Inc.
+# Copyright 2004, 2007 Freescale Semiconductor.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# xpedite5200 board
+#
+ifndef TEXT_BASE
+TEXT_BASE = 0xfff80000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_E500=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8548=1
+PLATFORM_CPPFLAGS += -mrelocatable
diff --git a/board/xes/xpedite5200/ddr.c b/board/xes/xpedite5200/ddr.c
new file mode 100644
index 0000000..c5616d5
--- /dev/null
+++ b/board/xes/xpedite5200/ddr.c
@@ -0,0 +1,91 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+
+static void
+get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
+{
+ i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
+
+ /* We use soldered memory, but use an SPD EEPROM to describe it.
+ * The SPD has an unspecified dimm type, but the DDR2 initialization
+ * code requires a specific type to be specified. This sets the type
+ * as a standard unregistered SO-DIMM. */
+ if (spd->dimm_type == 0) {
+ spd->dimm_type = 0x4;
+ ((uchar *)spd)[63] += 0x4;
+ }
+}
+
+unsigned int fsl_ddr_get_mem_data_rate(void)
+{
+ return get_ddr_freq(0);
+}
+
+void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
+ unsigned int ctrl_num)
+{
+ unsigned int i;
+
+ if (ctrl_num) {
+ printf("%s: invalid ctrl_num = %d\n", __func__, ctrl_num);
+ return;
+ }
+
+ for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++)
+ get_spd(&(ctrl_dimms_spd[i]), SPD_EEPROM_ADDRESS);
+}
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ /*
+ * Factors to consider for clock adjust:
+ * - number of chips on bus
+ * - position of slot
+ * - DDR1 vs. DDR2?
+ * - ???
+ *
+ * This needs to be determined on a board-by-board basis.
+ * 0110 3/4 cycle late
+ * 0111 7/8 cycle late
+ */
+ popts->clk_adjust = 7;
+
+ /*
+ * Factors to consider for CPO:
+ * - frequency
+ * - ddr1 vs. ddr2
+ */
+ popts->cpo_override = 9;
+
+ /*
+ * Factors to consider for write data delay:
+ * - number of DIMMs
+ *
+ * 1 = 1/4 clock delay
+ * 2 = 1/2 clock delay
+ * 3 = 3/4 clock delay
+ * 4 = 1 clock delay
+ * 5 = 5/4 clock delay
+ * 6 = 3/2 clock delay
+ */
+ popts->write_data_delay = 3;
+
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 0;
+}
diff --git a/board/xes/xpedite5200/law.c b/board/xes/xpedite5200/law.c
new file mode 100644
index 0000000..386f9c5
--- /dev/null
+++ b/board/xes/xpedite5200/law.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * Notes:
+ * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ * If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+struct law_entry law_table[] = {
+ /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
+ SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+ SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+#if CONFIG_SYS_PCI1_MEM_PHYS
+ SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCI_1),
+ SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAWAR_SIZE_8M, LAW_TRGT_IF_PCI_1),
+#endif
+#if CONFIG_SYS_PCI2_MEM_PHYS
+ SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI_2),
+ SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI_2),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/xes/xpedite5200/tlb.c b/board/xes/xpedite5200/tlb.c
new file mode 100644
index 0000000..bd7bff8
--- /dev/null
+++ b/board/xes/xpedite5200/tlb.c
@@ -0,0 +1,85 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* W**G* - NOR flashes */
+ /* This will be changed to *I*G* after relocation to RAM. */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE2, CONFIG_SYS_FLASH_BASE2,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_256M, 1),
+
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_1M, 1),
+
+ /* *I*G* - NAND flash */
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_1M, 1),
+
+#if CONFIG_PCI1
+ /* *I*G* - PCI MEM */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_1G, 1),
+#endif
+
+#if CONFIG_PCI2
+ /* *I*G* - PCI MEM */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS, CONFIG_SYS_PCI2_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_256M, 1),
+#endif
+
+#if defined(CONFIG_PCI1) || defined(CONFIG_PCI2)
+ /* *I*G* - PCI IO */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_16M, 1),
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/xes/xpedite5200/u-boot.lds b/board/xes/xpedite5200/u-boot.lds
new file mode 100644
index 0000000..bd952d2
--- /dev/null
+++ b/board/xes/xpedite5200/u-boot.lds
@@ -0,0 +1,145 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2004, 2007-2008 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+PHDRS
+{
+ text PT_LOAD;
+ bss PT_LOAD;
+}
+
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ *(.text)
+ *(.got1)
+ } :text
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
+ } :text
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ .bootpg ADDR(.text) + 0x7f000 :
+ {
+ cpu/mpc85xx/start.o (.bootpg)
+ } :text = 0xffff
+
+ .resetvec ADDR(.text) + 0x7fffc :
+ {
+ *(.resetvec)
+ } :text = 0xffff
+
+ . = ADDR(.text) + 0x80000;
+
+ __bss_start = .;
+ .bss (NOLOAD) :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ } :bss
+
+ . = ALIGN(4);
+ _end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/xes/xpedite5200/xpedite5200.c b/board/xes/xpedite5200/xpedite5200.c
new file mode 100644
index 0000000..5ddfb83
--- /dev/null
+++ b/board/xes/xpedite5200/xpedite5200.c
@@ -0,0 +1,125 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2004, 2007 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <asm/immap_fsl_pci.h>
+#include <asm/io.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <gpio/pca953x.h>
+
+extern void ft_board_pci_setup(void *blob, bd_t *bd);
+
+int checkboard(void)
+{
+ volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+ volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
+
+ char *s;
+
+ printf("Board: X-ES %s PMC\n", CONFIG_SYS_BOARD_NAME);
+ printf(" ");
+ s = getenv("board_rev");
+ if (s)
+ printf("Rev %s, ", s);
+ s = getenv("serial#");
+ if (s)
+ printf("Serial# %s, ", s);
+ s = getenv("board_cfg");
+ if (s)
+ printf("Cfg %s", s);
+ printf("\n");
+
+ lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
+ lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
+ ecm->eedr = 0xffffffff; /* Clear ecm errors */
+ ecm->eeer = 0xffffffff; /* Enable ecm errors */
+
+ return 0;
+}
+
+static void flash_cs_fixup(void)
+{
+ volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+ int flash_sel;
+
+ /*
+ * Print boot dev and swap flash flash chip selects if booted from 2nd
+ * flash. Swapping chip selects presents user with a common memory
+ * map regardless of which flash was booted from.
+ */
+ flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
+ CONFIG_SYS_PCA953X_FLASH_PASS_CS));
+ printf("FLASH: Executed from FLASH%d\n", flash_sel ? 2 : 1);
+
+ if (flash_sel) {
+ lbc->br0 = CONFIG_SYS_BR1_PRELIM;
+ lbc->or0 = CONFIG_SYS_OR1_PRELIM;
+
+ lbc->br1 = CONFIG_SYS_BR0_PRELIM;
+ lbc->or1 = CONFIG_SYS_OR0_PRELIM;
+ }
+}
+
+int board_early_init_r(void)
+{
+ /* Initialize PCA9557 devices */
+ pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
+ pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0);
+
+ /*
+ * Remap NOR flash region to caching-inhibited
+ * so that flash can be erased/programmed properly.
+ */
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+
+ /* Invalidate existing TLB entry for NOR flash */
+ disable_tlb(0);
+ set_tlb(1, (CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
+ (CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_256M, 1);
+
+ flash_cs_fixup();
+
+ return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+#ifdef CONFIG_PCI
+ ft_board_pci_setup(blob, bd);
+#endif
+ ft_cpu_setup(blob, bd);
+}
+#endif
diff --git a/include/configs/XPEDITE5200.h b/include/configs/XPEDITE5200.h
new file mode 100644
index 0000000..1df6855
--- /dev/null
+++ b/include/configs/XPEDITE5200.h
@@ -0,0 +1,546 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2004-2008 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * xpedite5200 board configuration file
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_BOOKE 1 /* BOOKE */
+#define CONFIG_E500 1 /* BOOKE e500 family */
+#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
+#define CONFIG_MPC8548 1
+#define CONFIG_XPEDITE5200 1
+#define CONFIG_SYS_BOARD_NAME "XPedite5200"
+#define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
+#define CONFIG_RELOC_FIXUP_WORKS /* Fully relocate to SDRAM */
+
+#define CONFIG_PCI 1 /* Enable PCI/PCIE */
+#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
+#define CONFIG_PCI1 1 /* PCI controller 1 */
+#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
+#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
+
+/*
+ * DDR config
+ */
+#define CONFIG_FSL_DDR2
+#undef CONFIG_FSL_DDR_INTERACTIVE
+#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
+#define CONFIG_DDR_SPD
+#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
+#define SPD_EEPROM_ADDRESS 0x54
+#define CONFIG_NUM_DDR_CONTROLLERS 1
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+#define CONFIG_CHIP_SELECTS_PER_CTRL 2
+#define CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_VERY_BIG_RAM
+
+#define CONFIG_SYS_CLK_FREQ 66666666
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE /* toggle L2 cache */
+#define CONFIG_BTB /* toggle branch predition */
+#define CONFIG_ENABLE_36BIT_PHYS 1
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
+#define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */
+#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
+#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
+#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR + 0x8000)
+
+/*
+ * Diagnostics
+ */
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_SYS_MEMTEST_START 0x10000000
+#define CONFIG_SYS_MEMTEST_END 0x20000000
+
+/*
+ * Memory map
+ * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
+ * 0x8000_0000 0xbfff_ffff PCI1 Mem 1G non-cacheable
+ * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
+ * 0xe800_0000 0xe87f_ffff PCI1 IO 8M non-cacheable
+ * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
+ * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
+ * 0xf800_0000 0xfbff_ffff NOR Flash 2 64M non-cacheable
+ * 0xfc00_0000 0xffff_ffff NOR Flash 1 64M non-cacheable
+ */
+
+#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_4 | LCRR_EADC_3)
+
+/*
+ * NAND flash configuration
+ */
+#define CONFIG_SYS_NAND_BASE 0xef800000
+#define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_NAND_ACTL
+#define CONFIG_SYS_NAND_ACTL_CLE (1 << 3) /* ADDR3 is CLE */
+#define CONFIG_SYS_NAND_ACTL_ALE (1 << 4) /* ADDR4 is ALE */
+#define CONFIG_SYS_NAND_ACTL_NCE (0) /* NCE not controlled by ADDR */
+#define CONFIG_SYS_NAND_ACTL_DELAY 25
+
+/*
+ * NOR flash configuration
+ */
+#define CONFIG_SYS_FLASH_BASE 0xfc000000
+#define CONFIG_SYS_FLASH_BASE2 0xf8000000
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
+#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \
+ {0xfbf40000, 0xc0000} }
+#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+
+/*
+ * Chip select configuration
+ */
+/* NOR Flash 0 on CS0 */
+#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
+ BR_PS_16 | \
+ BR_V)
+#define CONFIG_SYS_OR0_PRELIM (OR_AM_64MB | \
+ OR_GPCM_ACS_DIV4 | \
+ OR_GPCM_SCY_8)
+
+/* NOR Flash 1 on CS1 */
+#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \
+ BR_PS_16 | \
+ BR_V)
+#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
+
+/* NAND flash on CS2 */
+#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \
+ BR_PS_8 | \
+ BR_V)
+
+/* NAND flash on CS2 */
+#define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \
+ OR_GPCM_BCTLD | \
+ OR_GPCM_CSNT | \
+ OR_GPCM_ACS_DIV4 | \
+ OR_GPCM_SCY_4 | \
+ OR_GPCM_TRLX | \
+ OR_GPCM_EHTR)
+
+/* NAND flash on CS3 */
+#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \
+ BR_PS_8 | \
+ BR_V)
+#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
+
+/*
+ * Use L1 as initial stack
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK 1
+#define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
+#define CONFIG_SYS_INIT_RAM_END 0x4000
+
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
+#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+/*
+ * Use the HUSH parser
+ */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+#define CONFIG_OF_STDOUT_VIA_ALIAS 1
+
+#define CONFIG_SYS_64BIT_VSPRINTF 1
+#define CONFIG_SYS_64BIT_STRTOUL 1
+
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C /* I2C with hardware support */
+#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C_OFFSET 0x3000
+#define CONFIG_SYS_I2C2_OFFSET 0x3100
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
+
+/* I2C EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
+
+/* I2C RTC */
+#define CONFIG_RTC_M41T11 1
+#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+#define CONFIG_SYS_M41T11_BASE_YEAR 2000
+
+/* GPIO */
+#define CONFIG_PCA953X
+#define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
+#define CONFIG_SYS_I2C_PCA953X_ADDR1 0x19
+#define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
+
+/* PCA957 @ 0x18 */
+#define CONFIG_SYS_PCA953X_BRD_CFG0 0x01
+#define CONFIG_SYS_PCA953X_BRD_CFG1 0x02
+#define CONFIG_SYS_PCA953X_BRD_CFG2 0x04
+#define CONFIG_SYS_PCA953X_XMC_ROOT0 0x08
+#define CONFIG_SYS_PCA953X_FLASH_PASS_CS 0x10
+#define CONFIG_SYS_PCA953X_FLASH_WP 0x20
+#define CONFIG_SYS_PCA953X_MONARCH 0x40
+#define CONFIG_SYS_PCA953X_EREADY 0x80
+
+/* PCA957 @ 0x19 */
+#define CONFIG_SYS_PCA953X_P14_IO0 0x01
+#define CONFIG_SYS_PCA953X_P14_IO1 0x02
+#define CONFIG_SYS_PCA953X_P14_IO2 0x04
+#define CONFIG_SYS_PCA953X_P14_IO3 0x08
+#define CONFIG_SYS_PCA953X_P14_IO4 0x10
+#define CONFIG_SYS_PCA953X_P14_IO5 0x20
+#define CONFIG_SYS_PCA953X_P14_IO6 0x40
+#define CONFIG_SYS_PCA953X_P14_IO7 0x80
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE 0x40000000 /* 1G */
+#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS 0xe8000000
+#define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 1M */
+
+/*
+ * Networking options
+ */
+#define CONFIG_TSEC_ENET /* tsec ethernet support */
+#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
+#define CONFIG_NET_MULTI 1
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_ETHPRIME "eTSEC1"
+
+#define CONFIG_TSEC1 1
+#define CONFIG_TSEC1_NAME "eTSEC1"
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC1_PHY_ADDR 1
+#define TSEC1_PHYIDX 0
+#define CONFIG_HAS_ETH0
+
+#define CONFIG_TSEC2 1
+#define CONFIG_TSEC2_NAME "eTSEC2"
+#define TSEC2_FLAGS TSEC_GIGABIT
+#define TSEC2_PHY_ADDR 2
+#define TSEC2_PHYIDX 0
+#define CONFIG_HAS_ETH1
+
+#define CONFIG_TSEC3 1
+#define CONFIG_TSEC3_NAME "eTSEC3"
+#define TSEC3_FLAGS TSEC_GIGABIT
+#define TSEC3_PHY_ADDR 3
+#define TSEC3_PHYIDX 0
+#define CONFIG_HAS_ETH2
+
+#define CONFIG_TSEC4 1
+#define CONFIG_TSEC4_NAME "eTSEC4"
+#define TSEC4_FLAGS TSEC_GIGABIT
+#define TSEC4_PHY_ADDR 4
+#define TSEC4_PHYIDX 0
+#define CONFIG_HAS_ETH3
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+
+/*
+ * Command configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCA953X
+#define CONFIG_CMD_PCA953X_INFO
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SNTP
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
+#define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */
+#define CONFIG_PANIC_HANG /* do not reset board on panic */
+#define CONFIG_PREBOOT /* enable preboot variable */
+#define CONFIG_FIT 1
+#define CONFIG_FIT_VERBOSE 1
+#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
+#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 16 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
+
+/*
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
+#define CONFIG_ENV_SIZE 0x8000
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024))
+
+/*
+ * Flash memory map:
+ * fff80000 - ffffffff Pri U-Boot (512 KB)
+ * fff40000 - fff7ffff Pri U-Boot Environment (256 KB)
+ * fff00000 - fff3ffff Pri FDT (256KB)
+ * fef00000 - ffefffff Pri OS image (16MB)
+ * fc000000 - feefffff Pri OS Use/Filesystem (47MB)
+ *
+ * fbf80000 - fbffffff Sec U-Boot (512 KB)
+ * fbf40000 - fbf7ffff Sec U-Boot Environment (256 KB)
+ * fbf00000 - fbf3ffff Sec FDT (256KB)
+ * faf00000 - fbefffff Sec OS image (16MB)
+ * f8000000 - faefffff Sec OS Use/Filesystem (47MB)
+ */
+#define CONFIG_UBOOT1_ENV_ADDR MK_STR(0xfff80000)
+#define CONFIG_UBOOT2_ENV_ADDR MK_STR(0xfbf80000)
+#define CONFIG_FDT1_ENV_ADDR MK_STR(0xfff00000)
+#define CONFIG_FDT2_ENV_ADDR MK_STR(0xfbf00000)
+#define CONFIG_OS1_ENV_ADDR MK_STR(0xfef00000)
+#define CONFIG_OS2_ENV_ADDR MK_STR(0xfaf00000)
+
+#define CONFIG_PROG_UBOOT1 \
+ "$download_cmd $loadaddr $ubootfile; " \
+ "if test $? -eq 0; then " \
+ "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
+ "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
+ "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
+ "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
+ "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
+ "if test $? -ne 0; then " \
+ "echo PROGRAM FAILED; " \
+ "else; " \
+ "echo PROGRAM SUCCEEDED; " \
+ "fi; " \
+ "else; " \
+ "echo DOWNLOAD FAILED; " \
+ "fi;"
+
+#define CONFIG_PROG_UBOOT2 \
+ "$download_cmd $loadaddr $ubootfile; " \
+ "if test $? -eq 0; then " \
+ "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
+ "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
+ "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
+ "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
+ "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
+ "if test $? -ne 0; then " \
+ "echo PROGRAM FAILED; " \
+ "else; " \
+ "echo PROGRAM SUCCEEDED; " \
+ "fi; " \
+ "else; " \
+ "echo DOWNLOAD FAILED; " \
+ "fi;"
+
+#define CONFIG_BOOT_OS_NET \
+ "$download_cmd $osaddr $osfile; " \
+ "if test $? -eq 0; then " \
+ "if test -n $fdtaddr; then " \
+ "$download_cmd $fdtaddr $fdtfile; " \
+ "if test $? -eq 0; then " \
+ "bootm $osaddr - $fdtaddr; " \
+ "else; " \
+ "echo FDT DOWNLOAD FAILED; " \
+ "fi; " \
+ "else; " \
+ "bootm $osaddr; " \
+ "fi; " \
+ "else; " \
+ "echo OS DOWNLOAD FAILED; " \
+ "fi;"
+
+#define CONFIG_PROG_OS1 \
+ "$download_cmd $osaddr $osfile; " \
+ "if test $? -eq 0; then " \
+ "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
+ "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
+ "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
+ "if test $? -ne 0; then " \
+ "echo OS PROGRAM FAILED; " \
+ "else; " \
+ "echo OS PROGRAM SUCCEEDED; " \
+ "fi; " \
+ "else; " \
+ "echo OS DOWNLOAD FAILED; " \
+ "fi;"
+
+#define CONFIG_PROG_OS2 \
+ "$download_cmd $osaddr $osfile; " \
+ "if test $? -eq 0; then " \
+ "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
+ "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
+ "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
+ "if test $? -ne 0; then " \
+ "echo OS PROGRAM FAILED; " \
+ "else; " \
+ "echo OS PROGRAM SUCCEEDED; " \
+ "fi; " \
+ "else; " \
+ "echo OS DOWNLOAD FAILED; " \
+ "fi;"
+
+#define CONFIG_PROG_FDT1 \
+ "$download_cmd $fdtaddr $fdtfile; " \
+ "if test $? -eq 0; then " \
+ "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
+ "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
+ "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
+ "if test $? -ne 0; then " \
+ "echo FDT PROGRAM FAILED; " \
+ "else; " \
+ "echo FDT PROGRAM SUCCEEDED; " \
+ "fi; " \
+ "else; " \
+ "echo FDT DOWNLOAD FAILED; " \
+ "fi;"
+
+#define CONFIG_PROG_FDT2 \
+ "$download_cmd $fdtaddr $fdtfile; " \
+ "if test $? -eq 0; then " \
+ "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
+ "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
+ "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
+ "if test $? -ne 0; then " \
+ "echo FDT PROGRAM FAILED; " \
+ "else; " \
+ "echo FDT PROGRAM SUCCEEDED; " \
+ "fi; " \
+ "else; " \
+ "echo FDT DOWNLOAD FAILED; " \
+ "fi;"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "autoload=yes\0" \
+ "download_cmd=tftp\0" \
+ "console_args=console=ttyS0,115200\0" \
+ "root_args=root=/dev/nfs rw\0" \
+ "misc_args=ip=on\0" \
+ "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
+ "bootfile=/home/user/file\0" \
+ "osfile=/home/user/uImage-XPedite5200\0" \
+ "fdtfile=/home/user/xpedite5200.dtb\0" \
+ "ubootfile=/home/user/u-boot.bin\0" \
+ "fdtaddr=c00000\0" \
+ "osaddr=0x1000000\0" \
+ "loadaddr=0x1000000\0" \
+ "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
+ "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
+ "prog_os1="CONFIG_PROG_OS1"\0" \
+ "prog_os2="CONFIG_PROG_OS2"\0" \
+ "prog_fdt1="CONFIG_PROG_FDT1"\0" \
+ "prog_fdt2="CONFIG_PROG_FDT2"\0" \
+ "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
+ "bootcmd_flash1=run set_bootargs; " \
+ "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
+ "bootcmd_flash2=run set_bootargs; " \
+ "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
+ "bootcmd=run bootcmd_flash1\0"
+#endif /* __CONFIG_H */
--
1.6.0.2.GIT
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH v3 2/2] XPedite5200 board support
2008-12-01 19:47 ` [U-Boot] [PATCH v3 2/2] XPedite5200 board support Peter Tyser
@ 2008-12-01 20:17 ` Jon Loeliger
2008-12-01 20:31 ` Peter Tyser
0 siblings, 1 reply; 9+ messages in thread
From: Jon Loeliger @ 2008-12-01 20:17 UTC (permalink / raw)
To: u-boot
On Mon, 2008-12-01 at 13:47 -0600, Peter Tyser wrote:
> Initial support for Extreme Engineering Solutions XPedite5200 -
> a MPC8548-based PMC single board computer.
>
> Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
> ---
> +/*
> + * Use L1 as initial stack
> + */
> +#define CONFIG_SYS_INIT_RAM_LOCK 1
*sigh*
Shouldn't introduce this here either...
> +#define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
> +#define CONFIG_SYS_INIT_RAM_END 0x4000
> +
Thanks,
jdl
^ permalink raw reply [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH v3 2/2] XPedite5200 board support
2008-12-01 20:17 ` Jon Loeliger
@ 2008-12-01 20:31 ` Peter Tyser
2008-12-01 22:06 ` Jon Loeliger
0 siblings, 1 reply; 9+ messages in thread
From: Peter Tyser @ 2008-12-01 20:31 UTC (permalink / raw)
To: u-boot
On Mon, 2008-12-01 at 14:17 -0600, Jon Loeliger wrote:
> On Mon, 2008-12-01 at 13:47 -0600, Peter Tyser wrote:
> > Initial support for Extreme Engineering Solutions XPedite5200 -
> > a MPC8548-based PMC single board computer.
> >
> > Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
> > ---
>
> > +/*
> > + * Use L1 as initial stack
> > + */
> > +#define CONFIG_SYS_INIT_RAM_LOCK 1
>
> *sigh*
>
> Shouldn't introduce this here either...
> > +#define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
> > +#define CONFIG_SYS_INIT_RAM_END 0x4000
> > +
>
> Thanks,
> jdl
Which define are you referring to? A quick glance looks like these 3
defines are used legitimately. Am I missing something?
If a define should be removed, would it be possible to accept these
patches? After they are accepted I'd be happy to submit another patch
to clean up the defines for all boards. The boards I've used as
references have the similar defines which should also be cleaned up.
Thanks for the feedback,
Peter
^ permalink raw reply [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH v3 2/2] XPedite5200 board support
2008-12-01 20:31 ` Peter Tyser
@ 2008-12-01 22:06 ` Jon Loeliger
0 siblings, 0 replies; 9+ messages in thread
From: Jon Loeliger @ 2008-12-01 22:06 UTC (permalink / raw)
To: u-boot
On Mon, 2008-12-01 at 14:31 -0600, Peter Tyser wrote:
> Which define are you referring to? A quick glance looks like these 3
> defines are used legitimately. Am I missing something?
Double *sigh*...
I clearly didn't drink enough over the holidays (here).
Ignore me.
Sorry,
jdl
^ permalink raw reply [flat|nested] 9+ messages in thread
* [U-Boot] Problem in Optimizing the Boot Loader in Start.s of MPC85xx
2008-12-01 19:47 ` [U-Boot] [PATCH v3 1/2] 85xx: Add PORDEVSR_PCI1 define Peter Tyser
2008-12-01 19:47 ` [U-Boot] [PATCH v3 2/2] XPedite5200 board support Peter Tyser
@ 2008-12-03 10:35 ` Vignesh Kumar B
2008-12-03 18:30 ` Scott Wood
2008-12-04 20:58 ` [U-Boot] [PATCH v3 1/2] 85xx: Add PORDEVSR_PCI1 define Andy Fleming
2 siblings, 1 reply; 9+ messages in thread
From: Vignesh Kumar B @ 2008-12-03 10:35 UTC (permalink / raw)
To: u-boot
Hi,
I have tried modifying the Start.s of uboot as mentioned below.
When I try to link I get an error "`.bootpg' can't be allocated in
segment 1".
Can someone guide me on this. I am also attaching the start.o and the
linker script that I am using along with this mail.
When I see the dump of start.o I find that it occupies space around
0x1c0, let say max 0x200.
But why then I get this error as this is less than the 4K page mapped.
Should I change anything let me know.
Start.S
=========
#----------------------------------------------------------
# Header File for Various constants Related to 85xx
#----------------------------------------------------------
#include "init85xx.h"
.section .bootpg,"ax"
.globl _start_e500
_start_e500:
#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
# setup ccsrbar
bl setup_ccsrbar
#endif
/* create a temp mapping in AS=1 to the CCSRBAR */
lis %r6, 0x100c0000 at h
ori %r6, %r6, 0x100c0000 at l
lis %r7, 0xC0000500 at h
ori %r7, %r7, 0xC0000500 at l
lis %r8, 0xE0000008 at h
ori %r8, %r8, 0xE0000008 at l
lis %r9, 0xE0000015 at h
ori %r9, %r9, 0xE0000015 at l
mtspr MAS0,%r6
mtspr MAS1,%r7
mtspr MAS2,%r8
mtspr MAS3,%r9
isync
msync
tlbwe
tlbre
/* clear registers/arrays not reset by hardware */
/* L1 */
li %r0,2
mtspr L1CSR0,%r0 /* invalidate d-cache */
mtspr L1CSR1,%r0 /* invalidate i-cache */
mfspr %r1,DBSR
mtspr DBSR,%r1 /* Clear all valid bits */
/* Enable L1 Caches early */
lis %r2,L1CSR0_CPE at H /* enable parity */
ori %r2,%r2,L1CSR0_DCE
mtspr L1CSR0,%r2 /* enable L1 Dcache */
isync
mtspr L1CSR1,%r2 /* enable L1 Icache */
isync
sync
########################################################################
#
# Clear and set up some registers - CCSRBAR use default value
########################################################################
#
li %r0,0x0000
lis %r1,0xffff
mtspr DEC, %r0 /* prevent dec
exceptions */
mttbl %r0 /* prevent fit &
wdt exceptions */
mttbu %r0
mtspr TSR, %r1 /* clear all timer
exception status */
mtspr TCR, %r0 /* disable all - Disable
WDT */
mtspr ESR, %r0 /* clear exception
syndrome register */
mtspr MCSR,%r0 /* machine check
syndrome register */
mtxer %r0 /* clear integer
exception register */
mtspr MMUCSR0, %r1 /* invalidate all tlb's
*/
/* Enable Time Base and Select Time Base Clock */
lis %r0,HID0_EMCP at h /* Enable
machine check */
ori %r0, %r0, HID0_ENMAS7 at l /*Only For e500V2
Processors*/
ori %r0, %r0,HID0_TBEN at l /* Enable Timebase */
mtspr HID0, %r0
/* create a temp mapping in AS=1 to the boot window */
lis %r6, 0x100F0000 at h
ori %r6, %r6, 0x100F0000 at l
lis %r7, 0xC0001000 at h
ori %r7, %r7, 0xC0001700 at l
lis %r8, 0xFF00000A at h
ori %r8, %r8, 0xFF00000A at l
lis %r9, 0xFF000015 at h
ori %r9, %r9, 0xFF000015 at l
mtspr MAS0,%r6
mtspr MAS1,%r7
mtspr MAS2,%r8
mtspr MAS3,%r9
isync
msync
tlbwe
tlbre
/* create a temp mapping in AS=1 to the stack */
lis %r6, 0x100E0000 at h
ori %r6, %r6, 0x100E0000 at l
lis %r7, 0xC0001000 at h
ori %r7, %r7, 0xC0001200 at l
lis %r8, 0xE4010000 at h
ori %r8, %r8, 0xE4010000 at l
lis %r9, 0XE4010015 at h
ori %r9, %r9, 0XE4010015 at l
mtspr MAS0,%r6
mtspr MAS1,%r7
mtspr MAS2,%r8
mtspr MAS3,%r9
isync
msync
tlbwe
lis %r6,MSR_CE|MSR_ME|MSR_DE|MSR_IS|MSR_DS at h
ori %r6,%r6,MSR_CE|MSR_ME|MSR_DE|MSR_IS|MSR_DS at l
lis %r7,switch_as at h
ori %r7,%r7,switch_as at l
mtspr SRR0,%r7
mtspr SRR1,%r6
rfi
switch_as:
/* L1 DCache is used for initial RAM */
/* Allocate Initial RAM in data cache. */
lis %r3,CONFIG_SYS_INIT_RAM_ADDR at h
ori %r3,%r3,CONFIG_SYS_INIT_RAM_ADDR at l
mfspr %r2, L1CFG0
andi. %r2, %r2, 0x1ff
/* cache size * 1024 / (2 * L1 line size) */
slwi %r2, %r2, (10 - 1 - L1_CACHE_SHIFT)
mtctr %r2
li %r0,0
1:
dcbz %r0,%r3
dcbtls 0,%r0,%r3
addi %r3,%r3,CONFIG_SYS_CACHELINE_SIZE
bdnz 1b
/* Jump out the last 4K page and continue to 'normal' start */
/* Calculate absolute address in FLASH and jump there
*/
/*--------------------------------------------------------------*/
lis %r3,CONFIG_SYS_MONITOR_BASE at h
ori %r3,%r3,CONFIG_SYS_MONITOR_BASE at l
addi %r3,%r3,_start_cont - _start + _START_OFFSET
mtlr %r3
blr
#-----------------------------------------------------
# Special sequence needed to update CCSRBAR itself
#-----------------------------------------------------
..globl setup_ccsrbar
#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
setup_ccsrbar:
lis %r4, CONFIG_SYS_CCSRBAR_DEFAULT at h
ori %r4, %r4, CONFIG_SYS_CCSRBAR_DEFAULT at l
lis %r5, CONFIG_SYS_CCSRBAR at h
ori %r5, %r5, CONFIG_SYS_CCSRBAR at l
srwi %r6,%r5,12
stw %r6, 0(%r4)
isync
lis %r5, 0xffff
ori %r5,%r5,0xf000
lwz %r5, 0(%r5)
isync
lis %r3, CONFIG_SYS_CCSRBAR at h
lwz %r5, CONFIG_SYS_CCSRBAR at l(%r3)
isync
blr
#endif
.text
.globl _start
_start:
.long 0xDEADBEEF
.align 4
.globl _start_cont
_start_cont:
/* Setup the stack in initial RAM,could be L2-as-SRAM or L1
dcache*/
lis %r1,CONFIG_SYS_INIT_RAM_ADDR at h
ori %r1,%r1,CONFIG_SYS_INIT_SP_OFFSET at l
li %r0,0
stwu %r0,-4(%r1)
stwu %r0,-4(%r1) /* Terminate call chain */
stwu %r1,-8(%r1) /* Save back chain and move SP
*/
lis %r0,RESET_VECTOR at h /* Address of reset vector */
ori %r0,%r0,RESET_VECTOR at l
stwu %r1,-8(%r1) /* Save back chain and move SP
*/
stw %r0,+12(%r1) /* Save return addr (underflow
vect) */
#switch back to AS = 0
lis %r3,(MSR_CE|MSR_ME|MSR_DE)@h
ori %r3,%r3,(MSR_CE|MSR_ME|MSR_DE)@l
mtmsr %r3
isync
bl main # Jump to main()
exit:
b exit # If there is a return from main(), loop
forever
..globl mpc85xx_start_image
mpc85xx_start_image:
#----------------------------------------
# Disable D-cache
#----------------------------------------
mfspr %r4,L1CSR0
lis %r5,0
ori %r5,%r5,L1CSR0_DCE
andc %r4,%r4,%r5
mtspr L1CSR0,%r0
isync
#----------------------------------------
# Jump to image
#----------------------------------------
mtlr %r3
blr
.end # end of text section
Start.o
========
D:\MPC8568\bsp-freescale-cdsmpc8568_cpusub\cpusub\ppc\be\start.o:
file format elf32-powerpc
D:\MPC8568\bsp-freescale-cdsmpc8568_cpusub\cpusub\ppc\be\start.o
architecture: powerpc:common, flags 0x00000011:
HAS_RELOC, HAS_SYMS
start address 0x00000000
Sections:
Idx Name Size VMA LMA File off Algn
0 .text 00000070 00000000 00000000 00000040 2**4
CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
1 .data 00000000 00000000 00000000 000000b0 2**0
CONTENTS, ALLOC, LOAD, DATA
2 .bss 00000000 00000000 00000000 000000b0 2**0
ALLOC
3 .bootpg 000001c4 00000000 00000000 000000b0 2**0
CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
4 .PPC.EMB.apuinfo 00000018 00000000 00000000 00000274 2**0
CONTENTS, READONLY
SYMBOL TABLE:
00000001 l *ABS* 00000000 PPC_CPUOP_ENABLED
00000001 l *ABS* 00000000 MPC8280
00000001 l *ABS* 00000000 BUILDENV_qss
00000001 l *ABS* 00000000 VARIANT_cpusub
00000001 l *ABS* 00000000 VARIANT_be
00000000 l d .text 00000000 .text
00000000 l d .data 00000000 .data
00000000 l d .bss 00000000 .bss
00000000 l d .bootpg 00000000 .bootpg
00000148 l .bootpg 00000000 switch_as
0000004c l .text 00000000 exit
00000000 l d .PPC.EMB.apuinfo 00000000 .PPC.EMB.apuinfo
00000000 g .bootpg 00000000 _start_e500
00000188 g .bootpg 00000000 setup_ccsrbar
00000010 g .text 00000000 _start_cont
00000000 g .text 00000000 _start
00000000 *UND* 00000000 main
00000050 g .text 00000000 mpc85xx_start_image
Disassembly of section .text:
00000000 <_start>:
0: de ad be ef .long 0xdeadbeef
4: 60 00 00 00 nop
8: 60 00 00 00 nop
c: 60 00 00 00 nop
00000010 <_start_cont>:
10: 3c 20 e4 01 lis r1,-7167
14: 60 21 3f 80 ori r1,r1,16256
18: 38 00 00 00 li r0,0
1c: 94 01 ff fc stwu r0,-4(r1)
20: 94 01 ff fc stwu r0,-4(r1)
24: 94 21 ff f8 stwu r1,-8(r1)
28: 3c 00 ff ff lis r0,-1
2c: 60 00 ff fc ori r0,r0,65532
30: 94 21 ff f8 stwu r1,-8(r1)
34: 90 01 00 0c stw r0,12(r1)
38: 3c 60 00 02 lis r3,2
3c: 60 63 12 00 ori r3,r3,4608
40: 7c 60 01 24 mtmsr r3
44: 4c 00 01 2c isync
48: 48 00 00 01 bl 48 <_start_cont+0x38>
48: R_PPC_REL24 main
0000004c <exit>:
4c: 48 00 00 00 b 4c <exit>
00000050 <mpc85xx_start_image>:
50: 7c 92 fa a6 mfdbcr0 r4
54: 3c a0 00 00 lis r5,0
58: 60 a5 00 01 ori r5,r5,1
5c: 7c 84 28 78 andc r4,r4,r5
60: 7c 12 fb a6 mtdbcr0 r0
64: 4c 00 01 2c isync
68: 7c 68 03 a6 mtlr r3
6c: 4e 80 00 20 blr
Disassembly of section .bootpg:
00000000 <_start_e500>:
0: 48 00 00 01 bl 0 <_start_e500>
0: R_PPC_REL24 setup_ccsrbar
4: 3c c0 10 0c lis r6,4108
8: 60 c6 00 00 ori r6,r6,0
c: 3c e0 c0 00 lis r7,-16384
10: 60 e7 05 00 ori r7,r7,1280
14: 3d 00 e0 00 lis r8,-8192
18: 61 08 00 08 ori r8,r8,8
1c: 3d 20 e0 00 lis r9,-8192
20: 61 29 00 15 ori r9,r9,21
24: 7c d0 9b a6 mtspr 624,r6
28: 7c f1 9b a6 mtspr 625,r7
2c: 7d 12 9b a6 mtspr 626,r8
30: 7d 33 9b a6 mtspr 627,r9
34: 4c 00 01 2c isync
38: 7c 00 04 ac sync
3c: 7c 00 07 a4 tlbwehi r0,r0
40: 7c 00 07 64 tlbrehi r0,r0
44: 38 00 00 02 li r0,2
48: 7c 12 fb a6 mtdbcr0 r0
4c: 7c 13 fb a6 mtspr 1011,r0
50: 7c 30 4a a6 mfspr r1,304
54: 7c 30 4b a6 mtspr 304,r1
58: 3c 40 00 01 lis r2,1
5c: 60 42 00 01 ori r2,r2,1
60: 7c 52 fb a6 mtdbcr0 r2
64: 4c 00 01 2c isync
68: 7c 53 fb a6 mtspr 1011,r2
6c: 4c 00 01 2c isync
70: 7c 00 04 ac sync
74: 38 00 00 00 li r0,0
78: 3c 20 ff ff lis r1,-1
7c: 7c 16 03 a6 mtdec r0
80: 7c 1c 43 a6 mtsprg 4,r0
84: 7c 1d 43 a6 mtsprg 5,r0
88: 7c 30 53 a6 mtspr 336,r1
8c: 7c 14 53 a6 mtspr 340,r0
90: 7c 1e 0b a6 mtspr 62,r0
94: 7c 1c 8b a6 mtspr 572,r0
98: 7c 01 03 a6 mtxer r0
9c: 7c 34 fb a6 mtiac1 r1
a0: 3c 00 80 00 lis r0,-32768
a4: 60 00 00 80 ori r0,r0,128
a8: 60 00 40 00 ori r0,r0,16384
ac: 7c 10 fb a6 mtdbsr r0
b0: 3c c0 10 0f lis r6,4111
b4: 60 c6 00 00 ori r6,r6,0
b8: 3c e0 c0 00 lis r7,-16384
bc: 60 e7 17 00 ori r7,r7,5888
c0: 3d 00 ff 00 lis r8,-256
c4: 61 08 00 0a ori r8,r8,10
c8: 3d 20 ff 00 lis r9,-256
cc: 61 29 00 15 ori r9,r9,21
d0: 7c d0 9b a6 mtspr 624,r6
d4: 7c f1 9b a6 mtspr 625,r7
d8: 7d 12 9b a6 mtspr 626,r8
dc: 7d 33 9b a6 mtspr 627,r9
e0: 4c 00 01 2c isync
e4: 7c 00 04 ac sync
e8: 7c 00 07 a4 tlbwehi r0,r0
ec: 7c 00 07 64 tlbrehi r0,r0
f0: 3c c0 10 0e lis r6,4110
f4: 60 c6 00 00 ori r6,r6,0
f8: 3c e0 c0 00 lis r7,-16384
fc: 60 e7 12 00 ori r7,r7,4608
100: 3d 00 e4 01 lis r8,-7167
104: 61 08 00 00 ori r8,r8,0
108: 3d 20 e4 01 lis r9,-7167
10c: 61 29 00 15 ori r9,r9,21
110: 7c d0 9b a6 mtspr 624,r6
114: 7c f1 9b a6 mtspr 625,r7
118: 7d 12 9b a6 mtspr 626,r8
11c: 7d 33 9b a6 mtspr 627,r9
120: 4c 00 01 2c isync
124: 7c 00 04 ac sync
128: 7c 00 07 a4 tlbwehi r0,r0
12c: 3c c0 00 02 lis r6,2
130: 60 c6 12 30 ori r6,r6,4656
134: 3c e0 00 00 lis r7,0
136: R_PPC_ADDR16_HI .bootpg+0x148
138: 60 e7 01 48 ori r7,r7,328
13a: R_PPC_ADDR16_LO .bootpg+0x148
13c: 7c fa 03 a6 mtsrr0 r7
140: 7c db 03 a6 mtsrr1 r6
144: 4c 00 00 64 rfi
00000148 <switch_as>:
148: 3c 60 e4 01 lis r3,-7167
14c: 60 63 00 00 ori r3,r3,0
150: 7c 43 82 a6 mfspr r2,515
154: 70 42 01 ff andi. r2,r2,511
158: 54 42 20 36 rlwinm r2,r2,4,0,27
15c: 7c 49 03 a6 mtctr r2
160: 38 00 00 00 li r0,0
164: 7c 00 1f ec dcbz r0,r3
168: 7c 00 19 4c .long 0x7c00194c
16c: 38 63 00 20 addi r3,r3,32
170: 42 00 ff f4 bdnz+ 164 <switch_as+0x1c>
174: 3c 60 ff f8 lis r3,-8
178: 60 63 00 00 ori r3,r3,0
17c: 38 63 00 10 addi r3,r3,16
180: 7c 68 03 a6 mtlr r3
184: 4e 80 00 20 blr
00000188 <setup_ccsrbar>:
188: 3c 80 ff 70 lis r4,-144
18c: 60 84 00 00 ori r4,r4,0
190: 3c a0 e0 00 lis r5,-8192
194: 60 a5 00 00 ori r5,r5,0
198: 54 a6 a3 3e rlwinm r6,r5,20,12,31
19c: 90 c4 00 00 stw r6,0(r4)
1a0: 4c 00 01 2c isync
1a4: 3c a0 ff ff lis r5,-1
1a8: 60 a5 f0 00 ori r5,r5,61440
1ac: 80 a5 00 00 lwz r5,0(r5)
1b0: 4c 00 01 2c isync
1b4: 3c 60 e0 00 lis r3,-8192
1b8: 80 a3 00 00 lwz r5,0(r3)
1bc: 4c 00 01 2c isync
1c0: 4e 80 00 20 blr
Linker Code
===========
OUTPUT_ARCH(powerpc)
SECTIONS
{
.resetvec 0xFFFFFFFC:
{
*(.resetvec)
} = 0xffff
.bootpg 0xFFFFF000:
{
start.o (.bootpg)
} = 0xffff
.text 0xFFF80000:
{
start.o (.text)
board.o (.text)
main.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
__bss_start = .;
.bss (NOLOAD) :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}
Thanks & Regards,
Vignesh Kumar B
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^ permalink raw reply [flat|nested] 9+ messages in thread
* [U-Boot] Problem in Optimizing the Boot Loader in Start.s of MPC85xx
2008-12-03 10:35 ` [U-Boot] Problem in Optimizing the Boot Loader in Start.s of MPC85xx Vignesh Kumar B
@ 2008-12-03 18:30 ` Scott Wood
0 siblings, 0 replies; 9+ messages in thread
From: Scott Wood @ 2008-12-03 18:30 UTC (permalink / raw)
To: u-boot
On Wed, Dec 03, 2008 at 04:05:14PM +0530, Vignesh Kumar B wrote:
> I have tried modifying the Start.s of uboot as mentioned below.
> When I try to link I get an error "`.bootpg' can't be allocated in
> segment 1".
> Can someone guide me on this. I am also attaching the start.o and the
> linker script that I am using along with this mail.
>
> When I see the dump of start.o I find that it occupies space around
> 0x1c0, let say max 0x200.
> But why then I get this error as this is less than the 4K page mapped.
> Should I change anything let me know.
How big is the u-boot image as a whole (if you remove the bootpage stuff
so it will link)? What is the diff between a working version and your
changes?
-Scott
^ permalink raw reply [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH v3 1/2] 85xx: Add PORDEVSR_PCI1 define
2008-12-01 19:47 ` [U-Boot] [PATCH v3 1/2] 85xx: Add PORDEVSR_PCI1 define Peter Tyser
2008-12-01 19:47 ` [U-Boot] [PATCH v3 2/2] XPedite5200 board support Peter Tyser
2008-12-03 10:35 ` [U-Boot] Problem in Optimizing the Boot Loader in Start.s of MPC85xx Vignesh Kumar B
@ 2008-12-04 20:58 ` Andy Fleming
2 siblings, 0 replies; 9+ messages in thread
From: Andy Fleming @ 2008-12-04 20:58 UTC (permalink / raw)
To: u-boot
On Mon, Dec 1, 2008 at 1:47 PM, Peter Tyser <ptyser@xes-inc.com> wrote:
> Add define used to determine if PCI1 interface is in PCI or PCIX mode.
>
> Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
I thought this already had a constant defined, and I was right. It
was PORDEVSR_PCI. However, it wasn't next to the others, and your
definition is more consistent with the other code and with the manual.
As such, I converted all the other 8548 systems which checked that
bit to use your definition.
Thanks
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2008-12-04 20:58 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2008-12-01 19:47 [U-Boot] [PATCH v3 0/2] 85xx: Support for XPedite5200 Peter Tyser
2008-12-01 19:47 ` [U-Boot] [PATCH v3 1/2] 85xx: Add PORDEVSR_PCI1 define Peter Tyser
2008-12-01 19:47 ` [U-Boot] [PATCH v3 2/2] XPedite5200 board support Peter Tyser
2008-12-01 20:17 ` Jon Loeliger
2008-12-01 20:31 ` Peter Tyser
2008-12-01 22:06 ` Jon Loeliger
2008-12-03 10:35 ` [U-Boot] Problem in Optimizing the Boot Loader in Start.s of MPC85xx Vignesh Kumar B
2008-12-03 18:30 ` Scott Wood
2008-12-04 20:58 ` [U-Boot] [PATCH v3 1/2] 85xx: Add PORDEVSR_PCI1 define Andy Fleming
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