[PATCH 0/5] fpga: zynqpl: Add support for AES engine

[PATCH 0/5] fpga: zynqpl: Add support for AES engine

[Michal Simek]

Hi,

this patchset is adding support for AES support.

Thanks,
Michal


Ibai Erkiaga (1):
  fpga: zynqpl: Check if aes engine is enabled

Siva Durga Prasad Paladugu (1):
  fpga: zynqpl: Correct PL bitstream loading sequence for zynqaes

T Karthik Reddy (3):
  fpga: zynqpl: Check fpga config completion
  fpga: zynqpl: Flush dcache only for non-bitstream data
  fpga: zynqpl: Add zynq aes load & loadp commands

 board/xilinx/zynq/cmds.c | 54 +++++++++++++++++++++++++++++-----------
 drivers/fpga/zynqpl.c    | 39 +++++++++++++++++++++++------
 include/zynqpl.h         |  3 ++-
 3 files changed, 74 insertions(+), 22 deletions(-)

-- 
2.26.2

[PATCH 1/5] fpga: zynqpl: Correct PL bitstream loading sequence for zynqaes

[Michal Simek]

From: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>

Correct the PL bitstream loading sequence for zynqaes command by
clearing the loaded PL bitstream before loading the new encrypted
bitstream using the zynq aes command. This was done by setting
the PROG_B same as in case of fpgaload commands.
This patch fixes the issue of loading the encrypted PL bitstream
onto the PL in which a bitstream has already been loaded
successfully.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

 board/xilinx/zynq/cmds.c | 7 +++++--
 drivers/fpga/zynqpl.c    | 7 ++++---
 include/zynqpl.h         | 3 ++-
 3 files changed, 11 insertions(+), 6 deletions(-)

diff --git a/board/xilinx/zynq/cmds.c b/board/xilinx/zynq/cmds.c
index 27d44b760daf..ebefbf22120c 100644
--- a/board/xilinx/zynq/cmds.c
+++ b/board/xilinx/zynq/cmds.c
@@ -396,7 +396,8 @@ static int zynq_verify_image(u32 src_ptr)
 			status = zynq_decrypt_load(part_load_addr,
 						   part_img_len,
 						   part_dst_addr,
-						   part_data_len);
+						   part_data_len,
+						   BIT_NONE);
 			if (status != 0) {
 				printf("DECRYPTION_FAIL\n");
 				return -1;
@@ -435,6 +436,7 @@ static int zynq_decrypt_image(cmd_tbl_t *cmdtp, int flag, int argc,
 	char *endp;
 	u32 srcaddr, srclen, dstaddr, dstlen;
 	int status;
+	u8 imgtype = BIT_NONE;
 
 	if (argc < 5 && argc > cmdtp->maxargs)
 		return CMD_RET_USAGE;
@@ -461,7 +463,8 @@ static int zynq_decrypt_image(cmd_tbl_t *cmdtp, int flag, int argc,
 	if (dstlen % 4)
 		dstlen = roundup(dstlen, 4);
 
-	status = zynq_decrypt_load(srcaddr, srclen >> 2, dstaddr, dstlen >> 2);
+	status = zynq_decrypt_load(srcaddr, srclen >> 2, dstaddr,
+				   dstlen >> 2, imgtype);
 	if (status != 0)
 		return CMD_RET_FAILURE;
 
diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c
index 21624f715ba0..90a1f09f15e2 100644
--- a/drivers/fpga/zynqpl.c
+++ b/drivers/fpga/zynqpl.c
@@ -201,7 +201,7 @@ static int zynq_dma_xfer_init(bitstream_type bstype)
 	/* Clear loopback bit */
 	clrbits_le32(&devcfg_base->mctrl, DEVCFG_MCTRL_PCAP_LPBK);
 
-	if (bstype != BIT_PARTIAL) {
+	if (bstype != BIT_PARTIAL && bstype != BIT_NONE) {
 		zynq_slcr_devcfg_disable();
 
 		/* Setting PCFG_PROG_B signal to high */
@@ -508,7 +508,8 @@ struct xilinx_fpga_op zynq_op = {
  * Load the encrypted image from src addr and decrypt the image and
  * place it back the decrypted image into dstaddr.
  */
-int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen)
+int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen,
+		      u8 bstype)
 {
 	if (srcaddr < SZ_1M || dstaddr < SZ_1M) {
 		printf("%s: src and dst addr should be > 1M\n",
@@ -516,7 +517,7 @@ int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen)
 		return FPGA_FAIL;
 	}
 
-	if (zynq_dma_xfer_init(BIT_NONE)) {
+	if (zynq_dma_xfer_init(bstype)) {
 		printf("%s: zynq_dma_xfer_init FAIL\n", __func__);
 		return FPGA_FAIL;
 	}
diff --git a/include/zynqpl.h b/include/zynqpl.h
index 766e6918cd38..d7dc064585ea 100644
--- a/include/zynqpl.h
+++ b/include/zynqpl.h
@@ -12,7 +12,8 @@
 #include <xilinx.h>
 
 #ifdef CONFIG_CMD_ZYNQ_AES
-int zynq_decrypt_load(u32 srcaddr, u32 dstaddr, u32 srclen, u32 dstlen);
+int zynq_decrypt_load(u32 srcaddr, u32 dstaddr, u32 srclen, u32 dstlen,
+		      u8 bstype);
 #endif
 
 extern struct xilinx_fpga_op zynq_op;
-- 
2.26.2

[PATCH 2/5] fpga: zynqpl: Check fpga config completion

[Michal Simek]

From: T Karthik Reddy <t.karthik.reddy@xilinx.com>

This patch checks fpga config completion when a bitstream is loaded
into PL.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

 drivers/fpga/zynqpl.c | 19 +++++++++++++++++--
 1 file changed, 17 insertions(+), 2 deletions(-)

diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c
index 90a1f09f15e2..3f3c97e144cd 100644
--- a/drivers/fpga/zynqpl.c
+++ b/drivers/fpga/zynqpl.c
@@ -511,6 +511,8 @@ struct xilinx_fpga_op zynq_op = {
 int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen,
 		      u8 bstype)
 {
+	u32 isr_status, ts;
+
 	if (srcaddr < SZ_1M || dstaddr < SZ_1M) {
 		printf("%s: src and dst addr should be > 1M\n",
 		       __func__);
@@ -541,8 +543,21 @@ int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen,
 	if (zynq_dma_transfer(srcaddr | 1, srclen, dstaddr | 1, dstlen))
 		return FPGA_FAIL;
 
-	writel((readl(&devcfg_base->ctrl) & ~DEVCFG_CTRL_PCAP_RATE_EN_MASK),
-	       &devcfg_base->ctrl);
+	if (bstype == BIT_FULL) {
+		isr_status = readl(&devcfg_base->int_sts);
+		/* Check FPGA configuration completion */
+		ts = get_timer(0);
+		while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) {
+			if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
+				printf("%s: Timeout wait for FPGA to config\n",
+				       __func__);
+				return FPGA_FAIL;
+			}
+			isr_status = readl(&devcfg_base->int_sts);
+		}
+		printf("%s: FPGA config done\n", __func__);
+		zynq_slcr_devcfg_enable();
+	}
 
 	return FPGA_SUCCESS;
 }
-- 
2.26.2

[PATCH 3/5] fpga: zynqpl: Check if aes engine is enabled

[Michal Simek]

From: Ibai Erkiaga <ibai.erkiaga-elorza@xilinx.com>

AES engine cannot be used if has not been enabled at boot time
with an encrypted boot image.

Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@xilinx.com>
Acked-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

 drivers/fpga/zynqpl.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c
index 3f3c97e144cd..a323733ef363 100644
--- a/drivers/fpga/zynqpl.c
+++ b/drivers/fpga/zynqpl.c
@@ -19,6 +19,7 @@
 #define DEVCFG_CTRL_PCFG_PROG_B		0x40000000
 #define DEVCFG_CTRL_PCFG_AES_EFUSE_MASK	0x00001000
 #define DEVCFG_CTRL_PCAP_RATE_EN_MASK	0x02000000
+#define DEVCFG_CTRL_PCFG_AES_EN_MASK	0x00000E00
 #define DEVCFG_ISR_FATAL_ERROR_MASK	0x00740040
 #define DEVCFG_ISR_ERROR_FLAGS_MASK	0x00340840
 #define DEVCFG_ISR_RX_FIFO_OV		0x00040000
@@ -519,6 +520,13 @@ int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen,
 		return FPGA_FAIL;
 	}
 
+	/* Check AES engine is enabled */
+	if (!(readl(&devcfg_base->ctrl) &
+	      DEVCFG_CTRL_PCFG_AES_EN_MASK)) {
+		printf("%s: AES engine is not enabled\n", __func__);
+		return FPGA_FAIL;
+	}
+
 	if (zynq_dma_xfer_init(bstype)) {
 		printf("%s: zynq_dma_xfer_init FAIL\n", __func__);
 		return FPGA_FAIL;
-- 
2.26.2

[PATCH 4/5] fpga: zynqpl: Flush dcache only for non-bitstream data

[Michal Simek]

From: T Karthik Reddy <t.karthik.reddy@xilinx.com>

In case of aes decryption destination address range must be flushed
before transferring decrypted data to destination.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

 drivers/fpga/zynqpl.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c
index a323733ef363..6fc5cf57238e 100644
--- a/drivers/fpga/zynqpl.c
+++ b/drivers/fpga/zynqpl.c
@@ -545,8 +545,9 @@ int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen,
 	 * Flush destination address range only if image is not
 	 * bitstream.
 	 */
-	flush_dcache_range((u32)dstaddr, (u32)dstaddr +
-			   roundup(dstlen << 2, ARCH_DMA_MINALIGN));
+	if (bstype == BIT_NONE && dstaddr != 0xFFFFFFFF)
+		flush_dcache_range((u32)dstaddr, (u32)dstaddr +
+				   roundup(dstlen << 2, ARCH_DMA_MINALIGN));
 
 	if (zynq_dma_transfer(srcaddr | 1, srclen, dstaddr | 1, dstlen))
 		return FPGA_FAIL;
-- 
2.26.2

[PATCH 5/5] fpga: zynqpl: Add zynq aes load & loadp commands

[Michal Simek]

From: T Karthik Reddy <t.karthik.reddy@xilinx.com>

Added support for zynq aes load & loadp commands.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

 board/xilinx/zynq/cmds.c | 47 ++++++++++++++++++++++++++++++----------
 1 file changed, 35 insertions(+), 12 deletions(-)

diff --git a/board/xilinx/zynq/cmds.c b/board/xilinx/zynq/cmds.c
index ebefbf22120c..ee690a1e23a7 100644
--- a/board/xilinx/zynq/cmds.c
+++ b/board/xilinx/zynq/cmds.c
@@ -441,18 +441,37 @@ static int zynq_decrypt_image(cmd_tbl_t *cmdtp, int flag, int argc,
 	if (argc < 5 && argc > cmdtp->maxargs)
 		return CMD_RET_USAGE;
 
-	srcaddr = simple_strtoul(argv[2], &endp, 16);
-	if (*argv[2] == 0 || *endp != 0)
-		return CMD_RET_USAGE;
-	srclen = simple_strtoul(argv[3], &endp, 16);
-	if (*argv[3] == 0 || *endp != 0)
-		return CMD_RET_USAGE;
-	dstaddr = simple_strtoul(argv[4], &endp, 16);
-	if (*argv[4] == 0 || *endp != 0)
-		return CMD_RET_USAGE;
-	dstlen = simple_strtoul(argv[5], &endp, 16);
-	if (*argv[5] == 0 || *endp != 0)
-		return CMD_RET_USAGE;
+	if (argc == 5) {
+		if (!strcmp("load", argv[2]))
+			imgtype = BIT_FULL;
+		else if (!strcmp("loadp", argv[2]))
+			imgtype = BIT_PARTIAL;
+		else
+			return CMD_RET_USAGE;
+
+		srcaddr = simple_strtoul(argv[3], &endp, 16);
+		if (*argv[3] == 0 || *endp != 0)
+			return CMD_RET_USAGE;
+		srclen = simple_strtoul(argv[4], &endp, 16);
+		if (*argv[4] == 0 || *endp != 0)
+			return CMD_RET_USAGE;
+
+		dstaddr = 0xFFFFFFFF;
+		dstlen = srclen;
+	} else {
+		srcaddr = simple_strtoul(argv[2], &endp, 16);
+		if (*argv[2] == 0 || *endp != 0)
+			return CMD_RET_USAGE;
+		srclen = simple_strtoul(argv[3], &endp, 16);
+		if (*argv[3] == 0 || *endp != 0)
+			return CMD_RET_USAGE;
+		dstaddr = simple_strtoul(argv[4], &endp, 16);
+		if (*argv[4] == 0 || *endp != 0)
+			return CMD_RET_USAGE;
+		dstlen = simple_strtoul(argv[5], &endp, 16);
+		if (*argv[5] == 0 || *endp != 0)
+			return CMD_RET_USAGE;
+	}
 
 	/*
 	 * Roundup source and destination lengths to
@@ -516,6 +535,10 @@ static char zynq_help_text[] =
 	"                - Decrypts the encrypted image present in source\n"
 	"                  address and places the decrypted image at\n"
 	"                  destination address\n"
+	"aes load <srcaddr> <srclen>\n"
+	"aes loadp <srcaddr> <srclen>\n"
+	"       if operation type is load or loadp, it loads the encrypted\n"
+	"       full or partial bitstream on to PL respectively.\n"
 #endif
 	;
 #endif
-- 
2.26.2

[PATCH 0/5] fpga: zynqpl: Add support for AES engine

[Michal Simek]

?t 12. 5. 2020 v 8:48 odes?latel Michal Simek <michal.simek@xilinx.com> napsal:
>
> Hi,
>
> this patchset is adding support for AES support.
>
> Thanks,
> Michal
>
>
> Ibai Erkiaga (1):
>   fpga: zynqpl: Check if aes engine is enabled
>
> Siva Durga Prasad Paladugu (1):
>   fpga: zynqpl: Correct PL bitstream loading sequence for zynqaes
>
> T Karthik Reddy (3):
>   fpga: zynqpl: Check fpga config completion
>   fpga: zynqpl: Flush dcache only for non-bitstream data
>   fpga: zynqpl: Add zynq aes load & loadp commands
>
>  board/xilinx/zynq/cmds.c | 54 +++++++++++++++++++++++++++++-----------
>  drivers/fpga/zynqpl.c    | 39 +++++++++++++++++++++++------
>  include/zynqpl.h         |  3 ++-
>  3 files changed, 74 insertions(+), 22 deletions(-)
>
> --
> 2.26.2
>

Applied all.
M


-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs