[PATCH 0/4] arm64: zynqmp: Enable loading FPGA by SPL

[PATCH 0/4] arm64: zynqmp: Enable loading FPGA by SPL

[Michal Simek]

Hi,

this series enables loading fpga bitstream from FIT image by SPL.

Thanks,
Michal


Michal Simek (4):
  firmware: zynqmp: Swap addr_hi/low when PM_FPGA_LOAD is called
  mailbox: zynqmp: Extend timeout for getting observation bit
  arm64: zynqmp: Get rid of simple_itoa and replace it by snprintf
  arm64: zynqmp: Enable FPGA loading from SPL

 board/xilinx/zynqmp/zynqmp.c         | 7 +++++--
 configs/xilinx_zynqmp_virt_defconfig | 1 +
 drivers/firmware/firmware-zynqmp.c   | 8 ++++++++
 drivers/mailbox/zynqmp-ipi.c         | 2 +-
 4 files changed, 15 insertions(+), 3 deletions(-)

-- 
2.28.0

[PATCH 1/4] firmware: zynqmp: Swap addr_hi/low when PM_FPGA_LOAD is called

[Michal Simek]

Don't know reason but in regular flow addr_hi/low are swapped in ATF. It
means when fpga load is done from EL3 there is a need to swap it for PMUFW
to load bitstream.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

 drivers/firmware/firmware-zynqmp.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c
index 7583f24a200d..d4dc856bafa4 100644
--- a/drivers/firmware/firmware-zynqmp.c
+++ b/drivers/firmware/firmware-zynqmp.c
@@ -165,6 +165,14 @@ int __maybe_unused xilinx_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
 		 */
 		u32 regs[] = {api_id, arg0, arg1, arg2, arg3};
 
+		if (api_id == PM_FPGA_LOAD) {
+			/* Swap addr_hi/low because of incompatibility */
+			u32 temp = regs[1];
+
+			regs[1] = regs[2];
+			regs[2] = temp;
+		}
+
 		ipi_req(regs, PAYLOAD_ARG_CNT, ret_payload, PAYLOAD_ARG_CNT);
 #else
 		return -EPERM;
-- 
2.28.0

[PATCH 1/4] firmware: zynqmp: Swap addr_hi/low when PM_FPGA_LOAD is called

[Simon Glass]

On Wed, 7 Oct 2020 at 07:40, Michal Simek <michal.simek@xilinx.com> wrote:
>
> Don't know reason but in regular flow addr_hi/low are swapped in ATF. It
> means when fpga load is done from EL3 there is a need to swap it for PMUFW
> to load bitstream.
>
> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
> ---
>
>  drivers/firmware/firmware-zynqmp.c | 8 ++++++++
>  1 file changed, 8 insertions(+)

Reviewed-by: Simon Glass <sjg@chromium.org>

Is this a bug?


>
> diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c
> index 7583f24a200d..d4dc856bafa4 100644
> --- a/drivers/firmware/firmware-zynqmp.c
> +++ b/drivers/firmware/firmware-zynqmp.c
> @@ -165,6 +165,14 @@ int __maybe_unused xilinx_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
>                  */
>                 u32 regs[] = {api_id, arg0, arg1, arg2, arg3};
>
> +               if (api_id == PM_FPGA_LOAD) {
> +                       /* Swap addr_hi/low because of incompatibility */
> +                       u32 temp = regs[1];
> +
> +                       regs[1] = regs[2];
> +                       regs[2] = temp;
> +               }
> +
>                 ipi_req(regs, PAYLOAD_ARG_CNT, ret_payload, PAYLOAD_ARG_CNT);
>  #else
>                 return -EPERM;
> --
> 2.28.0
>

[PATCH 1/4] firmware: zynqmp: Swap addr_hi/low when PM_FPGA_LOAD is called

[Michal Simek]

On 12. 10. 20 5:34, Simon Glass wrote:
> On Wed, 7 Oct 2020 at 07:40, Michal Simek <michal.simek@xilinx.com> wrote:
>>
>> Don't know reason but in regular flow addr_hi/low are swapped in ATF. It
>> means when fpga load is done from EL3 there is a need to swap it for PMUFW
>> to load bitstream.
>>
>> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
>> ---
>>
>>  drivers/firmware/firmware-zynqmp.c | 8 ++++++++
>>  1 file changed, 8 insertions(+)
> 
> Reviewed-by: Simon Glass <sjg@chromium.org>
> 
> Is this a bug?

I have never enable loading fpga from SPLthat's why from u-boot point of
view it is not a bug but adding new functionality.

From ATF/PMU point of view they should never done it and I would
consider this as a bug there.

Thanks,
Michal

[PATCH 2/4] mailbox: zynqmp: Extend timeout for getting observation bit

[Michal Simek]

In case of fpga loading (which can be huge) 100ms is not enough. That's why
extend timeout 10 times to wait maximum 1s to get ACK back.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

 drivers/mailbox/zynqmp-ipi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mailbox/zynqmp-ipi.c b/drivers/mailbox/zynqmp-ipi.c
index 9483ed9cefcf..847a03648b8a 100644
--- a/drivers/mailbox/zynqmp-ipi.c
+++ b/drivers/mailbox/zynqmp-ipi.c
@@ -56,7 +56,7 @@ static int zynqmp_ipi_send(struct mbox_chan *chan, const void *data)
 
 	/* Wait until observation bit is cleared */
 	ret = wait_for_bit_le32(&ipi_int_apu->obs, IPI_BIT_MASK_PMU0, false,
-				100, false);
+				1000, false);
 
 	debug("%s, send %ld bytes\n", __func__, msg->len);
 	return ret;
-- 
2.28.0

[PATCH 3/4] arm64: zynqmp: Get rid of simple_itoa and replace it by snprintf

[Michal Simek]

simple_itoa() is implemented only for !CONFIG_USE_TINY_PRINTF. Tiny printf
is normally used by SPL that's code which uses simple_itoa() has missing
reference. That's why refactor code by using on snprintf() instead of
strncpy()/strncat() combination. This change also descrease code size by
saving 24B based on buildman.

aarch64: (for 1/1 boards) all -22.0 rodata +2.0 text -24.0
         xilinx_zynqmp_virt: all -22 rodata +2 text -24
            u-boot: add: 0/0, grow: 0/-1 bytes: 0/-24 (-24)
              function                                   old     new   delta
              board_init                                 520     496     -24

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

 board/xilinx/zynqmp/zynqmp.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index 70d6fd422eb1..362c6e3dd6fb 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -190,6 +190,7 @@ static char *zynqmp_get_silicon_idcode_name(void)
 	u32 idcode, idcode2;
 	char name[ZYNQMP_VERSION_SIZE];
 	u32 ret_payload[PAYLOAD_ARG_CNT];
+	int ret;
 
 	xilinx_pm_request(PM_GET_CHIPID, 0, 0, 0, 0, ret_payload);
 
@@ -216,8 +217,10 @@ static char *zynqmp_get_silicon_idcode_name(void)
 		return "unknown";
 
 	/* Add device prefix to the name */
-	strncpy(name, "zu", ZYNQMP_VERSION_SIZE);
-	strncat(&name[2], simple_itoa(zynqmp_devices[i].device), 2);
+	ret = snprintf(name, ZYNQMP_VERSION_SIZE, "zu%d",
+		       zynqmp_devices[i].device);
+	if (ret <= 0)
+		return "unknown";
 
 	if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_EV) {
 		/* Devices with EV variant might be EG/CG/EV family */
-- 
2.28.0

[PATCH 4/4] arm64: zynqmp: Enable FPGA loading from SPL

[Michal Simek]

fpga bitstream needs to be listed in config node in FIT image. Only tested
option is bitstream in BIN format.
Enabling this feature increase code size by almost 4k.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

 configs/xilinx_zynqmp_virt_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig
index c54ddffdd6f3..79a0091b1981 100644
--- a/configs/xilinx_zynqmp_virt_defconfig
+++ b/configs/xilinx_zynqmp_virt_defconfig
@@ -21,6 +21,7 @@ CONFIG_USE_PREBOOT=y
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_SPL_FPGA=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
-- 
2.28.0

[PATCH 0/4] arm64: zynqmp: Enable loading FPGA by SPL

[Michal Simek]

st 7. 10. 2020 v 15:40 odes?latel Michal Simek <michal.simek@xilinx.com> napsal:
>
> Hi,
>
> this series enables loading fpga bitstream from FIT image by SPL.
>
> Thanks,
> Michal
>
>
> Michal Simek (4):
>   firmware: zynqmp: Swap addr_hi/low when PM_FPGA_LOAD is called
>   mailbox: zynqmp: Extend timeout for getting observation bit
>   arm64: zynqmp: Get rid of simple_itoa and replace it by snprintf
>   arm64: zynqmp: Enable FPGA loading from SPL
>
>  board/xilinx/zynqmp/zynqmp.c         | 7 +++++--
>  configs/xilinx_zynqmp_virt_defconfig | 1 +
>  drivers/firmware/firmware-zynqmp.c   | 8 ++++++++
>  drivers/mailbox/zynqmp-ipi.c         | 2 +-
>  4 files changed, 15 insertions(+), 3 deletions(-)
>
> --
> 2.28.0
>

Applied all.
M

-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs