* [PATCH 01/10] arm64: zynqmp: Add missing silabs, skip-recall for si570 ref clk nodes
2021-05-10 14:17 [PATCH 00/10] arm64: zynqmp: Add support for KRIA boards and update phy/pinctrl descs Michal Simek
@ 2021-05-10 14:17 ` Michal Simek
2021-05-10 14:17 ` [PATCH 02/10] arm64: zynqmp: Add 'silabs, skip-recall' to DDR DIMM si570 clk node Michal Simek
` (9 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Michal Simek @ 2021-05-10 14:17 UTC (permalink / raw)
To: u-boot
All si570 which are used for ps reference clock generation should contain
silabs,skip-recall property not to cause break on ps clock.
On Versal boards this will cause hang on Versal cpu when it is booted at
the same time with SC.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
arch/arm/dts/zynqmp-e-a2197-00-revA.dts | 1 +
arch/arm/dts/zynqmp-m-a2197-01-revA.dts | 3 ++-
arch/arm/dts/zynqmp-m-a2197-02-revA.dts | 3 ++-
arch/arm/dts/zynqmp-m-a2197-03-revA.dts | 3 ++-
arch/arm/dts/zynqmp-p-a2197-00-revA.dts | 1 +
5 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
index aae3c626f562..135c83f502e8 100644
--- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
+++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
@@ -475,6 +475,7 @@
factory-fout = <33333333>;
clock-frequency = <33333333>;
clock-output-names = "ref_clk";
+ silabs,skip-recall;
};
/* and connector J212D */
};
diff --git a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts
index 19e1ebdb1d6a..213149a3dc83 100644
--- a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts
+++ b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts
@@ -343,9 +343,10 @@
compatible = "silabs,si570";
reg = <0x5d>; /* FIXME addr */
temperature-stability = <50>;
- factory-fout = <156250000>; /* FIXME every chip can be different */
+ factory-fout = <33333333>;
clock-frequency = <33333333>;
clock-output-names = "REF_CLK"; /* FIXME */
+ silabs,skip-recall;
};
/* Connection via Samtec U20D */
/* Use for storing information about X-PRC card */
diff --git a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts
index 46ec427648fa..c458110e5a89 100644
--- a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts
+++ b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts
@@ -349,9 +349,10 @@
compatible = "silabs,si570";
reg = <0x5d>; /* FIXME addr */
temperature-stability = <50>;
- factory-fout = <156250000>; /* FIXME every chip can be different */
+ factory-fout = <33333333>;
clock-frequency = <33333333>;
clock-output-names = "REF_CLK"; /* FIXME */
+ silabs,skip-recall;
};
/* Connection via Samtec U20D */
/* Use for storing information about X-PRC card */
diff --git a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts
index 6eb58e6701ad..cee7ca1fa995 100644
--- a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts
+++ b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts
@@ -339,9 +339,10 @@
compatible = "silabs,si570";
reg = <0x5d>; /* FIXME addr */
temperature-stability = <50>;
- factory-fout = <156250000>; /* FIXME every chip can be different */
+ factory-fout = <33333333>;
clock-frequency = <33333333>;
clock-output-names = "REF_CLK"; /* FIXME */
+ silabs,skip-recall;
};
/* Connection via Samtec U20D */
/* Use for storing information about X-PRC card */
diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts
index 4f7824ae4007..8e1e6b7f903b 100644
--- a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts
+++ b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts
@@ -390,6 +390,7 @@
factory-fout = <33333333>;
clock-frequency = <33333333>;
clock-output-names = "ref_clk";
+ silabs,skip-recall;
};
/* Connection via Samtec J212D */
/* Use for storing information about X-PRC card */
--
2.31.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH 02/10] arm64: zynqmp: Add 'silabs, skip-recall' to DDR DIMM si570 clk node
2021-05-10 14:17 [PATCH 00/10] arm64: zynqmp: Add support for KRIA boards and update phy/pinctrl descs Michal Simek
2021-05-10 14:17 ` [PATCH 01/10] arm64: zynqmp: Add missing silabs, skip-recall for si570 ref clk nodes Michal Simek
@ 2021-05-10 14:17 ` Michal Simek
2021-05-10 14:17 ` [PATCH 03/10] arm64: zynqmp: Add label to all GPIO lines for VCK190 SC Michal Simek
` (8 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Michal Simek @ 2021-05-10 14:17 UTC (permalink / raw)
To: u-boot
From: Saeed Nowshadi <saeed.nowshadi@xilinx.com>
The 'silabs,skip-recall' property prevents interruption in operation of
the clock while the driver is being probed. Without this property, the
DDR DIMM clk can cause a failure during Versal's boot.
Signed-off-by: Saeed Nowshadi <saeed.nowshadi@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
arch/arm/dts/zynqmp-e-a2197-00-revA.dts | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
index 135c83f502e8..e5d75e552346 100644
--- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
+++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
@@ -2,7 +2,7 @@
/*
* dts file for Xilinx Versal a2197 RevA System Controller
*
- * (C) Copyright 2019 - 2020, Xilinx, Inc.
+ * (C) Copyright 2019 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
@@ -505,6 +505,7 @@
factory-fout = <200000000>;
clock-frequency = <200000000>;
clock-output-names = "si570_ddrdimm1_clk";
+ silabs,skip-recall;
};
};
i2c at 4 { /* LPDDR4_SI570_CLK2 */
--
2.31.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH 03/10] arm64: zynqmp: Add label to all GPIO lines for VCK190 SC
2021-05-10 14:17 [PATCH 00/10] arm64: zynqmp: Add support for KRIA boards and update phy/pinctrl descs Michal Simek
2021-05-10 14:17 ` [PATCH 01/10] arm64: zynqmp: Add missing silabs, skip-recall for si570 ref clk nodes Michal Simek
2021-05-10 14:17 ` [PATCH 02/10] arm64: zynqmp: Add 'silabs, skip-recall' to DDR DIMM si570 clk node Michal Simek
@ 2021-05-10 14:17 ` Michal Simek
2021-05-10 14:17 ` [PATCH 04/10] arm64: zynqmp: Add 'i2c-mux-idle-disconnect' property Michal Simek
` (7 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Michal Simek @ 2021-05-10 14:17 UTC (permalink / raw)
To: u-boot
From: Saeed Nowshadi <saeed.nowshadi@xilinx.com>
Add label to GPIO lines so the user-level applications can find any line
without knowing its physical path on System Controller on VCK190/VMK180.
These labels are describing EMIO gpio connection which depends on PL which
we normally don't describe but that's only way to go for now. Lately this
should be done out of this source code.
Signed-off-by: Saeed Nowshadi <saeed.nowshadi@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
arch/arm/dts/zynqmp-e-a2197-00-revA.dts | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
index e5d75e552346..ffa3dbb5f71f 100644
--- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
+++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
@@ -163,20 +163,20 @@
"", "", "", "", "", /* 70 - 74 */
"", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
"SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */
- "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "", "", /* 80 - 84 */
- "", "", "", "", "", /* 85 - 89 */
- "", "", "", "", "", /* 90 - 94 */
- "", "", "", "", "", /* 95 - 99 */
+ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "", /* 80 - 84 */
+ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "", /* 85 - 89 */
+ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */
+ "SYSCTLR_GPIO5", "", "", "", "", /* 95 - 99 */
"", "", "", "", "", /* 100 - 104 */
"", "", "", "", "", /* 105 - 109 */
"", "", "", "", "", /* 110 - 114 */
"", "", "", "", "", /* 115 - 119 */
"", "", "", "", "", /* 120 - 124 */
"", "", "", "", "", /* 125 - 129 */
- "", "", "", "", "", /* 130 - 134 */
+ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "", "", "", /* 130 - 134 */
"", "", "", "", "", /* 135 - 139 */
- "", "", "", "", "", /* 140 - 144 */
- "", "", "", "", "", /* 145 - 149 */
+ "PMBUS_ALERT", "", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */
+ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */
"", "", "", "", "", /* 150 - 154 */
"", "", "", "", "", /* 155 - 159 */
"", "", "", "", "", /* 160 - 164 */
--
2.31.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH 04/10] arm64: zynqmp: Add 'i2c-mux-idle-disconnect' property
2021-05-10 14:17 [PATCH 00/10] arm64: zynqmp: Add support for KRIA boards and update phy/pinctrl descs Michal Simek
` (2 preceding siblings ...)
2021-05-10 14:17 ` [PATCH 03/10] arm64: zynqmp: Add label to all GPIO lines for VCK190 SC Michal Simek
@ 2021-05-10 14:17 ` Michal Simek
2021-05-10 14:17 ` [PATCH 05/10] arm64: zynqmp: Remove comment about clock chips Michal Simek
` (6 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Michal Simek @ 2021-05-10 14:17 UTC (permalink / raw)
To: u-boot
From: Raviteja Narayanam <raviteja.narayanam@xilinx.com>
I2C muxes that have the slave devices with same address are
falling into the below problem.
VCK190 system controller (SC) - zynqmp-e-a2197-00-revA.dts
I2C1 (0xff030000) -> Mux1 (@0x74) -> Channel 3 -> 0x50
I2C1 (0xff030000) -> Mux2 (@0x75) -> Channel 0 -> 0x50
1. SC accesses I2C1 - Mux1 (0x74) - Channel 3 and then
2. SC accesses I2C1 - Mux2 (0x75) - Channel 0.
Now it results in 2 slave devices with same address (0x50)
on the I2C bus, making the communication un-reliable.
When ' i2c-mux-idle-disconnect' is in DT, after '1', the Mux
channel output is disconnected, making none of the channels
available to the I2C1. So, there is no question of having the
same addressed slave (0x50) present on the bus when we are doing '2'.
Same pattern is seen in below two boards also.
ZCU208 - zynqmp-zcu208-revA.dts
ZCU216 - zynqmp-zcu216-revA.dts
Signed-off-by: Raviteja Narayanam <raviteja.narayanam@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
arch/arm/dts/zynqmp-e-a2197-00-revA.dts | 2 ++
arch/arm/dts/zynqmp-zcu208-revA.dts | 2 ++
arch/arm/dts/zynqmp-zcu216-revA.dts | 2 ++
3 files changed, 6 insertions(+)
diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
index ffa3dbb5f71f..8ec2e866535b 100644
--- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
+++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
@@ -457,6 +457,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x74>;
+ i2c-mux-idle-disconnect;
/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */
dc_i2c: i2c at 0 { /* DC_I2C */
#address-cells = <1>;
@@ -561,6 +562,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x75>;
+ i2c-mux-idle-disconnect;
i2c at 0 { /* SFP0_IIC */
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dts b/arch/arm/dts/zynqmp-zcu208-revA.dts
index 0e114cdacb1a..c24301090dde 100644
--- a/arch/arm/dts/zynqmp-zcu208-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu208-revA.dts
@@ -388,6 +388,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x74>;
+ i2c-mux-idle-disconnect;
/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
i2c_eeprom: i2c at 0 {
#address-cells = <1>;
@@ -504,6 +505,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x75>;
+ i2c-mux-idle-disconnect;
/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
i2c at 0 {
#address-cells = <1>;
diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts b/arch/arm/dts/zynqmp-zcu216-revA.dts
index 2302b07c4825..675baf4bed61 100644
--- a/arch/arm/dts/zynqmp-zcu216-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu216-revA.dts
@@ -399,6 +399,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x74>;
+ i2c-mux-idle-disconnect;
/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
i2c_eeprom: i2c at 0 {
#address-cells = <1>;
@@ -515,6 +516,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x75>;
+ i2c-mux-idle-disconnect;
/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
i2c at 0 {
#address-cells = <1>;
--
2.31.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH 05/10] arm64: zynqmp: Remove comment about clock chips
2021-05-10 14:17 [PATCH 00/10] arm64: zynqmp: Add support for KRIA boards and update phy/pinctrl descs Michal Simek
` (3 preceding siblings ...)
2021-05-10 14:17 ` [PATCH 04/10] arm64: zynqmp: Add 'i2c-mux-idle-disconnect' property Michal Simek
@ 2021-05-10 14:17 ` Michal Simek
2021-05-10 14:17 ` [PATCH 06/10] arm64: zynqmp: Add missing mio-bank properties to sdhci Michal Simek
` (5 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Michal Simek @ 2021-05-10 14:17 UTC (permalink / raw)
To: u-boot
These comments weren't push to mainline that's why remove them.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
arch/arm/dts/zynqmp-zcu208-revA.dts | 10 +++++-----
arch/arm/dts/zynqmp-zcu216-revA.dts | 10 +++++-----
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dts b/arch/arm/dts/zynqmp-zcu208-revA.dts
index c24301090dde..cd2f02f21de5 100644
--- a/arch/arm/dts/zynqmp-zcu208-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu208-revA.dts
@@ -424,27 +424,27 @@
si5341_2: out at 2 {
/* refclk2 for PS-GT, used for USB3 */
reg = <2>;
- always-on; /* assigned-clocks does not enable, so do it here */
+ always-on;
};
si5341_3: out at 3 {
/* refclk3 for PS-GT, used for SATA */
reg = <3>;
- always-on; /* assigned-clocks does not enable, so do it here */
+ always-on;
};
si5341_5: out at 5 {
/* refclk5 PL CLK100 */
reg = <5>;
- always-on; /* assigned-clocks does not enable, so do it here */
+ always-on;
};
si5341_6: out at 6 {
/* refclk6 PL CLK125 */
reg = <6>;
- always-on; /* assigned-clocks does not enable, so do it here */
+ always-on;
};
si5341_9: out at 9 {
/* refclk9 used for PS_REF_CLK 33.3 MHz */
reg = <9>;
- always-on; /* assigned-clocks does not enable, so do it here */
+ always-on;
};
};
};
diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts b/arch/arm/dts/zynqmp-zcu216-revA.dts
index 675baf4bed61..8aecb1529250 100644
--- a/arch/arm/dts/zynqmp-zcu216-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu216-revA.dts
@@ -435,27 +435,27 @@
si5341_2: out at 2 {
/* refclk2 for PS-GT, used for USB3 */
reg = <2>;
- always-on; /* assigned-clocks does not enable, so do it here */
+ always-on;
};
si5341_3: out at 3 {
/* refclk3 for PS-GT, used for SATA */
reg = <3>;
- always-on; /* assigned-clocks does not enable, so do it here */
+ always-on;
};
si5341_5: out at 5 {
/* refclk5 PL CLK100 */
reg = <5>;
- always-on; /* assigned-clocks does not enable, so do it here */
+ always-on;
};
si5341_6: out at 6 {
/* refclk6 PL CLK125 */
reg = <6>;
- always-on; /* assigned-clocks does not enable, so do it here */
+ always-on;
};
si5341_9: out at 9 {
/* refclk9 used for PS_REF_CLK 33.3 MHz */
reg = <9>;
- always-on; /* assigned-clocks does not enable, so do it here */
+ always-on;
};
};
};
--
2.31.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH 06/10] arm64: zynqmp: Add missing mio-bank properties to sdhci
2021-05-10 14:17 [PATCH 00/10] arm64: zynqmp: Add support for KRIA boards and update phy/pinctrl descs Michal Simek
` (4 preceding siblings ...)
2021-05-10 14:17 ` [PATCH 05/10] arm64: zynqmp: Remove comment about clock chips Michal Simek
@ 2021-05-10 14:17 ` Michal Simek
2021-05-10 14:17 ` [PATCH 07/10] arm64: zynqmp: Add zynqmp firmware specific DT nodes Michal Simek
` (4 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Michal Simek @ 2021-05-10 14:17 UTC (permalink / raw)
To: u-boot
Add missing xlnx,mio-bank property to sdhci node. Also add properties with
0 value to have it listed in case that files are copied to different
projects where default case doesn't need to be handled in the same way.
That's why explicitly list them too.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
index 8d8ebeaac3bf..0f1094804d91 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
@@ -93,6 +93,7 @@
&sdhci0 {
status = "okay";
no-1-8-v;
+ xlnx,mio-bank = <0>;
};
&ttc0 {
--
2.31.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH 07/10] arm64: zynqmp: Add zynqmp firmware specific DT nodes
2021-05-10 14:17 [PATCH 00/10] arm64: zynqmp: Add support for KRIA boards and update phy/pinctrl descs Michal Simek
` (5 preceding siblings ...)
2021-05-10 14:17 ` [PATCH 06/10] arm64: zynqmp: Add missing mio-bank properties to sdhci Michal Simek
@ 2021-05-10 14:17 ` Michal Simek
2021-05-10 14:17 ` [PATCH 08/10] arm64: zynqmp: Add pinctrl description Michal Simek
` (3 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Michal Simek @ 2021-05-10 14:17 UTC (permalink / raw)
To: u-boot
From: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Probe zynqmp firmware driver by adding zynqmp firmware, power &
ipi mailbox device tree nodes for mini emmc.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
arch/arm/dts/zynqmp-mini-emmc0.dts | 40 ++++++++++++++++++++++++++++++
arch/arm/dts/zynqmp-mini-emmc1.dts | 40 ++++++++++++++++++++++++++++++
2 files changed, 80 insertions(+)
diff --git a/arch/arm/dts/zynqmp-mini-emmc0.dts b/arch/arm/dts/zynqmp-mini-emmc0.dts
index 8467dd8e1cc7..8d9f9ca37259 100644
--- a/arch/arm/dts/zynqmp-mini-emmc0.dts
+++ b/arch/arm/dts/zynqmp-mini-emmc0.dts
@@ -41,6 +41,46 @@
clock-frequency = <200000000>;
};
+ firmware {
+ zynqmp_firmware: zynqmp-firmware {
+ compatible = "xlnx,zynqmp-firmware";
+ #power-domain-cells = <1>;
+ method = "smc";
+ u-boot,dm-pre-reloc;
+
+ zynqmp_power: zynqmp-power {
+ u-boot,dm-pre-reloc;
+ compatible = "xlnx,zynqmp-power";
+ mboxes = <&ipi_mailbox_pmu1 0>,
+ <&ipi_mailbox_pmu1 1>;
+ mbox-names = "tx", "rx";
+ };
+ };
+ };
+
+ zynqmp_ipi: zynqmp_ipi {
+ u-boot,dm-pre-reloc;
+ compatible = "xlnx,zynqmp-ipi-mailbox";
+ xlnx,ipi-id = <0>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ ipi_mailbox_pmu1: mailbox at ff990400 {
+ u-boot,dm-pre-reloc;
+ reg = <0x0 0xff9905c0 0x0 0x20>,
+ <0x0 0xff9905e0 0x0 0x20>,
+ <0x0 0xff990e80 0x0 0x20>,
+ <0x0 0xff990ea0 0x0 0x20>;
+ reg-names = "local_request_region",
+ "local_response_region",
+ "remote_request_region",
+ "remote_response_region";
+ #mbox-cells = <1>;
+ xlnx,ipi-id = <4>;
+ };
+ };
+
amba: amba {
compatible = "simple-bus";
#address-cells = <2>;
diff --git a/arch/arm/dts/zynqmp-mini-emmc1.dts b/arch/arm/dts/zynqmp-mini-emmc1.dts
index 2afcc7751b9f..5722b762d679 100644
--- a/arch/arm/dts/zynqmp-mini-emmc1.dts
+++ b/arch/arm/dts/zynqmp-mini-emmc1.dts
@@ -41,6 +41,46 @@
clock-frequency = <200000000>;
};
+ firmware {
+ zynqmp_firmware: zynqmp-firmware {
+ compatible = "xlnx,zynqmp-firmware";
+ #power-domain-cells = <1>;
+ method = "smc";
+ u-boot,dm-pre-reloc;
+
+ zynqmp_power: zynqmp-power {
+ u-boot,dm-pre-reloc;
+ compatible = "xlnx,zynqmp-power";
+ mboxes = <&ipi_mailbox_pmu1 0>,
+ <&ipi_mailbox_pmu1 1>;
+ mbox-names = "tx", "rx";
+ };
+ };
+ };
+
+ zynqmp_ipi: zynqmp_ipi {
+ u-boot,dm-pre-reloc;
+ compatible = "xlnx,zynqmp-ipi-mailbox";
+ xlnx,ipi-id = <0>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ ipi_mailbox_pmu1: mailbox at ff990400 {
+ u-boot,dm-pre-reloc;
+ reg = <0x0 0xff9905c0 0x0 0x20>,
+ <0x0 0xff9905e0 0x0 0x20>,
+ <0x0 0xff990e80 0x0 0x20>,
+ <0x0 0xff990ea0 0x0 0x20>;
+ reg-names = "local_request_region",
+ "local_response_region",
+ "remote_request_region",
+ "remote_response_region";
+ #mbox-cells = <1>;
+ xlnx,ipi-id = <4>;
+ };
+ };
+
amba: amba {
compatible = "simple-bus";
#address-cells = <2>;
--
2.31.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH 08/10] arm64: zynqmp: Add pinctrl description
2021-05-10 14:17 [PATCH 00/10] arm64: zynqmp: Add support for KRIA boards and update phy/pinctrl descs Michal Simek
` (6 preceding siblings ...)
2021-05-10 14:17 ` [PATCH 07/10] arm64: zynqmp: Add zynqmp firmware specific DT nodes Michal Simek
@ 2021-05-10 14:17 ` Michal Simek
2021-05-10 14:17 ` [PATCH 09/10] arm64: zynqmp: Add psgtr DT descriptions Michal Simek
` (2 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Michal Simek @ 2021-05-10 14:17 UTC (permalink / raw)
To: u-boot
ZynqMP pinctrl Linux driver has been merged to 5.13-rc1 kernel. Based on it
DT files can be extended by pinctrl configurations.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 229 +++++++++++++
arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 306 +++++++++++++++++
arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts | 329 +++++++++++++++++++
arch/arm/dts/zynqmp-zcu100-revC.dts | 238 +++++++++++++-
arch/arm/dts/zynqmp-zcu102-revA.dts | 288 ++++++++++++++++
arch/arm/dts/zynqmp-zcu104-revA.dts | 216 ++++++++++++
arch/arm/dts/zynqmp-zcu104-revC.dts | 216 ++++++++++++
arch/arm/dts/zynqmp-zcu106-revA.dts | 288 ++++++++++++++++
arch/arm/dts/zynqmp-zcu111-revA.dts | 225 +++++++++++++
arch/arm/dts/zynqmp-zcu208-revA.dts | 68 ++++
arch/arm/dts/zynqmp-zcu216-revA.dts | 68 ++++
include/dt-bindings/pinctrl/pinctrl-zynqmp.h | 19 ++
12 files changed, 2489 insertions(+), 1 deletion(-)
create mode 100644 include/dt-bindings/pinctrl/pinctrl-zynqmp.h
diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
index b8c5efb6a914..d5862c1cabe9 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
@@ -11,6 +11,8 @@
#include "zynqmp.dtsi"
#include "zynqmp-clk-ccf.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
/ {
model = "ZynqMP zc1751-xm015-dc1 RevA";
@@ -75,6 +77,8 @@
status = "okay";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gem3_default>;
phy0: ethernet-phy at 0 {
reg = <0>;
};
@@ -82,6 +86,8 @@
&gpio {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_default>;
};
&gpu {
@@ -91,6 +97,11 @@
&i2c1 {
status = "okay";
clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;
eeprom: eeprom at 55 {
compatible = "atmel,24c64"; /* 24AA64 */
@@ -98,6 +109,216 @@
};
};
+&pinctrl0 {
+ status = "okay";
+ pinctrl_i2c1_default: i2c1-default {
+ mux {
+ groups = "i2c1_9_grp";
+ function = "i2c1";
+ };
+
+ conf {
+ groups = "i2c1_9_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpio {
+ mux {
+ groups = "gpio0_36_grp", "gpio0_37_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_36_grp", "gpio0_37_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_uart0_default: uart0-default {
+ mux {
+ groups = "uart0_8_grp";
+ function = "uart0";
+ };
+
+ conf {
+ groups = "uart0_8_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO34";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO35";
+ bias-disable;
+ };
+ };
+
+ pinctrl_usb0_default: usb0-default {
+ mux {
+ groups = "usb0_0_grp";
+ function = "usb0";
+ };
+
+ conf {
+ groups = "usb0_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO52", "MIO53", "MIO55";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
+ "MIO60", "MIO61", "MIO62", "MIO63";
+ bias-disable;
+ };
+ };
+
+ pinctrl_gem3_default: gem3-default {
+ mux {
+ function = "ethernet3";
+ groups = "ethernet3_0_grp";
+ };
+
+ conf {
+ groups = "ethernet3_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
+ "MIO75";
+ bias-high-impedance;
+ low-power-disable;
+ };
+
+ conf-tx {
+ pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
+ "MIO69";
+ bias-disable;
+ low-power-enable;
+ };
+
+ mux-mdio {
+ function = "mdio3";
+ groups = "mdio3_0_grp";
+ };
+
+ conf-mdio {
+ groups = "mdio3_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+ };
+
+ pinctrl_sdhci0_default: sdhci0-default {
+ mux {
+ groups = "sdio0_0_grp";
+ function = "sdio0";
+ };
+
+ conf {
+ groups = "sdio0_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+
+ mux-cd {
+ groups = "sdio0_cd_0_grp";
+ function = "sdio0_cd";
+ };
+
+ conf-cd {
+ groups = "sdio0_cd_0_grp";
+ bias-high-impedance;
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux-wp {
+ groups = "sdio0_wp_0_grp";
+ function = "sdio0_wp";
+ };
+
+ conf-wp {
+ groups = "sdio0_wp_0_grp";
+ bias-high-impedance;
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_sdhci1_default: sdhci1-default {
+ mux {
+ groups = "sdio1_0_grp";
+ function = "sdio1";
+ };
+
+ conf {
+ groups = "sdio1_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+
+ mux-cd {
+ groups = "sdio1_cd_0_grp";
+ function = "sdio1_cd";
+ };
+
+ conf-cd {
+ groups = "sdio1_cd_0_grp";
+ bias-high-impedance;
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux-wp {
+ groups = "sdio1_wp_0_grp";
+ function = "sdio1_wp";
+ };
+
+ conf-wp {
+ groups = "sdio1_wp_0_grp";
+ bias-high-impedance;
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_gpio_default: gpio-default {
+ mux {
+ function = "gpio0";
+ groups = "gpio0_38_grp";
+ };
+
+ conf {
+ groups = "gpio0_38_grp";
+ bias-disable;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+};
+
&qspi {
status = "okay";
flash at 0 {
@@ -147,6 +368,8 @@
/* eMMC */
&sdhci0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdhci0_default>;
bus-width = <8>;
xlnx,mio-bank = <0>;
};
@@ -158,16 +381,22 @@
* This property should be removed for supporting UHS mode
*/
no-1-8-v;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdhci1_default>;
xlnx,mio-bank = <1>;
};
&uart0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0_default>;
};
/* ULPI SMSC USB3320 */
&usb0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0_default>;
};
&dwc3_0 {
diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
index 3204456e6451..d6e924803354 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
@@ -11,6 +11,8 @@
#include "zynqmp.dtsi"
#include "zynqmp-clk-ccf.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
/ {
model = "ZynqMP zc1751-xm016-dc2 RevA";
@@ -43,10 +45,14 @@
&can0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can0_default>;
};
&can1 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can1_default>;
};
&fpd_dma_chan1 {
@@ -85,6 +91,8 @@
status = "okay";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gem2_default>;
phy0: ethernet-phy at 5 {
reg = <5>;
ti,rx-internal-delay = <0x8>;
@@ -101,6 +109,11 @@
&i2c0 {
status = "okay";
clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c0_default>;
+ pinctrl-1 = <&pinctrl_i2c0_gpio>;
+ scl-gpios = <&gpio 6 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
tca6416_u26: gpio at 20 {
compatible = "ti,tca6416";
@@ -118,6 +131,8 @@
&nand0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_nand0_default>;
arasan,has-mdma;
nand at 0 {
@@ -190,6 +205,285 @@
};
};
+&pinctrl0 {
+ status = "okay";
+ pinctrl_can0_default: can0-default {
+ mux {
+ function = "can0";
+ groups = "can0_9_grp";
+ };
+
+ conf {
+ groups = "can0_9_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO38";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO39";
+ bias-disable;
+ };
+ };
+
+ pinctrl_can1_default: can1-default {
+ mux {
+ function = "can1";
+ groups = "can1_8_grp";
+ };
+
+ conf {
+ groups = "can1_8_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO33";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO32";
+ bias-disable;
+ };
+ };
+
+ pinctrl_i2c0_default: i2c0-default {
+ mux {
+ groups = "i2c0_1_grp";
+ function = "i2c0";
+ };
+
+ conf {
+ groups = "i2c0_1_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c0_gpio: i2c0-gpio {
+ mux {
+ groups = "gpio0_6_grp", "gpio0_7_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_6_grp", "gpio0_7_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_uart0_default: uart0-default {
+ mux {
+ groups = "uart0_10_grp";
+ function = "uart0";
+ };
+
+ conf {
+ groups = "uart0_10_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO42";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO43";
+ bias-disable;
+ };
+ };
+
+ pinctrl_uart1_default: uart1-default {
+ mux {
+ groups = "uart1_10_grp";
+ function = "uart1";
+ };
+
+ conf {
+ groups = "uart1_10_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO41";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO40";
+ bias-disable;
+ };
+ };
+
+ pinctrl_usb1_default: usb1-default {
+ mux {
+ groups = "usb1_0_grp";
+ function = "usb1";
+ };
+
+ conf {
+ groups = "usb1_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO64", "MIO65", "MIO67";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71",
+ "MIO72", "MIO73", "MIO74", "MIO75";
+ bias-disable;
+ };
+ };
+
+ pinctrl_gem2_default: gem2-default {
+ mux {
+ function = "ethernet2";
+ groups = "ethernet2_0_grp";
+ };
+
+ conf {
+ groups = "ethernet2_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO58", "MIO59", "MIO60", "MIO61", "MIO62",
+ "MIO63";
+ bias-high-impedance;
+ low-power-disable;
+ };
+
+ conf-tx {
+ pins = "MIO52", "MIO53", "MIO54", "MIO55", "MIO56",
+ "MIO57";
+ bias-disable;
+ low-power-enable;
+ };
+
+ mux-mdio {
+ function = "mdio2";
+ groups = "mdio2_0_grp";
+ };
+
+ conf-mdio {
+ groups = "mdio2_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+ };
+
+ pinctrl_nand0_default: nand0-default {
+ mux {
+ groups = "nand0_0_grp";
+ function = "nand0";
+ };
+
+ conf {
+ groups = "nand0_0_grp";
+ bias-pull-up;
+ };
+
+ mux-ce {
+ groups = "nand0_ce_0_grp";
+ function = "nand0_ce";
+ };
+
+ conf-ce {
+ groups = "nand0_ce_0_grp";
+ bias-pull-up;
+ };
+
+ mux-rb {
+ groups = "nand0_rb_0_grp";
+ function = "nand0_rb";
+ };
+
+ conf-rb {
+ groups = "nand0_rb_0_grp";
+ bias-pull-up;
+ };
+
+ mux-dqs {
+ groups = "nand0_dqs_0_grp";
+ function = "nand0_dqs";
+ };
+
+ conf-dqs {
+ groups = "nand0_dqs_0_grp";
+ bias-pull-up;
+ };
+ };
+
+ pinctrl_spi0_default: spi0-default {
+ mux {
+ groups = "spi0_0_grp";
+ function = "spi0";
+ };
+
+ conf {
+ groups = "spi0_0_grp";
+ bias-disable;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux-cs {
+ groups = "spi0_ss_0_grp", "spi0_ss_1_grp",
+ "spi0_ss_2_grp";
+ function = "spi0_ss";
+ };
+
+ conf-cs {
+ groups = "spi0_ss_0_grp", "spi0_ss_1_grp",
+ "spi0_ss_2_grp";
+ bias-disable;
+ };
+ };
+
+ pinctrl_spi1_default: spi1-default {
+ mux {
+ groups = "spi1_3_grp";
+ function = "spi1";
+ };
+
+ conf {
+ groups = "spi1_3_grp";
+ bias-disable;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux-cs {
+ groups = "spi1_ss_9_grp", "spi1_ss_10_grp",
+ "spi1_ss_11_grp";
+ function = "spi1_ss";
+ };
+
+ conf-cs {
+ groups = "spi1_ss_9_grp", "spi1_ss_10_grp",
+ "spi1_ss_11_grp";
+ bias-disable;
+ };
+ };
+};
+
&rtc {
status = "okay";
};
@@ -197,6 +491,9 @@
&spi0 {
status = "okay";
num-cs = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi0_default>;
+
spi0_flash0: flash at 0 {
#address-cells = <1>;
#size-cells = <1>;
@@ -214,6 +511,9 @@
&spi1 {
status = "okay";
num-cs = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1_default>;
+
spi1_flash0: flash at 0 {
#address-cells = <1>;
#size-cells = <1>;
@@ -231,6 +531,8 @@
/* ULPI SMSC USB3320 */
&usb1 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb1_default>;
};
&dwc3_1 {
@@ -240,8 +542,12 @@
&uart0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0_default>;
};
&uart1 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_default>;
};
diff --git a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
index 0f1094804d91..46b27a000949 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
@@ -12,6 +12,9 @@
#include "zynqmp.dtsi"
#include "zynqmp-clk-ccf.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
+
/ {
model = "ZynqMP zc1751-xm019-dc5 RevA";
compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
@@ -73,6 +76,8 @@
status = "okay";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gem1_default>;
phy0: ethernet-phy at 0 {
reg = <0>;
};
@@ -84,42 +89,366 @@
&i2c0 {
status = "okay";
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c0_default>;
+ pinctrl-1 = <&pinctrl_i2c0_gpio>;
+ scl-gpios = <&gpio 74 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio 75 GPIO_ACTIVE_HIGH>;
};
&i2c1 {
status = "okay";
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio 76 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio 77 GPIO_ACTIVE_HIGH>;
+
+};
+
+&pinctrl0 {
+ status = "okay";
+ pinctrl_i2c0_default: i2c0-default {
+ mux {
+ groups = "i2c0_18_grp";
+ function = "i2c0";
+ };
+
+ conf {
+ groups = "i2c0_18_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c0_gpio: i2c0-gpio {
+ mux {
+ groups = "gpio0_74_grp", "gpio0_75_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_74_grp", "gpio0_75_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c1_default: i2c1-default {
+ mux {
+ groups = "i2c1_19_grp";
+ function = "i2c1";
+ };
+
+ conf {
+ groups = "i2c1_19_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpio {
+ mux {
+ groups = "gpio0_76_grp", "gpio0_77_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_76_grp", "gpio0_77_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_uart0_default: uart0-default {
+ mux {
+ groups = "uart0_17_grp";
+ function = "uart0";
+ };
+
+ conf {
+ groups = "uart0_17_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO70";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO71";
+ bias-disable;
+ };
+ };
+
+ pinctrl_uart1_default: uart1-default {
+ mux {
+ groups = "uart1_18_grp";
+ function = "uart1";
+ };
+
+ conf {
+ groups = "uart1_18_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO73";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO72";
+ bias-disable;
+ };
+ };
+
+ pinctrl_gem1_default: gem1-default {
+ mux {
+ function = "ethernet1";
+ groups = "ethernet1_0_grp";
+ };
+
+ conf {
+ groups = "ethernet1_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO44", "MIO45", "MIO46", "MIO47", "MIO48",
+ "MIO49";
+ bias-high-impedance;
+ low-power-disable;
+ };
+
+ conf-tx {
+ pins = "MIO38", "MIO39", "MIO40", "MIO41", "MIO42",
+ "MIO43";
+ bias-disable;
+ low-power-enable;
+ };
+
+ mux-mdio {
+ function = "mdio1";
+ groups = "mdio1_0_grp";
+ };
+
+ conf-mdio {
+ groups = "mdio1_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+ };
+
+ pinctrl_sdhci0_default: sdhci0-default {
+ mux {
+ groups = "sdio0_0_grp";
+ function = "sdio0";
+ };
+
+ conf {
+ groups = "sdio0_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+
+ mux-cd {
+ groups = "sdio0_cd_0_grp";
+ function = "sdio0_cd";
+ };
+
+ conf-cd {
+ groups = "sdio0_cd_0_grp";
+ bias-high-impedance;
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux-wp {
+ groups = "sdio0_wp_0_grp";
+ function = "sdio0_wp";
+ };
+
+ conf-wp {
+ groups = "sdio0_wp_0_grp";
+ bias-high-impedance;
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_watchdog0_default: watchdog0-default {
+ mux-clk {
+ groups = "swdt0_clk_1_grp";
+ function = "swdt0_clk";
+ };
+
+ conf-clk {
+ groups = "swdt0_clk_1_grp";
+ bias-pull-up;
+ };
+
+ mux-rst {
+ groups = "swdt0_rst_1_grp";
+ function = "swdt0_rst";
+ };
+
+ conf-rst {
+ groups = "swdt0_rst_1_grp";
+ bias-disable;
+ slew-rate = <SLEW_RATE_SLOW>;
+ };
+ };
+
+ pinctrl_ttc0_default: ttc0-default {
+ mux-clk {
+ groups = "ttc0_clk_0_grp";
+ function = "ttc0_clk";
+ };
+
+ conf-clk {
+ groups = "ttc0_clk_0_grp";
+ bias-pull-up;
+ };
+
+ mux-wav {
+ groups = "ttc0_wav_0_grp";
+ function = "ttc0_wav";
+ };
+
+ conf-wav {
+ groups = "ttc0_wav_0_grp";
+ bias-disable;
+ slew-rate = <SLEW_RATE_SLOW>;
+ };
+ };
+
+ pinctrl_ttc1_default: ttc1-default {
+ mux-clk {
+ groups = "ttc1_clk_0_grp";
+ function = "ttc1_clk";
+ };
+
+ conf-clk {
+ groups = "ttc1_clk_0_grp";
+ bias-pull-up;
+ };
+
+ mux-wav {
+ groups = "ttc1_wav_0_grp";
+ function = "ttc1_wav";
+ };
+
+ conf-wav {
+ groups = "ttc1_wav_0_grp";
+ bias-disable;
+ slew-rate = <SLEW_RATE_SLOW>;
+ };
+ };
+
+ pinctrl_ttc2_default: ttc2-default {
+ mux-clk {
+ groups = "ttc2_clk_0_grp";
+ function = "ttc2_clk";
+ };
+
+ conf-clk {
+ groups = "ttc2_clk_0_grp";
+ bias-pull-up;
+ };
+
+ mux-wav {
+ groups = "ttc2_wav_0_grp";
+ function = "ttc2_wav";
+ };
+
+ conf-wav {
+ groups = "ttc2_wav_0_grp";
+ bias-disable;
+ slew-rate = <SLEW_RATE_SLOW>;
+ };
+ };
+
+ pinctrl_ttc3_default: ttc3-default {
+ mux-clk {
+ groups = "ttc3_clk_0_grp";
+ function = "ttc3_clk";
+ };
+
+ conf-clk {
+ groups = "ttc3_clk_0_grp";
+ bias-pull-up;
+ };
+
+ mux-wav {
+ groups = "ttc3_wav_0_grp";
+ function = "ttc3_wav";
+ };
+
+ conf-wav {
+ groups = "ttc3_wav_0_grp";
+ bias-disable;
+ slew-rate = <SLEW_RATE_SLOW>;
+ };
+ };
};
&sdhci0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdhci0_default>;
no-1-8-v;
xlnx,mio-bank = <0>;
};
&ttc0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ttc0_default>;
};
&ttc1 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ttc1_default>;
};
&ttc2 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ttc2_default>;
};
&ttc3 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ttc3_default>;
};
&uart0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0_default>;
};
&uart1 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_default>;
};
&watchdog0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_watchdog0_default>;
};
diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts b/arch/arm/dts/zynqmp-zcu100-revC.dts
index bbcc69c79673..9603043db109 100644
--- a/arch/arm/dts/zynqmp-zcu100-revC.dts
+++ b/arch/arm/dts/zynqmp-zcu100-revC.dts
@@ -15,6 +15,7 @@
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
#include <dt-bindings/phy/phy.h>
/ {
@@ -185,6 +186,11 @@
&i2c1 {
status = "okay";
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
clock-frequency = <100000>;
i2c-mux at 75 { /* u11 */
compatible = "nxp,pca9548";
@@ -262,6 +268,221 @@
};
};
+&pinctrl0 {
+ status = "okay";
+ pinctrl_i2c1_default: i2c1-default {
+ mux {
+ groups = "i2c1_1_grp";
+ function = "i2c1";
+ };
+
+ conf {
+ groups = "i2c1_1_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpio {
+ mux {
+ groups = "gpio0_4_grp", "gpio0_5_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_4_grp", "gpio0_5_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_sdhci0_default: sdhci0-default {
+ mux {
+ groups = "sdio0_3_grp";
+ function = "sdio0";
+ };
+
+ conf {
+ groups = "sdio0_3_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+
+ mux-cd {
+ groups = "sdio0_cd_0_grp";
+ function = "sdio0_cd";
+ };
+
+ conf-cd {
+ groups = "sdio0_cd_0_grp";
+ bias-high-impedance;
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_sdhci1_default: sdhci1-default {
+ mux {
+ groups = "sdio1_2_grp";
+ function = "sdio1";
+ };
+
+ conf {
+ groups = "sdio1_2_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+ };
+
+ pinctrl_spi0_default: spi0-default {
+ mux {
+ groups = "spi0_3_grp";
+ function = "spi0";
+ };
+
+ conf {
+ groups = "spi0_3_grp";
+ bias-disable;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux-cs {
+ groups = "spi0_ss_9_grp";
+ function = "spi0_ss";
+ };
+
+ conf-cs {
+ groups = "spi0_ss_9_grp";
+ bias-disable;
+ };
+
+ };
+
+ pinctrl_spi1_default: spi1-default {
+ mux {
+ groups = "spi1_0_grp";
+ function = "spi1";
+ };
+
+ conf {
+ groups = "spi1_0_grp";
+ bias-disable;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux-cs {
+ groups = "spi1_ss_0_grp";
+ function = "spi1_ss";
+ };
+
+ conf-cs {
+ groups = "spi1_ss_0_grp";
+ bias-disable;
+ };
+
+ };
+
+ pinctrl_uart0_default: uart0-default {
+ mux {
+ groups = "uart0_0_grp";
+ function = "uart0";
+ };
+
+ conf {
+ groups = "uart0_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO3";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO2";
+ bias-disable;
+ };
+ };
+
+ pinctrl_uart1_default: uart1-default {
+ mux {
+ groups = "uart1_0_grp";
+ function = "uart1";
+ };
+
+ conf {
+ groups = "uart1_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO1";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO0";
+ bias-disable;
+ };
+ };
+
+ pinctrl_usb0_default: usb0-default {
+ mux {
+ groups = "usb0_0_grp";
+ function = "usb0";
+ };
+
+ conf {
+ groups = "usb0_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO52", "MIO53", "MIO55";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
+ "MIO60", "MIO61", "MIO62", "MIO63";
+ bias-disable;
+ };
+ };
+
+ pinctrl_usb1_default: usb1-default {
+ mux {
+ groups = "usb1_0_grp";
+ function = "usb1";
+ };
+
+ conf {
+ groups = "usb1_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO64", "MIO65", "MIO67";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71",
+ "MIO72", "MIO73", "MIO74", "MIO75";
+ bias-disable;
+ };
+ };
+};
+
&psgtr {
status = "okay";
/* usb3, dps */
@@ -278,12 +499,16 @@
status = "okay";
no-1-8-v;
disable-wp;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdhci0_default>;
xlnx,mio-bank = <0>;
};
&sdhci1 {
status = "okay";
bus-width = <0x4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdhci1_default>;
xlnx,mio-bank = <0>;
non-removable;
disable-wp;
@@ -304,16 +529,22 @@
status = "okay";
label = "LS-SPI0";
num-cs = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi0_default>;
};
&spi1 { /* High Speed connector */
status = "okay";
label = "HS-SPI1";
num-cs = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1_default>;
};
&uart0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0_default>;
bluetooth {
compatible = "ti,wl1831-st";
enable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;
@@ -322,12 +553,15 @@
&uart1 {
status = "okay";
-
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_default>;
};
/* ULPI SMSC USB3320 */
&usb0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0_default>;
};
&dwc3_0 {
@@ -339,6 +573,8 @@
/* ULPI SMSC USB3320 */
&usb1 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb1_default>;
};
&dwc3_1 {
diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts
index 9323b8d64d56..27c3dcc87f96 100644
--- a/arch/arm/dts/zynqmp-zcu102-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revA.dts
@@ -13,6 +13,7 @@
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
#include <dt-bindings/phy/phy.h>
/ {
@@ -154,6 +155,8 @@
&can1 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can1_default>;
};
&dcc {
@@ -196,6 +199,8 @@
status = "okay";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gem3_default>;
phy0: ethernet-phy at 21 {
reg = <21>;
ti,rx-internal-delay = <0x8>;
@@ -208,6 +213,8 @@
&gpio {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_default>;
};
&gpu {
@@ -217,6 +224,11 @@
&i2c0 {
status = "okay";
clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c0_default>;
+ pinctrl-1 = <&pinctrl_i2c0_gpio>;
+ scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
tca6416_u97: gpio at 20 {
compatible = "ti,tca6416";
@@ -476,6 +488,11 @@
&i2c1 {
status = "okay";
clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
/* PL i2c via PCA9306 - u45 */
i2c-mux at 74 { /* u34 */
@@ -658,6 +675,269 @@
};
};
+&pinctrl0 {
+ status = "okay";
+ pinctrl_i2c0_default: i2c0-default {
+ mux {
+ groups = "i2c0_3_grp";
+ function = "i2c0";
+ };
+
+ conf {
+ groups = "i2c0_3_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c0_gpio: i2c0-gpio {
+ mux {
+ groups = "gpio0_14_grp", "gpio0_15_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_14_grp", "gpio0_15_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c1_default: i2c1-default {
+ mux {
+ groups = "i2c1_4_grp";
+ function = "i2c1";
+ };
+
+ conf {
+ groups = "i2c1_4_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpio {
+ mux {
+ groups = "gpio0_16_grp", "gpio0_17_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_16_grp", "gpio0_17_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_uart0_default: uart0-default {
+ mux {
+ groups = "uart0_4_grp";
+ function = "uart0";
+ };
+
+ conf {
+ groups = "uart0_4_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO18";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO19";
+ bias-disable;
+ };
+ };
+
+ pinctrl_uart1_default: uart1-default {
+ mux {
+ groups = "uart1_5_grp";
+ function = "uart1";
+ };
+
+ conf {
+ groups = "uart1_5_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO21";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO20";
+ bias-disable;
+ };
+ };
+
+ pinctrl_usb0_default: usb0-default {
+ mux {
+ groups = "usb0_0_grp";
+ function = "usb0";
+ };
+
+ conf {
+ groups = "usb0_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO52", "MIO53", "MIO55";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
+ "MIO60", "MIO61", "MIO62", "MIO63";
+ bias-disable;
+ };
+ };
+
+ pinctrl_gem3_default: gem3-default {
+ mux {
+ function = "ethernet3";
+ groups = "ethernet3_0_grp";
+ };
+
+ conf {
+ groups = "ethernet3_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
+ "MIO75";
+ bias-high-impedance;
+ low-power-disable;
+ };
+
+ conf-tx {
+ pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
+ "MIO69";
+ bias-disable;
+ low-power-enable;
+ };
+
+ mux-mdio {
+ function = "mdio3";
+ groups = "mdio3_0_grp";
+ };
+
+ conf-mdio {
+ groups = "mdio3_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+ };
+
+ pinctrl_can1_default: can1-default {
+ mux {
+ function = "can1";
+ groups = "can1_6_grp";
+ };
+
+ conf {
+ groups = "can1_6_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO25";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO24";
+ bias-disable;
+ };
+ };
+
+ pinctrl_sdhci1_default: sdhci1-default {
+ mux {
+ groups = "sdio1_0_grp";
+ function = "sdio1";
+ };
+
+ conf {
+ groups = "sdio1_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+
+ mux-cd {
+ groups = "sdio1_cd_0_grp";
+ function = "sdio1_cd";
+ };
+
+ conf-cd {
+ groups = "sdio1_cd_0_grp";
+ bias-high-impedance;
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux-wp {
+ groups = "sdio1_wp_0_grp";
+ function = "sdio1_wp";
+ };
+
+ conf-wp {
+ groups = "sdio1_wp_0_grp";
+ bias-high-impedance;
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_gpio_default: gpio-default {
+ mux-sw {
+ function = "gpio0";
+ groups = "gpio0_22_grp", "gpio0_23_grp";
+ };
+
+ conf-sw {
+ groups = "gpio0_22_grp", "gpio0_23_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux-msp {
+ function = "gpio0";
+ groups = "gpio0_13_grp", "gpio0_38_grp";
+ };
+
+ conf-msp {
+ groups = "gpio0_13_grp", "gpio0_38_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-pull-up {
+ pins = "MIO22", "MIO23";
+ bias-pull-up;
+ };
+
+ conf-pull-none {
+ pins = "MIO13", "MIO38";
+ bias-disable;
+ };
+ };
+};
+
&pcie {
status = "okay";
};
@@ -726,20 +1006,28 @@
* removed for supporting UHS mode
*/
no-1-8-v;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdhci1_default>;
xlnx,mio-bank = <1>;
};
&uart0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0_default>;
};
&uart1 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_default>;
};
/* ULPI SMSC USB3320 */
&usb0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0_default>;
};
&dwc3_0 {
diff --git a/arch/arm/dts/zynqmp-zcu104-revA.dts b/arch/arm/dts/zynqmp-zcu104-revA.dts
index a95bd4922a62..bad73d9093c0 100644
--- a/arch/arm/dts/zynqmp-zcu104-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu104-revA.dts
@@ -12,6 +12,7 @@
#include "zynqmp.dtsi"
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
#include <dt-bindings/phy/phy.h>
/ {
@@ -62,6 +63,8 @@
&can1 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can1_default>;
};
&dcc {
@@ -104,6 +107,8 @@
status = "okay";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gem3_default>;
phy0: ethernet-phy at c {
reg = <0xc>;
ti,rx-internal-delay = <0x8>;
@@ -124,6 +129,11 @@
&i2c1 {
status = "okay";
clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
/* Another connection to this bus via PL i2c via PCA9306 - u45 */
i2c-mux at 74 { /* u34 */
@@ -215,6 +225,204 @@
};
};
+&pinctrl0 {
+ status = "okay";
+
+ pinctrl_can1_default: can1-default {
+ mux {
+ function = "can1";
+ groups = "can1_6_grp";
+ };
+
+ conf {
+ groups = "can1_6_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ drive-strength = <12>;
+ };
+
+ conf-rx {
+ pins = "MIO25";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO24";
+ bias-disable;
+ };
+ };
+
+ pinctrl_i2c1_default: i2c1-default {
+ mux {
+ groups = "i2c1_4_grp";
+ function = "i2c1";
+ };
+
+ conf {
+ groups = "i2c1_4_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ drive-strength = <12>;
+ };
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpio {
+ mux {
+ groups = "gpio0_16_grp", "gpio0_17_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_16_grp", "gpio0_17_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ drive-strength = <12>;
+ };
+ };
+
+ pinctrl_gem3_default: gem3-default {
+ mux {
+ function = "ethernet3";
+ groups = "ethernet3_0_grp";
+ };
+
+ conf {
+ groups = "ethernet3_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ drive-strength = <12>;
+ };
+
+ conf-rx {
+ pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
+ "MIO75";
+ bias-high-impedance;
+ low-power-disable;
+ };
+
+ conf-tx {
+ pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
+ "MIO69";
+ bias-disable;
+ low-power-enable;
+ };
+
+ mux-mdio {
+ function = "mdio3";
+ groups = "mdio3_0_grp";
+ };
+
+ conf-mdio {
+ groups = "mdio3_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+ };
+
+ pinctrl_sdhci1_default: sdhci1-default {
+ mux {
+ groups = "sdio1_0_grp";
+ function = "sdio1";
+ };
+
+ conf {
+ groups = "sdio1_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ drive-strength = <12>;
+ };
+
+ mux-cd {
+ groups = "sdio1_cd_0_grp";
+ function = "sdio1_cd";
+ };
+
+ conf-cd {
+ groups = "sdio1_cd_0_grp";
+ bias-high-impedance;
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_uart0_default: uart0-default {
+ mux {
+ groups = "uart0_4_grp";
+ function = "uart0";
+ };
+
+ conf {
+ groups = "uart0_4_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ drive-strength = <12>;
+ };
+
+ conf-rx {
+ pins = "MIO18";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO19";
+ bias-disable;
+ };
+ };
+
+ pinctrl_uart1_default: uart1-default {
+ mux {
+ groups = "uart1_5_grp";
+ function = "uart1";
+ };
+
+ conf {
+ groups = "uart1_5_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ drive-strength = <12>;
+ };
+
+ conf-rx {
+ pins = "MIO21";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO20";
+ bias-disable;
+ };
+ };
+
+ pinctrl_usb0_default: usb0-default {
+ mux {
+ groups = "usb0_0_grp";
+ function = "usb0";
+ };
+
+ conf {
+ groups = "usb0_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ drive-strength = <12>;
+ };
+
+ conf-rx {
+ pins = "MIO52", "MIO53", "MIO55";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
+ "MIO60", "MIO61", "MIO62", "MIO63";
+ bias-disable;
+ };
+ };
+};
+
&qspi {
status = "okay";
flash at 0 {
@@ -274,21 +482,29 @@
&sdhci1 {
status = "okay";
no-1-8-v;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdhci1_default>;
xlnx,mio-bank = <1>;
disable-wp;
};
&uart0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0_default>;
};
&uart1 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_default>;
};
/* ULPI SMSC USB3320 */
&usb0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0_default>;
};
&dwc3_0 {
diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts b/arch/arm/dts/zynqmp-zcu104-revC.dts
index 8f30a2883e27..1b4cfb142a39 100644
--- a/arch/arm/dts/zynqmp-zcu104-revC.dts
+++ b/arch/arm/dts/zynqmp-zcu104-revC.dts
@@ -12,6 +12,7 @@
#include "zynqmp.dtsi"
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
#include <dt-bindings/phy/phy.h>
/ {
@@ -68,6 +69,8 @@
&can1 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can1_default>;
};
&dcc {
@@ -110,6 +113,8 @@
status = "okay";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gem3_default>;
phy0: ethernet-phy at c {
reg = <0xc>;
ti,rx-internal-delay = <0x8>;
@@ -130,6 +135,11 @@
&i2c1 {
status = "okay";
clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
tca6416_u97: gpio at 20 {
compatible = "ti,tca6416";
@@ -228,6 +238,204 @@
};
};
+&pinctrl0 {
+ status = "okay";
+
+ pinctrl_can1_default: can1-default {
+ mux {
+ function = "can1";
+ groups = "can1_6_grp";
+ };
+
+ conf {
+ groups = "can1_6_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ drive-strength = <12>;
+ };
+
+ conf-rx {
+ pins = "MIO25";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO24";
+ bias-disable;
+ };
+ };
+
+ pinctrl_i2c1_default: i2c1-default {
+ mux {
+ groups = "i2c1_4_grp";
+ function = "i2c1";
+ };
+
+ conf {
+ groups = "i2c1_4_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ drive-strength = <12>;
+ };
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpio {
+ mux {
+ groups = "gpio0_16_grp", "gpio0_17_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_16_grp", "gpio0_17_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ drive-strength = <12>;
+ };
+ };
+
+ pinctrl_gem3_default: gem3-default {
+ mux {
+ function = "ethernet3";
+ groups = "ethernet3_0_grp";
+ };
+
+ conf {
+ groups = "ethernet3_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ drive-strength = <12>;
+ };
+
+ conf-rx {
+ pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
+ "MIO75";
+ bias-high-impedance;
+ low-power-disable;
+ };
+
+ conf-tx {
+ pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
+ "MIO69";
+ bias-disable;
+ low-power-enable;
+ };
+
+ mux-mdio {
+ function = "mdio3";
+ groups = "mdio3_0_grp";
+ };
+
+ conf-mdio {
+ groups = "mdio3_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+ };
+
+ pinctrl_sdhci1_default: sdhci1-default {
+ mux {
+ groups = "sdio1_0_grp";
+ function = "sdio1";
+ };
+
+ conf {
+ groups = "sdio1_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ drive-strength = <12>;
+ };
+
+ mux-cd {
+ groups = "sdio1_cd_0_grp";
+ function = "sdio1_cd";
+ };
+
+ conf-cd {
+ groups = "sdio1_cd_0_grp";
+ bias-high-impedance;
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_uart0_default: uart0-default {
+ mux {
+ groups = "uart0_4_grp";
+ function = "uart0";
+ };
+
+ conf {
+ groups = "uart0_4_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ drive-strength = <12>;
+ };
+
+ conf-rx {
+ pins = "MIO18";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO19";
+ bias-disable;
+ };
+ };
+
+ pinctrl_uart1_default: uart1-default {
+ mux {
+ groups = "uart1_5_grp";
+ function = "uart1";
+ };
+
+ conf {
+ groups = "uart1_5_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ drive-strength = <12>;
+ };
+
+ conf-rx {
+ pins = "MIO21";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO20";
+ bias-disable;
+ };
+ };
+
+ pinctrl_usb0_default: usb0-default {
+ mux {
+ groups = "usb0_0_grp";
+ function = "usb0";
+ };
+
+ conf {
+ groups = "usb0_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ drive-strength = <12>;
+ };
+
+ conf-rx {
+ pins = "MIO52", "MIO53", "MIO55";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
+ "MIO60", "MIO61", "MIO62", "MIO63";
+ bias-disable;
+ };
+ };
+};
+
&qspi {
status = "okay";
flash at 0 {
@@ -287,21 +495,29 @@
&sdhci1 {
status = "okay";
no-1-8-v;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdhci1_default>;
xlnx,mio-bank = <1>;
disable-wp;
};
&uart0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0_default>;
};
&uart1 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_default>;
};
/* ULPI SMSC USB3320 */
&usb0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0_default>;
};
&dwc3_0 {
diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts
index 971f76f1cabe..9a6b00ff8c10 100644
--- a/arch/arm/dts/zynqmp-zcu106-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu106-revA.dts
@@ -13,6 +13,7 @@
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
#include <dt-bindings/phy/phy.h>
/ {
@@ -154,6 +155,8 @@
&can1 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can1_default>;
};
&dcc {
@@ -208,6 +211,8 @@
status = "okay";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gem3_default>;
phy0: ethernet-phy at c {
reg = <0xc>;
ti,rx-internal-delay = <0x8>;
@@ -219,6 +224,8 @@
&gpio {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_default>;
};
&gpu {
@@ -228,6 +235,11 @@
&i2c0 {
status = "okay";
clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c0_default>;
+ pinctrl-1 = <&pinctrl_i2c0_gpio>;
+ scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
tca6416_u97: gpio at 20 {
compatible = "ti,tca6416";
@@ -486,6 +498,11 @@
&i2c1 {
status = "okay";
clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
/* PL i2c via PCA9306 - u45 */
i2c-mux at 74 { /* u34 */
@@ -678,6 +695,269 @@
};
};
+&pinctrl0 {
+ status = "okay";
+ pinctrl_i2c0_default: i2c0-default {
+ mux {
+ groups = "i2c0_3_grp";
+ function = "i2c0";
+ };
+
+ conf {
+ groups = "i2c0_3_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c0_gpio: i2c0-gpio {
+ mux {
+ groups = "gpio0_14_grp", "gpio0_15_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_14_grp", "gpio0_15_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c1_default: i2c1-default {
+ mux {
+ groups = "i2c1_4_grp";
+ function = "i2c1";
+ };
+
+ conf {
+ groups = "i2c1_4_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpio {
+ mux {
+ groups = "gpio0_16_grp", "gpio0_17_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_16_grp", "gpio0_17_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_uart0_default: uart0-default {
+ mux {
+ groups = "uart0_4_grp";
+ function = "uart0";
+ };
+
+ conf {
+ groups = "uart0_4_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO18";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO19";
+ bias-disable;
+ };
+ };
+
+ pinctrl_uart1_default: uart1-default {
+ mux {
+ groups = "uart1_5_grp";
+ function = "uart1";
+ };
+
+ conf {
+ groups = "uart1_5_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO21";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO20";
+ bias-disable;
+ };
+ };
+
+ pinctrl_usb0_default: usb0-default {
+ mux {
+ groups = "usb0_0_grp";
+ function = "usb0";
+ };
+
+ conf {
+ groups = "usb0_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO52", "MIO53", "MIO55";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
+ "MIO60", "MIO61", "MIO62", "MIO63";
+ bias-disable;
+ };
+ };
+
+ pinctrl_gem3_default: gem3-default {
+ mux {
+ function = "ethernet3";
+ groups = "ethernet3_0_grp";
+ };
+
+ conf {
+ groups = "ethernet3_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
+ "MIO75";
+ bias-high-impedance;
+ low-power-disable;
+ };
+
+ conf-tx {
+ pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
+ "MIO69";
+ bias-disable;
+ low-power-enable;
+ };
+
+ mux-mdio {
+ function = "mdio3";
+ groups = "mdio3_0_grp";
+ };
+
+ conf-mdio {
+ groups = "mdio3_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+ };
+
+ pinctrl_can1_default: can1-default {
+ mux {
+ function = "can1";
+ groups = "can1_6_grp";
+ };
+
+ conf {
+ groups = "can1_6_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO25";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO24";
+ bias-disable;
+ };
+ };
+
+ pinctrl_sdhci1_default: sdhci1-default {
+ mux {
+ groups = "sdio1_0_grp";
+ function = "sdio1";
+ };
+
+ conf {
+ groups = "sdio1_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+
+ mux-cd {
+ groups = "sdio1_cd_0_grp";
+ function = "sdio1_cd";
+ };
+
+ conf-cd {
+ groups = "sdio1_cd_0_grp";
+ bias-high-impedance;
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux-wp {
+ groups = "sdio1_wp_0_grp";
+ function = "sdio1_wp";
+ };
+
+ conf-wp {
+ groups = "sdio1_wp_0_grp";
+ bias-high-impedance;
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_gpio_default: gpio-default {
+ mux {
+ function = "gpio0";
+ groups = "gpio0_22_grp", "gpio0_23_grp";
+ };
+
+ conf {
+ groups = "gpio0_22_grp", "gpio0_23_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux-msp {
+ function = "gpio0";
+ groups = "gpio0_13_grp", "gpio0_38_grp";
+ };
+
+ conf-msp {
+ groups = "gpio0_13_grp", "gpio0_38_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-pull-up {
+ pins = "MIO22";
+ bias-pull-up;
+ };
+
+ conf-pull-none {
+ pins = "MIO13", "MIO23", "MIO38";
+ bias-disable;
+ };
+ };
+};
+
&psgtr {
status = "okay";
/* nc, sata, usb3, dp */
@@ -741,20 +1021,28 @@
* This property should be removed for supporting UHS mode
*/
no-1-8-v;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdhci1_default>;
xlnx,mio-bank = <1>;
};
&uart0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0_default>;
};
&uart1 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_default>;
};
/* ULPI SMSC USB3320 */
&usb0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0_default>;
};
&dwc3_0 {
diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts
index 9e47008542ae..ec2bf537dff7 100644
--- a/arch/arm/dts/zynqmp-zcu111-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu111-revA.dts
@@ -13,6 +13,7 @@
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
#include <dt-bindings/phy/phy.h>
/ {
@@ -170,6 +171,8 @@
status = "okay";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gem3_default>;
phy0: ethernet-phy at c {
reg = <0xc>;
ti,rx-internal-delay = <0x8>;
@@ -181,6 +184,8 @@
&gpio {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_default>;
};
&gpu {
@@ -190,6 +195,11 @@
&i2c0 {
status = "okay";
clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c0_default>;
+ pinctrl-1 = <&pinctrl_i2c0_gpio>;
+ scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
tca6416_u22: gpio at 20 {
compatible = "ti,tca6416";
@@ -365,6 +375,11 @@
&i2c1 {
status = "okay";
clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
i2c-mux at 74 { /* u26 */
compatible = "nxp,pca9548";
@@ -554,6 +569,210 @@
};
};
+&pinctrl0 {
+ status = "okay";
+ pinctrl_i2c0_default: i2c0-default {
+ mux {
+ groups = "i2c0_3_grp";
+ function = "i2c0";
+ };
+
+ conf {
+ groups = "i2c0_3_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c0_gpio: i2c0-gpio {
+ mux {
+ groups = "gpio0_14_grp", "gpio0_15_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_14_grp", "gpio0_15_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c1_default: i2c1-default {
+ mux {
+ groups = "i2c1_4_grp";
+ function = "i2c1";
+ };
+
+ conf {
+ groups = "i2c1_4_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpio {
+ mux {
+ groups = "gpio0_16_grp", "gpio0_17_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_16_grp", "gpio0_17_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_uart0_default: uart0-default {
+ mux {
+ groups = "uart0_4_grp";
+ function = "uart0";
+ };
+
+ conf {
+ groups = "uart0_4_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO18";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO19";
+ bias-disable;
+ };
+ };
+
+ pinctrl_usb0_default: usb0-default {
+ mux {
+ groups = "usb0_0_grp";
+ function = "usb0";
+ };
+
+ conf {
+ groups = "usb0_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO52", "MIO53", "MIO55";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
+ "MIO60", "MIO61", "MIO62", "MIO63";
+ bias-disable;
+ };
+ };
+
+ pinctrl_gem3_default: gem3-default {
+ mux {
+ function = "ethernet3";
+ groups = "ethernet3_0_grp";
+ };
+
+ conf {
+ groups = "ethernet3_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
+ "MIO75";
+ bias-high-impedance;
+ low-power-disable;
+ };
+
+ conf-tx {
+ pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
+ "MIO69";
+ bias-disable;
+ low-power-enable;
+ };
+
+ mux-mdio {
+ function = "mdio3";
+ groups = "mdio3_0_grp";
+ };
+
+ conf-mdio {
+ groups = "mdio3_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+ };
+
+ pinctrl_sdhci1_default: sdhci1-default {
+ mux {
+ groups = "sdio1_0_grp";
+ function = "sdio1";
+ };
+
+ conf {
+ groups = "sdio1_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+
+ mux-cd {
+ groups = "sdio1_cd_0_grp";
+ function = "sdio1_cd";
+ };
+
+ conf-cd {
+ groups = "sdio1_cd_0_grp";
+ bias-high-impedance;
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_gpio_default: gpio-default {
+ mux {
+ function = "gpio0";
+ groups = "gpio0_22_grp", "gpio0_23_grp";
+ };
+
+ conf {
+ groups = "gpio0_22_grp", "gpio0_23_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux-msp {
+ function = "gpio0";
+ groups = "gpio0_13_grp", "gpio0_38_grp";
+ };
+
+ conf-msp {
+ groups = "gpio0_13_grp", "gpio0_38_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-pull-up {
+ pins = "MIO22";
+ bias-pull-up;
+ };
+
+ conf-pull-none {
+ pins = "MIO13", "MIO23", "MIO38";
+ bias-disable;
+ };
+ };
+};
+
&psgtr {
status = "okay";
/* nc, sata, usb3, dp */
@@ -613,6 +832,8 @@
/* SD1 with level shifter */
&sdhci1 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdhci1_default>;
disable-wp;
/*
* This property should be removed for supporting UHS mode
@@ -623,11 +844,15 @@
&uart0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0_default>;
};
/* ULPI SMSC USB3320 */
&usb0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0_default>;
dr_mode = "host";
};
diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dts b/arch/arm/dts/zynqmp-zcu208-revA.dts
index cd2f02f21de5..0dc9880b923a 100644
--- a/arch/arm/dts/zynqmp-zcu208-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu208-revA.dts
@@ -13,6 +13,7 @@
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
#include <dt-bindings/phy/phy.h>
/ {
@@ -221,6 +222,11 @@
&i2c0 {
status = "okay";
clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c0_default>;
+ pinctrl-1 = <&pinctrl_i2c0_gpio>;
+ scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
tca6416_u15: gpio at 20 { /* u15 */
compatible = "ti,tca6416";
@@ -382,6 +388,11 @@
&i2c1 {
status = "okay";
clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
i2c-mux at 74 {
compatible = "nxp,pca9548"; /* u20 */
@@ -567,6 +578,63 @@
/* MSP430 */
};
+&pinctrl0 {
+ status = "okay";
+ pinctrl_i2c0_default: i2c0-default {
+ mux {
+ groups = "i2c0_3_grp";
+ function = "i2c0";
+ };
+
+ conf {
+ groups = "i2c0_3_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c0_gpio: i2c0-gpio {
+ mux {
+ groups = "gpio0_14_grp", "gpio0_15_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_14_grp", "gpio0_15_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c1_default: i2c1-default {
+ mux {
+ groups = "i2c1_4_grp";
+ function = "i2c1";
+ };
+
+ conf {
+ groups = "i2c1_4_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpio {
+ mux {
+ groups = "gpio0_16_grp", "gpio0_17_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_16_grp", "gpio0_17_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+};
+
&qspi {
status = "okay";
is-dual = <1>;
diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts b/arch/arm/dts/zynqmp-zcu216-revA.dts
index 8aecb1529250..e0258ea0dda3 100644
--- a/arch/arm/dts/zynqmp-zcu216-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu216-revA.dts
@@ -13,6 +13,7 @@
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
#include <dt-bindings/phy/phy.h>
/ {
@@ -232,6 +233,11 @@
&i2c0 {
status = "okay";
clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c0_default>;
+ pinctrl-1 = <&pinctrl_i2c0_gpio>;
+ scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
tca6416_u15: gpio at 20 { /* u15 */
compatible = "ti,tca6416";
@@ -393,6 +399,11 @@
&i2c1 {
status = "okay";
clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
i2c-mux at 74 {
compatible = "nxp,pca9548"; /* u20 */
@@ -578,6 +589,63 @@
/* MSP430 */
};
+&pinctrl0 {
+ status = "okay";
+ pinctrl_i2c0_default: i2c0-default {
+ mux {
+ groups = "i2c0_3_grp";
+ function = "i2c0";
+ };
+
+ conf {
+ groups = "i2c0_3_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c0_gpio: i2c0-gpio {
+ mux {
+ groups = "gpio0_14_grp", "gpio0_15_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_14_grp", "gpio0_15_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c1_default: i2c1-default {
+ mux {
+ groups = "i2c1_4_grp";
+ function = "i2c1";
+ };
+
+ conf {
+ groups = "i2c1_4_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpio {
+ mux {
+ groups = "gpio0_16_grp", "gpio0_17_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_16_grp", "gpio0_17_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+};
+
&qspi {
status = "okay";
is-dual = <1>;
diff --git a/include/dt-bindings/pinctrl/pinctrl-zynqmp.h b/include/dt-bindings/pinctrl/pinctrl-zynqmp.h
new file mode 100644
index 000000000000..cdb215734bdf
--- /dev/null
+++ b/include/dt-bindings/pinctrl/pinctrl-zynqmp.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * MIO pin configuration defines for Xilinx ZynqMP
+ *
+ * Copyright (C) 2020 Xilinx, Inc.
+ */
+
+#ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H
+#define _DT_BINDINGS_PINCTRL_ZYNQMP_H
+
+/* Bit value for different voltage levels */
+#define IO_STANDARD_LVCMOS33 0
+#define IO_STANDARD_LVCMOS18 1
+
+/* Bit values for Slew Rates */
+#define SLEW_RATE_FAST 0
+#define SLEW_RATE_SLOW 1
+
+#endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */
--
2.31.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH 09/10] arm64: zynqmp: Add psgtr DT descriptions
2021-05-10 14:17 [PATCH 00/10] arm64: zynqmp: Add support for KRIA boards and update phy/pinctrl descs Michal Simek
` (7 preceding siblings ...)
2021-05-10 14:17 ` [PATCH 08/10] arm64: zynqmp: Add pinctrl description Michal Simek
@ 2021-05-10 14:17 ` Michal Simek
2021-05-10 14:17 ` [PATCH 10/10] arm64: zynqmp: Add description for SOM/Kria boards Michal Simek
2021-05-19 8:05 ` [PATCH 00/10] arm64: zynqmp: Add support for KRIA boards and update phy/pinctrl descs Michal Simek
10 siblings, 0 replies; 12+ messages in thread
From: Michal Simek @ 2021-05-10 14:17 UTC (permalink / raw)
To: u-boot
Mainline kernel has psgtr driver that's why it is good to add description
to DT files. Some boards are just missing description for USB3 and sata.
zc1751-dc1 and p-a2197 are also missing clock descriptions for input
clocks.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
arch/arm/dts/zynqmp-p-a2197-00-revA.dts | 22 +++++++++++++++++
arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 31 ++++++++++++++++++++++++
arch/arm/dts/zynqmp-zcu100-revC.dts | 4 +++
arch/arm/dts/zynqmp-zcu102-revA.dts | 2 ++
arch/arm/dts/zynqmp-zcu104-revA.dts | 2 ++
arch/arm/dts/zynqmp-zcu104-revC.dts | 2 ++
arch/arm/dts/zynqmp-zcu106-revA.dts | 2 ++
arch/arm/dts/zynqmp-zcu111-revA.dts | 9 ++++++-
arch/arm/dts/zynqmp-zcu208-revA.dts | 3 +++
arch/arm/dts/zynqmp-zcu216-revA.dts | 3 +++
10 files changed, 79 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts
index 8e1e6b7f903b..1f5201ac8883 100644
--- a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts
+++ b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts
@@ -11,6 +11,7 @@
#include "zynqmp.dtsi"
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/phy/phy.h>
/ {
model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */
@@ -43,6 +44,18 @@
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
+
+ si5332_1: si5332_1 { /* clk0_sgmii - u142 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <33333333>; /* FIXME */
+ };
+
+ si5332_2: si5332_2 { /* clk1_usb - u142 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <27000000>;
+ };
};
&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */
@@ -70,6 +83,13 @@
xlnx,mio-bank = <1>;
};
+&psgtr {
+ status = "okay";
+ /* sgmii, usb3 */
+ clocks = <&si5332_1>, <&si5332_2>;
+ clock-names = "ref0", "ref1";
+};
+
&gem0 {
status = "okay";
phy-handle = <&phy0>;
@@ -537,6 +557,8 @@
snps,dis_u2_susphy_quirk;
snps,dis_u3_susphy_quirk;
maximum-speed = "super-speed";
+ phy-names = "usb3-phy";
+ phys = <&psgtr 1 PHY_TYPE_USB3 0 1>;
};
&usb1 {
diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
index d5862c1cabe9..039a8da1a960 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
@@ -11,6 +11,7 @@
#include "zynqmp.dtsi"
#include "zynqmp-clk-ccf.dtsi"
+#include <dt-bindings/phy/phy.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
@@ -39,6 +40,31 @@
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
};
+
+ clock_si5338_0: clk27 { /* u55 SI5338-GM */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <27000000>;
+ };
+
+ clock_si5338_2: clk26 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ };
+
+ clock_si5338_3: clk150 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <150000000>;
+ };
+};
+
+&psgtr {
+ status = "okay";
+ /* dp, usb3, sata */
+ clocks = <&clock_si5338_0>, <&clock_si5338_2>, <&clock_si5338_3>;
+ clock-names = "ref1", "ref2", "ref3";
};
&fpd_dma_chan1 {
@@ -363,6 +389,8 @@
ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ phy-names = "sata-phy";
+ phys = <&psgtr 3 PHY_TYPE_SATA 1 3>;
};
/* eMMC */
@@ -402,6 +430,9 @@
&dwc3_0 {
status = "okay";
dr_mode = "host";
+ snps,usb3_lpm_capable;
+ phy-names = "usb3-phy";
+ phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
};
&zynqmp_dpdma {
diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts b/arch/arm/dts/zynqmp-zcu100-revC.dts
index 9603043db109..b83696cccd2b 100644
--- a/arch/arm/dts/zynqmp-zcu100-revC.dts
+++ b/arch/arm/dts/zynqmp-zcu100-revC.dts
@@ -567,6 +567,8 @@
&dwc3_0 {
status = "okay";
dr_mode = "peripheral";
+ phy-names = "usb3-phy";
+ phys = <&psgtr 2 PHY_TYPE_USB3 0 0>;
maximum-speed = "super-speed";
};
@@ -580,6 +582,8 @@
&dwc3_1 {
status = "okay";
dr_mode = "host";
+ phy-names = "usb3-phy";
+ phys = <&psgtr 3 PHY_TYPE_USB3 1 0>;
maximum-speed = "super-speed";
};
diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts
index 27c3dcc87f96..ec61b7089da2 100644
--- a/arch/arm/dts/zynqmp-zcu102-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revA.dts
@@ -1034,6 +1034,8 @@
status = "okay";
dr_mode = "host";
snps,usb3_lpm_capable;
+ phy-names = "usb3-phy";
+ phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
maximum-speed = "super-speed";
};
diff --git a/arch/arm/dts/zynqmp-zcu104-revA.dts b/arch/arm/dts/zynqmp-zcu104-revA.dts
index bad73d9093c0..c25ac9af48e8 100644
--- a/arch/arm/dts/zynqmp-zcu104-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu104-revA.dts
@@ -511,6 +511,8 @@
status = "okay";
dr_mode = "host";
snps,usb3_lpm_capable;
+ phy-names = "usb3-phy";
+ phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
maximum-speed = "super-speed";
};
diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts b/arch/arm/dts/zynqmp-zcu104-revC.dts
index 1b4cfb142a39..ce9d8fb3b815 100644
--- a/arch/arm/dts/zynqmp-zcu104-revC.dts
+++ b/arch/arm/dts/zynqmp-zcu104-revC.dts
@@ -524,6 +524,8 @@
status = "okay";
dr_mode = "host";
snps,usb3_lpm_capable;
+ phy-names = "usb3-phy";
+ phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
maximum-speed = "super-speed";
};
diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts
index 9a6b00ff8c10..ae20e581c0f4 100644
--- a/arch/arm/dts/zynqmp-zcu106-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu106-revA.dts
@@ -1049,6 +1049,8 @@
status = "okay";
dr_mode = "host";
snps,usb3_lpm_capable;
+ phy-names = "usb3-phy";
+ phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
};
&watchdog0 {
diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts
index ec2bf537dff7..d564f74344c9 100644
--- a/arch/arm/dts/zynqmp-zcu111-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu111-revA.dts
@@ -826,7 +826,7 @@
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
phy-names = "sata-phy";
- phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
+ phys = <&psgtr 3 PHY_TYPE_SATA 1 3>;
};
/* SD1 with level shifter */
@@ -853,7 +853,14 @@
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0_default>;
+};
+
+&dwc3_0 {
+ status = "okay";
dr_mode = "host";
+ snps,usb3_lpm_capable;
+ phy-names = "usb3-phy";
+ phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
};
&zynqmp_dpdma {
diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dts b/arch/arm/dts/zynqmp-zcu208-revA.dts
index 0dc9880b923a..880281d4e79b 100644
--- a/arch/arm/dts/zynqmp-zcu208-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu208-revA.dts
@@ -671,6 +671,7 @@
ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ phy-names = "sata-phy";
phys = <&psgtr 3 PHY_TYPE_SATA 1 3>;
};
@@ -698,4 +699,6 @@
status = "okay";
dr_mode = "host";
snps,usb3_lpm_capable;
+ phy-names = "usb3-phy";
+ phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
};
diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts b/arch/arm/dts/zynqmp-zcu216-revA.dts
index e0258ea0dda3..f899226ae198 100644
--- a/arch/arm/dts/zynqmp-zcu216-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu216-revA.dts
@@ -675,6 +675,7 @@
ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ phy-names = "sata-phy";
phys = <&psgtr 3 PHY_TYPE_SATA 1 3>;
};
@@ -702,4 +703,6 @@
status = "okay";
dr_mode = "host";
snps,usb3_lpm_capable;
+ phy-names = "usb3-phy";
+ phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
};
--
2.31.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH 10/10] arm64: zynqmp: Add description for SOM/Kria boards
2021-05-10 14:17 [PATCH 00/10] arm64: zynqmp: Add support for KRIA boards and update phy/pinctrl descs Michal Simek
` (8 preceding siblings ...)
2021-05-10 14:17 ` [PATCH 09/10] arm64: zynqmp: Add psgtr DT descriptions Michal Simek
@ 2021-05-10 14:17 ` Michal Simek
2021-05-19 8:05 ` [PATCH 00/10] arm64: zynqmp: Add support for KRIA boards and update phy/pinctrl descs Michal Simek
10 siblings, 0 replies; 12+ messages in thread
From: Michal Simek @ 2021-05-10 14:17 UTC (permalink / raw)
To: u-boot
The patch contains several DT files for SOM platform.
Carrier card is sck-kv (KV260) revA/B. SMK-K26 is description for starter
kit which doesn't have EMMC populated. And SM-K26 is full som with EMMC.
Files are divided in this way to make sure that SOM can be plugged to
different carrier card and all peripherals on SOM (or defined by a spec) can
be used by U-Boot. Full DT for SOM+CC can be merged together as overlays.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
arch/arm/dts/Makefile | 4 +
arch/arm/dts/zynqmp-sck-kv-g-revA.dts | 373 +++++++++++++++++++
arch/arm/dts/zynqmp-sck-kv-g-revB.dts | 353 ++++++++++++++++++
arch/arm/dts/zynqmp-sm-k26-revA-u-boot.dtsi | 21 ++
arch/arm/dts/zynqmp-sm-k26-revA.dts | 316 ++++++++++++++++
arch/arm/dts/zynqmp-smk-k26-revA-u-boot.dtsi | 21 ++
arch/arm/dts/zynqmp-smk-k26-revA.dts | 21 ++
configs/xilinx_zynqmp_virt_defconfig | 2 +-
8 files changed, 1110 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/zynqmp-sck-kv-g-revA.dts
create mode 100644 arch/arm/dts/zynqmp-sck-kv-g-revB.dts
create mode 100644 arch/arm/dts/zynqmp-sm-k26-revA-u-boot.dtsi
create mode 100644 arch/arm/dts/zynqmp-sm-k26-revA.dts
create mode 100644 arch/arm/dts/zynqmp-smk-k26-revA-u-boot.dtsi
create mode 100644 arch/arm/dts/zynqmp-smk-k26-revA.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index a5cae010c263..ed40b1f85a6d 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -305,6 +305,10 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
zynqmp-mini-emmc1.dtb \
zynqmp-mini-nand.dtb \
zynqmp-mini-qspi.dtb \
+ zynqmp-sm-k26-revA.dtb \
+ zynqmp-smk-k26-revA.dtb \
+ zynqmp-sck-kv-g-revA.dtbo \
+ zynqmp-sck-kv-g-revB.dtbo \
zynqmp-topic-miamimp-xilinx-xdp-v1r1.dtb \
zynqmp-zcu100-revC.dtb \
zynqmp-zcu102-revA.dtb \
diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts
new file mode 100644
index 000000000000..cad2d0572185
--- /dev/null
+++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts
@@ -0,0 +1,373 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for KV260 revA Carrier Card
+ *
+ * (C) Copyright 2020, Xilinx, Inc.
+ *
+ * SD level shifter:
+ * "A" ? A01 board un-modified (NXP)
+ * "Y" ? A01 board modified with legacy interposer (Nexperia)
+ * "Z" ? A01 board modified with Diode interposer
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/net/ti-dp83867.h>
+ #include <dt-bindings/phy/phy.h>
+ #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
+
+/dts-v1/;
+/plugin/;
+
+/{
+ compatible = "xlnx,zynqmp-sk-kv260-revA",
+ "xlnx,zynqmp-sk-kv260-revY",
+ "xlnx,zynqmp-sk-kv260-revZ",
+ "xlnx,zynqmp-sk-kv260", "xlnx,zynqmp";
+
+ fragment1 {
+ target = <&i2c1>; /* I2C_SCK C23/C24 - MIO from SOM */
+
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
+
+ u14: ina260 at 40 { /* u14 */
+ compatible = "ti,ina260";
+ #io-channel-cells = <1>;
+ label = "ina260-u14";
+ reg = <0x40>;
+ };
+ /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */
+ };
+ };
+
+ fragment1a {
+ target = <&amba>;
+ __overlay__ {
+ ina260-u14 {
+ compatible = "iio-hwmon";
+ io-channels = <&u14 0>, <&u14 1>, <&u14 2>;
+ };
+
+ si5332_0: si5332_0 { /* u17 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
+ si5332_1: si5332_1 { /* u17 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+
+ si5332_2: si5332_2 { /* u17 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <48000000>;
+ };
+
+ si5332_3: si5332_3 { /* u17 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ };
+
+ si5332_4: si5332_4 { /* u17 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ };
+
+ si5332_5: si5332_5 { /* u17 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <27000000>;
+ };
+ };
+ };
+
+/* DP/USB 3.0 and SATA */
+ fragment2 {
+ target = <&psgtr>;
+ __overlay__ {
+ status = "okay";
+ /* pcie, usb3, sata */
+ clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>;
+ clock-names = "ref0", "ref1", "ref2";
+ };
+ };
+
+ fragment3 {
+ target = <&sata>;
+ __overlay__ {
+ status = "okay";
+ /* SATA OOB timing settings */
+ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+ ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+ ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+ ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+ ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ phy-names = "sata-phy";
+ phys = <&psgtr 3 PHY_TYPE_SATA 1 2>;
+ };
+ };
+
+ fragment4 {
+ target = <&zynqmp_dpsub>;
+ __overlay__ {
+ status = "disabled";
+ phy-names = "dp-phy0", "dp-phy1";
+ phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
+ };
+ };
+
+ fragment9 {
+ target = <&zynqmp_dpdma>;
+ __overlay__ {
+ status = "okay";
+ };
+ };
+
+ fragment10 {
+ target = <&usb0>;
+ __overlay__ {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0_default>;
+ usbhub: usb5744 { /* u43 */
+ compatible = "microchip,usb5744";
+ reset-gpios = <&gpio 44 GPIO_ACTIVE_HIGH>;
+ };
+ };
+ };
+
+ fragment11 {
+ target = <&dwc3_0>;
+ __overlay__ {
+ status = "okay";
+ dr_mode = "host";
+ snps,usb3_lpm_capable;
+ phy-names = "usb3-phy";
+ phys = <&psgtr 2 PHY_TYPE_USB3 0 1>;
+ maximum-speed = "super-speed";
+ };
+ };
+
+ fragment12 {
+ target = <&sdhci1>; /* on CC with tuned parameters */
+ __overlay__ {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdhci1_default>;
+ /*
+ * SD 3.0 requires level shifter and this property
+ * should be removed if the board has level shifter and
+ * need to work in UHS mode
+ */
+ no-1-8-v;
+ disable-wp;
+ xlnx,mio-bank = <1>;
+ };
+ };
+
+ fragment13 {
+ target = <&gem3>; /* required by spec */
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gem3_default>;
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
+ reset-delay-us = <2>;
+
+ phy0: ethernet-phy at 1 {
+ #phy-cells = <1>;
+ reg = <1>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ ti,dp83867-rxctrl-strap-quirk;
+ };
+ };
+ };
+ };
+
+ fragment14 {
+ target = <&pinctrl0>; /* required by spec */
+ __overlay__ {
+ status = "okay";
+
+ pinctrl_uart1_default: uart1-default {
+ conf {
+ groups = "uart1_9_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ drive-strength = <12>;
+ };
+
+ conf-rx {
+ pins = "MIO37";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO36";
+ bias-disable;
+ };
+
+ mux {
+ groups = "uart1_9_grp";
+ function = "uart1";
+ };
+ };
+
+ pinctrl_i2c1_default: i2c1-default {
+ conf {
+ groups = "i2c1_6_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux {
+ groups = "i2c1_6_grp";
+ function = "i2c1";
+ };
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpio {
+ conf {
+ groups = "gpio0_24_grp", "gpio0_25_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux {
+ groups = "gpio0_24_grp", "gpio0_25_grp";
+ function = "gpio0";
+ };
+ };
+
+ pinctrl_gem3_default: gem3-default {
+ conf {
+ groups = "ethernet3_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO70", "MIO72", "MIO74";
+ bias-high-impedance;
+ low-power-disable;
+ };
+
+ conf-bootstrap {
+ pins = "MIO71", "MIO73", "MIO75";
+ bias-disable;
+ low-power-disable;
+ };
+
+ conf-tx {
+ pins = "MIO64", "MIO65", "MIO66",
+ "MIO67", "MIO68", "MIO69";
+ bias-disable;
+ low-power-enable;
+ };
+
+ conf-mdio {
+ groups = "mdio3_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+
+ mux-mdio {
+ function = "mdio3";
+ groups = "mdio3_0_grp";
+ };
+
+ mux {
+ function = "ethernet3";
+ groups = "ethernet3_0_grp";
+ };
+ };
+
+ pinctrl_usb0_default: usb0-default {
+ conf {
+ groups = "usb0_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO52", "MIO53", "MIO55";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
+ "MIO60", "MIO61", "MIO62", "MIO63";
+ bias-disable;
+ };
+
+ mux {
+ groups = "usb0_0_grp";
+ function = "usb0";
+ };
+ };
+
+ pinctrl_sdhci1_default: sdhci1-default {
+ conf {
+ groups = "sdio1_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+
+ conf-cd {
+ groups = "sdio1_cd_0_grp";
+ bias-high-impedance;
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux-cd {
+ groups = "sdio1_cd_0_grp";
+ function = "sdio1_cd";
+ };
+
+ mux {
+ groups = "sdio1_0_grp";
+ function = "sdio1";
+ };
+ };
+ };
+ };
+ fragment15 {
+ target = <&uart1>;
+ __overlay__ {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_default>;
+ };
+ };
+};
diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
new file mode 100644
index 000000000000..6e46f5717b23
--- /dev/null
+++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
@@ -0,0 +1,353 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for KV260 revA Carrier Card
+ *
+ * (C) Copyright 2020, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/net/ti-dp83867.h>
+ #include <dt-bindings/phy/phy.h>
+ #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
+
+/dts-v1/;
+/plugin/;
+
+/{
+ compatible = "xlnx,zynqmp-sk-kv260-rev1",
+ "xlnx,zynqmp-sk-kv260-revB", "xlnx,zynqmp-sk-kv260-revA",
+ "xlnx,zynqmp-sk-kv260", "xlnx,zynqmp";
+
+ fragment1 {
+ target = <&i2c1>; /* I2C_SCK C23/C24 - MIO from SOM */
+
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
+
+ u14: ina260 at 40 { /* u14 */
+ compatible = "ti,ina260";
+ #io-channel-cells = <1>;
+ label = "ina260-u14";
+ reg = <0x40>;
+ };
+ usbhub: usb5744 at 2d { /* u43 */
+ compatible = "microchip,usb5744";
+ reg = <0x2d>;
+ reset-gpios = <&gpio 44 GPIO_ACTIVE_HIGH>;
+ };
+ /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */
+ };
+ };
+
+ fragment1a {
+ target = <&amba>;
+ __overlay__ {
+ ina260-u14 {
+ compatible = "iio-hwmon";
+ io-channels = <&u14 0>, <&u14 1>, <&u14 2>;
+ };
+
+ si5332_0: si5332_0 { /* u17 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
+ si5332_1: si5332_1 { /* u17 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+
+ si5332_2: si5332_2 { /* u17 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <48000000>;
+ };
+
+ si5332_3: si5332_3 { /* u17 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ };
+
+ si5332_4: si5332_4 { /* u17 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ };
+
+ si5332_5: si5332_5 { /* u17 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <27000000>;
+ };
+ };
+ };
+
+/* DP/USB 3.0 */
+ fragment2 {
+ target = <&psgtr>;
+ __overlay__ {
+ status = "okay";
+ /* pcie, usb3, sata */
+ clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>;
+ clock-names = "ref0", "ref1", "ref2";
+ };
+ };
+
+ fragment4 {
+ target = <&zynqmp_dpsub>;
+ __overlay__ {
+ status = "disabled";
+ phy-names = "dp-phy0", "dp-phy1";
+ phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
+ };
+ };
+
+ fragment9 {
+ target = <&zynqmp_dpdma>;
+ __overlay__ {
+ status = "okay";
+ };
+ };
+
+ fragment10 {
+ target = <&usb0>;
+ __overlay__ {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0_default>;
+ };
+ };
+
+ fragment11 {
+ target = <&dwc3_0>;
+ __overlay__ {
+ status = "okay";
+ dr_mode = "host";
+ snps,usb3_lpm_capable;
+ phy-names = "usb3-phy";
+ phys = <&psgtr 2 PHY_TYPE_USB3 0 1>;
+ maximum-speed = "super-speed";
+ };
+ };
+
+ fragment12 {
+ target = <&sdhci1>; /* on CC with tuned parameters */
+ __overlay__ {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdhci1_default>;
+ /*
+ * SD 3.0 requires level shifter and this property
+ * should be removed if the board has level shifter and
+ * need to work in UHS mode
+ */
+ no-1-8-v;
+ disable-wp;
+ xlnx,mio-bank = <1>;
+ clk-phase-sd-hs = <126>, <60>;
+ clk-phase-uhs-sdr25 = <120>, <60>;
+ clk-phase-uhs-ddr50 = <126>, <48>;
+ };
+ };
+
+ fragment13 {
+ target = <&gem3>; /* required by spec */
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gem3_default>;
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
+ reset-delay-us = <2>;
+
+ phy0: ethernet-phy at 1 {
+ #phy-cells = <1>;
+ reg = <1>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ ti,dp83867-rxctrl-strap-quirk;
+ };
+ };
+ };
+ };
+
+ fragment14 {
+ target = <&pinctrl0>; /* required by spec */
+ __overlay__ {
+ status = "okay";
+
+ pinctrl_uart1_default: uart1-default {
+ conf {
+ groups = "uart1_9_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ drive-strength = <12>;
+ };
+
+ conf-rx {
+ pins = "MIO37";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO36";
+ bias-disable;
+ };
+
+ mux {
+ groups = "uart1_9_grp";
+ function = "uart1";
+ };
+ };
+
+ pinctrl_i2c1_default: i2c1-default {
+ conf {
+ groups = "i2c1_6_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux {
+ groups = "i2c1_6_grp";
+ function = "i2c1";
+ };
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpio {
+ conf {
+ groups = "gpio0_24_grp", "gpio0_25_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux {
+ groups = "gpio0_24_grp", "gpio0_25_grp";
+ function = "gpio0";
+ };
+ };
+
+ pinctrl_gem3_default: gem3-default {
+ conf {
+ groups = "ethernet3_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO70", "MIO72", "MIO74";
+ bias-high-impedance;
+ low-power-disable;
+ };
+
+ conf-bootstrap {
+ pins = "MIO71", "MIO73", "MIO75";
+ bias-disable;
+ low-power-disable;
+ };
+
+ conf-tx {
+ pins = "MIO64", "MIO65", "MIO66",
+ "MIO67", "MIO68", "MIO69";
+ bias-disable;
+ low-power-enable;
+ };
+
+ conf-mdio {
+ groups = "mdio3_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+
+ mux-mdio {
+ function = "mdio3";
+ groups = "mdio3_0_grp";
+ };
+
+ mux {
+ function = "ethernet3";
+ groups = "ethernet3_0_grp";
+ };
+ };
+
+ pinctrl_usb0_default: usb0-default {
+ conf {
+ groups = "usb0_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO52", "MIO53", "MIO55";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
+ "MIO60", "MIO61", "MIO62", "MIO63";
+ bias-disable;
+ };
+
+ mux {
+ groups = "usb0_0_grp";
+ function = "usb0";
+ };
+ };
+
+ pinctrl_sdhci1_default: sdhci1-default {
+ conf {
+ groups = "sdio1_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+
+ conf-cd {
+ groups = "sdio1_cd_0_grp";
+ bias-high-impedance;
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux-cd {
+ groups = "sdio1_cd_0_grp";
+ function = "sdio1_cd";
+ };
+
+ mux {
+ groups = "sdio1_0_grp";
+ function = "sdio1";
+ };
+ };
+ };
+ };
+ fragment15 {
+ target = <&uart1>;
+ __overlay__ {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_default>;
+ };
+ };
+};
diff --git a/arch/arm/dts/zynqmp-sm-k26-revA-u-boot.dtsi b/arch/arm/dts/zynqmp-sm-k26-revA-u-boot.dtsi
new file mode 100644
index 000000000000..3f01233cc5a2
--- /dev/null
+++ b/arch/arm/dts/zynqmp-sm-k26-revA-u-boot.dtsi
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP K26/KV260 SD wiring
+ *
+ * (C) Copyright 2020, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/* SD0 only supports 3.3V, no level shifter */
+&sdhci1 { /* on CC - MIO 39 - 51 */
+ status = "okay";
+ no-1-8-v;
+ disable-wp;
+ broken-cd;
+ xlnx,mio-bank = <1>;
+ /* Do not run SD in HS mode from bootloader */
+ sdhci-caps-mask = <0 0x200000>;
+ sdhci-caps = <0 0>;
+ max-frequency = <19000000>;
+};
diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts
new file mode 100644
index 000000000000..e4cf382a4975
--- /dev/null
+++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts
@@ -0,0 +1,316 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP SM-K26 rev1/B/A
+ *
+ * (C) Copyright 2020, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/phy/phy.h>
+
+/ {
+ model = "ZynqMP SM-K26 Rev1/B/A";
+ compatible = "xlnx,zynqmp-sm-k26-rev1", "xlnx,zynqmp-sm-k26-revB",
+ "xlnx,zynqmp-sm-k26-revA", "xlnx,zynqmp-sm-k26",
+ "xlnx,zynqmp";
+
+ aliases {
+ gpio0 = &gpio;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ mmc0 = &sdhci0;
+ mmc1 = &sdhci1;
+ rtc0 = &rtc;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &dcc;
+ spi0 = &qspi;
+ spi1 = &spi0;
+ spi2 = &spi1;
+ usb0 = &usb0;
+ usb1 = &usb1;
+ nvmem0 = &eeprom;
+ nvmem1 = &eeprom_cc;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial1:115200n8";
+ };
+
+ memory at 0 {
+ device_type = "memory"; /* 4GB */
+ reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+ fwuen {
+ label = "fwuen";
+ gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ ds35 {
+ label = "heartbeat";
+ gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ ds36 {
+ label = "vbus_det";
+ gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+ };
+
+ ams {
+ compatible = "iio-hwmon";
+ io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,
+ <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,
+ <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,
+ <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>,
+ <&xilinx_ams 12>, <&xilinx_ams 13>, <&xilinx_ams 14>,
+ <&xilinx_ams 15>, <&xilinx_ams 16>, <&xilinx_ams 17>,
+ <&xilinx_ams 18>, <&xilinx_ams 19>, <&xilinx_ams 20>,
+ <&xilinx_ams 21>, <&xilinx_ams 22>, <&xilinx_ams 23>,
+ <&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>,
+ <&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>;
+ };
+};
+
+&uart1 { /* MIO36/MIO37 */
+ status = "okay";
+};
+
+&qspi { /* MIO 0-5 - U143 */
+ status = "okay";
+ flash at 0 { /* MT25QU512A */
+ compatible = "mt25qu512a", "jedec,spi-nor"; /* 64MB */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <40000000>; /* 40MHz */
+ partition at 0 {
+ label = "Image Selector";
+ reg = <0x0 0x80000>; /* 512KB */
+ read-only;
+ lock;
+ };
+ partition at 80000 {
+ label = "Image Selector Golden";
+ reg = <0x80000 0x80000>; /* 512KB */
+ read-only;
+ lock;
+ };
+ partition at 100000 {
+ label = "Persistent Register";
+ reg = <0x100000 0x20000>; /* 128KB */
+ };
+ partition at 120000 {
+ label = "Persistent Register Backup";
+ reg = <0x120000 0x20000>; /* 128KB */
+ };
+ partition at 140000 {
+ label = "Open_1";
+ reg = <0x140000 0xC0000>; /* 768KB */
+ };
+ partition at 200000 {
+ label = "Image A (FSBL, PMU, ATF, U-Boot)";
+ reg = <0x200000 0xD00000>; /* 13MB */
+ };
+ partition at f00000 {
+ label = "ImgSel Image A Catch";
+ reg = <0xF00000 0x80000>; /* 512KB */
+ read-only;
+ lock;
+ };
+ partition at f80000 {
+ label = "Image B (FSBL, PMU, ATF, U-Boot)";
+ reg = <0xF80000 0xD00000>; /* 13MB */
+ };
+ partition at 1c80000 {
+ label = "ImgSel Image B Catch";
+ reg = <0x1C80000 0x80000>; /* 512KB */
+ read-only;
+ lock;
+ };
+ partition at 1d00000 {
+ label = "Open_2";
+ reg = <0x1D00000 0x100000>; /* 1MB */
+ };
+ partition at 1e00000 {
+ label = "Recovery Image";
+ reg = <0x1E00000 0x200000>; /* 2MB */
+ read-only;
+ lock;
+ };
+ partition at 2000000 {
+ label = "Recovery Image Backup";
+ reg = <0x2000000 0x200000>; /* 2MB */
+ read-only;
+ lock;
+ };
+ partition at 2200000 {
+ label = "U-Boot storage variables";
+ reg = <0x2200000 0x20000>; /* 128KB */
+ };
+ partition at 2220000 {
+ label = "U-Boot storage variables backup";
+ reg = <0x2220000 0x20000>; /* 128KB */
+ };
+ partition at 2240000 {
+ label = "SHA256";
+ reg = <0x2240000 0x10000>; /* 256B but 64KB sector */
+ read-only;
+ lock;
+ };
+ partition at 2250000 {
+ label = "User";
+ reg = <0x2250000 0x1db0000>; /* 29.5 MB */
+ };
+ };
+};
+
+&sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALBH-IT - U133A*/
+ status = "okay";
+ non-removable;
+ disable-wp;
+ bus-width = <8>;
+ xlnx,mio-bank = <0>;
+};
+
+&spi1 { /* MIO6, 9-11 */
+ status = "okay";
+ label = "TPM";
+ num-cs = <1>;
+ tpm at 0 { /* slm9670 - U144 */
+ compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
+ reg = <0>;
+ spi-max-frequency = <18500000>;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+ scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
+
+ eeprom: eeprom at 50 { /* u46 - also at address 0x58 */
+ compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */
+ reg = <0x50>;
+ /* WP pin EE_WP_EN connected to slg7x644092 at 68 */
+ };
+
+ eeprom_cc: eeprom at 51 { /* required by spec - also at address 0x59 */
+ compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */
+ reg = <0x51>;
+ };
+
+ /* da9062 at 30 - u170 - also at address 0x31 */
+ /* da9131 at 33 - u167 */
+ da9131: pmic at 33 {
+ compatible = "dlg,da9131";
+ reg = <0x33>;
+ regulators {
+ da9131_buck1: buck1 {
+ regulator-name = "da9131_buck1";
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ da9131_buck2: buck2 {
+ regulator-name = "da9131_buck2";
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+
+ /* da9130 at 32 - u166 */
+ da9130: pmic at 32 {
+ compatible = "dlg,da9130";
+ reg = <0x32>;
+ regulators {
+ da9130_buck1: buck1 {
+ regulator-name = "da9130_buck1";
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+
+ /* slg7x644091 at 70 - u168 NOT accessible due to address conflict with stdp4320 */
+ /*
+ * stdp4320 - u27 FW has below two issues to be fixed in next board revision.
+ * Device acknowledging to addresses 0x5C, 0x5D, 0x70, 0x72, 0x76.
+ * Address conflict with slg7x644091 at 70 making both the devices NOT accessible.
+ * With the FW fix, stdp4320 should respond to address 0x73 only.
+ */
+ /* slg7x644092 at 68 - u169 */
+ /* Also connected via JA1C as C23/C24 */
+};
+
+&gpio {
+ status = "okay";
+ gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */
+ "QSPI_CS_B", "SPI_CLK", "LED1", "LED2", "SPI_CS_B", /* 5 - 9 */
+ "SPI_MISO", "SPI_MOSI", "FWUEN", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */
+ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */
+ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST", "I2C1_SCL", /* 20 - 24 */
+ "I2C1_SDA", "", "", "", "", /* 25 - 29 */
+ "", "", "", "", "", /* 30 - 34 */
+ "", "", "", "", "", /* 35 - 39 */
+ "", "", "", "", "", /* 40 - 44 */
+ "", "", "", "", "", /* 45 - 49 */
+ "", "", "", "", "", /* 50 - 54 */
+ "", "", "", "", "", /* 55 - 59 */
+ "", "", "", "", "", /* 60 - 64 */
+ "", "", "", "", "", /* 65 - 69 */
+ "", "", "", "", "", /* 70 - 74 */
+ "", "", "", /* 75 - 77, MIO end and EMIO start */
+ "", "", /* 78 - 79 */
+ "", "", "", "", "", /* 80 - 84 */
+ "", "", "", "", "", /* 85 - 89 */
+ "", "", "", "", "", /* 90 - 94 */
+ "", "", "", "", "", /* 95 - 99 */
+ "", "", "", "", "", /* 100 - 104 */
+ "", "", "", "", "", /* 105 - 109 */
+ "", "", "", "", "", /* 110 - 114 */
+ "", "", "", "", "", /* 115 - 119 */
+ "", "", "", "", "", /* 120 - 124 */
+ "", "", "", "", "", /* 125 - 129 */
+ "", "", "", "", "", /* 130 - 134 */
+ "", "", "", "", "", /* 135 - 139 */
+ "", "", "", "", "", /* 140 - 144 */
+ "", "", "", "", "", /* 145 - 149 */
+ "", "", "", "", "", /* 150 - 154 */
+ "", "", "", "", "", /* 155 - 159 */
+ "", "", "", "", "", /* 160 - 164 */
+ "", "", "", "", "", /* 165 - 169 */
+ "", "", "", ""; /* 170 - 174 */
+};
+
+&xilinx_ams {
+ status = "okay";
+};
+
+&ams_ps {
+ status = "okay";
+};
+
+&ams_pl {
+ status = "okay";
+};
diff --git a/arch/arm/dts/zynqmp-smk-k26-revA-u-boot.dtsi b/arch/arm/dts/zynqmp-smk-k26-revA-u-boot.dtsi
new file mode 100644
index 000000000000..8e9106792ff9
--- /dev/null
+++ b/arch/arm/dts/zynqmp-smk-k26-revA-u-boot.dtsi
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP Z2-VSOM
+ *
+ * (C) Copyright 2020, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/* SD0 only supports 3.3V, no level shifter */
+&sdhci1 { /* FIXME - on CC - MIO 39 - 51 */
+ status = "okay";
+ no-1-8-v;
+ disable-wp;
+ broken-cd;
+ xlnx,mio-bank = <1>;
+ /* Do not run SD in HS mode from bootloader */
+ sdhci-caps-mask = <0 0x200000>;
+ sdhci-caps = <0 0>;
+ max-frequency = <19000000>;
+};
diff --git a/arch/arm/dts/zynqmp-smk-k26-revA.dts b/arch/arm/dts/zynqmp-smk-k26-revA.dts
new file mode 100644
index 000000000000..300edc880093
--- /dev/null
+++ b/arch/arm/dts/zynqmp-smk-k26-revA.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP SMK-K26 rev1/B/A
+ *
+ * (C) Copyright 2020, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+#include "zynqmp-sm-k26-revA.dts"
+
+/ {
+ model = "ZynqMP SMK-K26 Rev1/B/A";
+ compatible = "xlnx,zynqmp-smk-k26-rev1", "xlnx,zynqmp-smk-k26-revB",
+ "xlnx,zynqmp-smk-k26-revA", "xlnx,zynqmp-smk-k26",
+ "xlnx,zynqmp";
+};
+
+&sdhci0 {
+ status = "disabled";
+};
diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig
index 9414b267060f..934042172a84 100644
--- a/configs/xilinx_zynqmp_virt_defconfig
+++ b/configs/xilinx_zynqmp_virt_defconfig
@@ -68,7 +68,7 @@ CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y
CONFIG_CMD_UBI=y
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_LIST="avnet-ultra96-rev1 zynqmp-a2197-revA zynqmp-e-a2197-00-revA zynqmp-g-a2197-00-revA zynqmp-m-a2197-01-revA zynqmp-m-a2197-02-revA zynqmp-m-a2197-03-revA zynqmp-p-a2197-00-revA zynqmp-zc1232-revA zynqmp-zc1254-revA zynqmp-zc1751-xm015-dc1 zynqmp-zc1751-xm016-dc2 zynqmp-zc1751-xm017-dc3 zynqmp-zc1751-xm018-dc4 zynqmp-zc1751-xm019-dc5 zynqmp-zcu100-revC zynqmp-zcu102-rev1.1 zynqmp-zcu102-rev1.0 zynqmp-zcu102-revA zynqmp-zcu102-revB zynqmp-zcu104-revA zynqmp-zcu104-revC zynqmp-zcu106-revA zynqmp-zcu111-revA zynqmp-zcu1275-revA zynqmp-zcu1275-revB zynqmp-zcu1285-revA zynqmp-zcu208-revA zynqmp-zcu216-revA zynqmp-topic-miamimp-xilinx-xdp-v1r1"
+CONFIG_OF_LIST="avnet-ultra96-rev1 zynqmp-a2197-revA zynqmp-e-a2197-00-revA zynqmp-g-a2197-00-revA zynqmp-m-a2197-01-revA zynqmp-m-a2197-02-revA zynqmp-m-a2197-03-revA zynqmp-p-a2197-00-revA zynqmp-zc1232-revA zynqmp-zc1254-revA zynqmp-zc1751-xm015-dc1 zynqmp-zc1751-xm016-dc2 zynqmp-zc1751-xm017-dc3 zynqmp-zc1751-xm018-dc4 zynqmp-zc1751-xm019-dc5 zynqmp-zcu100-revC zynqmp-zcu102-rev1.1 zynqmp-zcu102-rev1.0 zynqmp-zcu102-revA zynqmp-zcu102-revB zynqmp-zcu104-revA zynqmp-zcu104-revC zynqmp-zcu106-revA zynqmp-zcu111-revA zynqmp-zcu1275-revA zynqmp-zcu1275-revB zynqmp-zcu1285-revA zynqmp-zcu208-revA zynqmp-zcu216-revA zynqmp-topic-miamimp-xilinx-xdp-v1r1 zynqmp-sm-k26-revA zynqmp-smk-k26-revA"
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent interrupts iommus power-domains"
CONFIG_ENV_IS_NOWHERE=y
CONFIG_ENV_IS_IN_FAT=y
--
2.31.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH 00/10] arm64: zynqmp: Add support for KRIA boards and update phy/pinctrl descs
2021-05-10 14:17 [PATCH 00/10] arm64: zynqmp: Add support for KRIA boards and update phy/pinctrl descs Michal Simek
` (9 preceding siblings ...)
2021-05-10 14:17 ` [PATCH 10/10] arm64: zynqmp: Add description for SOM/Kria boards Michal Simek
@ 2021-05-19 8:05 ` Michal Simek
10 siblings, 0 replies; 12+ messages in thread
From: Michal Simek @ 2021-05-19 8:05 UTC (permalink / raw)
To: u-boot
po 10. 5. 2021 v 16:17 odes?latel Michal Simek <michal.simek@xilinx.com> napsal:
>
> Hi,
>
> this patchset is adding support for new Xilinx SOM platform. SOM+CC.
> Also adding description for pin control and PSGTR phys with also some small
> fixes in DT.
>
> Thanks,
> Michal
>
>
> Michal Simek (6):
> arm64: zynqmp: Add missing silabs,skip-recall for si570 ref clk nodes
> arm64: zynqmp: Remove comment about clock chips
> arm64: zynqmp: Add missing mio-bank properties to sdhci
> arm64: zynqmp: Add pinctrl description
> arm64: zynqmp: Add psgtr DT descriptions
> arm64: zynqmp: Add description for SOM/Kria boards
>
> Raviteja Narayanam (1):
> arm64: zynqmp: Add 'i2c-mux-idle-disconnect' property
>
> Saeed Nowshadi (2):
> arm64: zynqmp: Add 'silabs,skip-recall' to DDR DIMM si570 clk node
> arm64: zynqmp: Add label to all GPIO lines for VCK190 SC
>
> T Karthik Reddy (1):
> arm64: zynqmp: Add zynqmp firmware specific DT nodes
>
> arch/arm/dts/Makefile | 4 +
> arch/arm/dts/zynqmp-e-a2197-00-revA.dts | 20 +-
> arch/arm/dts/zynqmp-m-a2197-01-revA.dts | 3 +-
> arch/arm/dts/zynqmp-m-a2197-02-revA.dts | 3 +-
> arch/arm/dts/zynqmp-m-a2197-03-revA.dts | 3 +-
> arch/arm/dts/zynqmp-mini-emmc0.dts | 40 ++
> arch/arm/dts/zynqmp-mini-emmc1.dts | 40 ++
> arch/arm/dts/zynqmp-p-a2197-00-revA.dts | 23 ++
> arch/arm/dts/zynqmp-sck-kv-g-revA.dts | 373 +++++++++++++++++++
> arch/arm/dts/zynqmp-sck-kv-g-revB.dts | 353 ++++++++++++++++++
> arch/arm/dts/zynqmp-sm-k26-revA-u-boot.dtsi | 21 ++
> arch/arm/dts/zynqmp-sm-k26-revA.dts | 316 ++++++++++++++++
> arch/arm/dts/zynqmp-smk-k26-revA-u-boot.dtsi | 21 ++
> arch/arm/dts/zynqmp-smk-k26-revA.dts | 21 ++
> arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 260 +++++++++++++
> arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 306 +++++++++++++++
> arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts | 330 ++++++++++++++++
> arch/arm/dts/zynqmp-zcu100-revC.dts | 242 +++++++++++-
> arch/arm/dts/zynqmp-zcu102-revA.dts | 290 ++++++++++++++
> arch/arm/dts/zynqmp-zcu104-revA.dts | 218 +++++++++++
> arch/arm/dts/zynqmp-zcu104-revC.dts | 218 +++++++++++
> arch/arm/dts/zynqmp-zcu106-revA.dts | 290 ++++++++++++++
> arch/arm/dts/zynqmp-zcu111-revA.dts | 234 +++++++++++-
> arch/arm/dts/zynqmp-zcu208-revA.dts | 83 ++++-
> arch/arm/dts/zynqmp-zcu216-revA.dts | 83 ++++-
> configs/xilinx_zynqmp_virt_defconfig | 2 +-
> include/dt-bindings/pinctrl/pinctrl-zynqmp.h | 19 +
> 27 files changed, 3792 insertions(+), 24 deletions(-)
> create mode 100644 arch/arm/dts/zynqmp-sck-kv-g-revA.dts
> create mode 100644 arch/arm/dts/zynqmp-sck-kv-g-revB.dts
> create mode 100644 arch/arm/dts/zynqmp-sm-k26-revA-u-boot.dtsi
> create mode 100644 arch/arm/dts/zynqmp-sm-k26-revA.dts
> create mode 100644 arch/arm/dts/zynqmp-smk-k26-revA-u-boot.dtsi
> create mode 100644 arch/arm/dts/zynqmp-smk-k26-revA.dts
> create mode 100644 include/dt-bindings/pinctrl/pinctrl-zynqmp.h
>
> --
> 2.31.1
>
Applied.
M
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
^ permalink raw reply [flat|nested] 12+ messages in thread