[PATCH 0/2] nand: zynq: Sync up with Linux

[PATCH 0/2] nand: zynq: Sync up with Linux

[Michal Simek]

Hi,

recently PL35x driver was upstreamed and there were some changes in DT
binding which should be reflected here too. That's why sending these two
patches to update the driver and the way how nand and nor memories are
described in DT.

Thanks,
Michal


Michael Walle (1):
  ARM: dts: zynq: add NAND flash controller node

Michal Simek (1):
  mtd: nand: Update driver to match new DT binding

 arch/arm/dts/bitmain-antminer-s9.dts |  2 +-
 arch/arm/dts/zynq-7000.dtsi          | 57 +++++++++++++++-------------
 arch/arm/dts/zynq-zc770-xm011.dts    |  2 +-
 drivers/mtd/nand/raw/zynq_nand.c     |  9 +++--
 4 files changed, 38 insertions(+), 32 deletions(-)

-- 
2.35.1

[PATCH 1/2] mtd: nand: Update driver to match new DT binding

[Michal Simek]

New binding changed node name from flash@e1000000 to nand-controller@0,0
which should be reflected in the driver. Both names are supported for
backward compatibility.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

 drivers/mtd/nand/raw/zynq_nand.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/mtd/nand/raw/zynq_nand.c b/drivers/mtd/nand/raw/zynq_nand.c
index d79252837065..10e9cd18b077 100644
--- a/drivers/mtd/nand/raw/zynq_nand.c
+++ b/drivers/mtd/nand/raw/zynq_nand.c
@@ -1086,10 +1086,13 @@ static int zynq_nand_probe(struct udevice *dev)
 	int is_16bit_bw;
 
 	smc->reg = (struct zynq_nand_smc_regs *)dev_read_addr(dev);
-	of_nand = dev_read_subnode(dev, "flash@e1000000");
+	of_nand = dev_read_subnode(dev, "nand-controller@0,0");
 	if (!ofnode_valid(of_nand)) {
-		printf("Failed to find nand node in dt\n");
-		return -ENODEV;
+		of_nand = dev_read_subnode(dev, "flash@e1000000");
+		if (!ofnode_valid(of_nand)) {
+			printf("Failed to find nand node in dt\n");
+			return -ENODEV;
+		}
 	}
 
 	if (!ofnode_is_available(of_nand)) {
-- 
2.35.1

[PATCH 2/2] ARM: dts: zynq: add NAND flash controller node

[Michal Simek]

From: Michael Walle <michael@walle.cc>

Recently, a driver for the ARM Primecell PL35x static memory controller
(including NAND controller) was added in linux. Add the corresponding
device tree node.

Also update cfi-flash registers and location in DT.

Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/20210616155437.27378-3-michael@walle.cc
---

 arch/arm/dts/bitmain-antminer-s9.dts |  2 +-
 arch/arm/dts/zynq-7000.dtsi          | 57 +++++++++++++++-------------
 arch/arm/dts/zynq-zc770-xm011.dts    |  2 +-
 3 files changed, 32 insertions(+), 29 deletions(-)

diff --git a/arch/arm/dts/bitmain-antminer-s9.dts b/arch/arm/dts/bitmain-antminer-s9.dts
index 0694350555f5..408862bef042 100644
--- a/arch/arm/dts/bitmain-antminer-s9.dts
+++ b/arch/arm/dts/bitmain-antminer-s9.dts
@@ -50,7 +50,7 @@
 	ps-clk-frequency = <33333333>;
 };
 
-&nand0 {
+&nfc0 {
 	status = "okay";
 };
 
diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index 4dda753671c2..9495911397eb 100644
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -246,33 +246,6 @@
 			#size-cells = <0>;
 		};
 
-		smcc: memory-controller@e000e000 {
-			#address-cells = <1>;
-			#size-cells = <1>;
-			status = "disabled";
-			clock-names = "memclk", "apb_pclk";
-			clocks = <&clkc 11>, <&clkc 44>;
-			compatible = "arm,pl353-smc-r2p1", "arm,primecell";
-			interrupt-parent = <&intc>;
-			interrupts = <0 18 4>;
-			ranges ;
-			reg = <0xe000e000 0x1000>;
-			nand0: flash@e1000000 {
-				status = "disabled";
-				compatible = "arm,pl353-nand-r2p1";
-				reg = <0xe1000000 0x1000000>;
-				#address-cells = <1>;
-				#size-cells = <1>;
-			};
-			nor0: flash@e2000000 {
-				status = "disabled";
-				compatible = "cfi-flash";
-				reg = <0xe2000000 0x2000000>;
-				#address-cells = <1>;
-				#size-cells = <1>;
-			};
-		};
-
 		gem0: ethernet@e000b000 {
 			compatible = "cdns,zynq-gem", "cdns,gem";
 			reg = <0xe000b000 0x1000>;
@@ -295,6 +268,36 @@
 			#size-cells = <0>;
 		};
 
+		smcc: memory-controller@e000e000 {
+			compatible = "arm,pl353-smc-r2p1", "arm,primecell";
+			reg = <0xe000e000 0x0001000>;
+			status = "disabled";
+			clock-names = "memclk", "apb_pclk";
+			clocks = <&clkc 11>, <&clkc 44>;
+			ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */
+				  0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */
+				  0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */
+			#address-cells = <2>;
+			#size-cells = <1>;
+			interrupt-parent = <&intc>;
+			interrupts = <0 18 4>;
+
+			nfc0: nand-controller@0,0 {
+				compatible = "arm,pl353-nand-r2p1";
+				reg = <0 0 0x1000000>;
+				status = "disabled";
+				#address-cells = <1>;
+				#size-cells = <1>;
+			};
+			nor0: flash@1,0 {
+				status = "disabled";
+				compatible = "cfi-flash";
+				reg = <1 0 0x2000000>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+			};
+		};
+
 		sdhci0: mmc@e0100000 {
 			compatible = "arasan,sdhci-8.9a";
 			status = "disabled";
diff --git a/arch/arm/dts/zynq-zc770-xm011.dts b/arch/arm/dts/zynq-zc770-xm011.dts
index b6e3e255d731..0ef2ae1744f2 100644
--- a/arch/arm/dts/zynq-zc770-xm011.dts
+++ b/arch/arm/dts/zynq-zc770-xm011.dts
@@ -47,7 +47,7 @@
 	};
 };
 
-&nand0 {
+&nfc0 {
 	status = "okay";
 };
 
-- 
2.35.1