[PATCH 0/6] arm64: zynqmp: Update SOM boards

[PATCH 0/6] arm64: zynqmp: Update SOM boards

[Michal Simek]

Hi,

kv-g boards have been moved to new model where u-boot configures a lot of
things at run time which requires updates in DTs especially in connection
to enabling clocks for these platforms.
There are also small adjustment to match the latest state.

Thanks,
Michal


Michal Simek (6):
  arm64: zynqmp: Move usb hub from i2c to usb node
  arm64: zynqmp: Setup clock for DP and DPDMA
  arm64: zynqmp: Use assigned-clock-rates for setting up clock in SOM
  arm64: zynqmp: Switch to ethernet-phy-id in kv260
  arm64: zynqmp: Enable DP driver for SOMs
  arm64: zynqmp: Fix level of gpio reset for usb on kv260 boards

 arch/arm/dts/zynqmp-clk-ccf.dtsi      |  8 ++++++++
 arch/arm/dts/zynqmp-sck-kv-g-revA.dts | 12 +++++++++---
 arch/arm/dts/zynqmp-sck-kv-g-revB.dts | 26 ++++++++++++++++++--------
 arch/arm/dts/zynqmp-sm-k26-revA.dts   |  5 +++++
 4 files changed, 40 insertions(+), 11 deletions(-)

-- 
2.35.1

[PATCH 1/6] arm64: zynqmp: Move usb hub from i2c to usb node

[Michal Simek]

Based on upstream discussion based on link below usb hub should be placed
to usb node directly as child node. Based on this Linux driver was updated
and the same change should be also reflected in kv260 board.

Link: https://lore.kernel.org/all/CAL_JsqJZBbu+UXqUNdZwg-uv0PAsNg55026PTwhKr5wQtxCjVQ@mail.gmail.com/
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

 arch/arm/dts/zynqmp-sck-kv-g-revB.dts | 13 ++++++++-----
 1 file changed, 8 insertions(+), 5 deletions(-)

diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
index df054e152a77..01b14ebcb609 100644
--- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
+++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
@@ -36,11 +36,7 @@
 		label = "ina260-u14";
 		reg = <0x40>;
 	};
-	usbhub: usb5744@2d { /* u43 */
-		compatible = "microchip,usb5744";
-		reg = <0x2d>;
-		reset-gpios = <&gpio 44 GPIO_ACTIVE_HIGH>;
-	};
+	/* u43 - 0x2d - USB hub */
 	/* u27 - 0xe0 - STDP4320 DP/HDMI splitter */
 };
 
@@ -111,6 +107,13 @@
 	pinctrl-0 = <&pinctrl_usb0_default>;
 	phy-names = "usb3-phy";
 	phys = <&psgtr 2 PHY_TYPE_USB3 0 1>;
+
+	usb5744: usb-hub { /* u43 */
+		status = "okay";
+		compatible = "microchip,usb5744";
+		i2c-bus = <&i2c1>;
+		reset-gpios = <&gpio 44 GPIO_ACTIVE_HIGH>;
+	};
 };
 
 &dwc3_0 {
-- 
2.35.1

[PATCH 2/6] arm64: zynqmp: Setup clock for DP and DPDMA

[Michal Simek]

Clocks are coming from shared HW design where these frequencies should be
aligned with PLL setup.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

 arch/arm/dts/zynqmp-clk-ccf.dtsi      | 4 ++++
 arch/arm/dts/zynqmp-sck-kv-g-revA.dts | 2 ++
 arch/arm/dts/zynqmp-sck-kv-g-revB.dts | 2 ++
 3 files changed, 8 insertions(+)

diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi
index 664e65896d7e..86b99070c4a8 100644
--- a/arch/arm/dts/zynqmp-clk-ccf.dtsi
+++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi
@@ -279,10 +279,14 @@
 
 &zynqmp_dpdma {
 	clocks = <&zynqmp_clk DPDMA_REF>;
+	assigned-clocks = <&zynqmp_clk DPDMA_REF>; /* apll */
 };
 
 &zynqmp_dpsub {
 	clocks = <&zynqmp_clk TOPSW_LSBUS>,
 		 <&zynqmp_clk DP_AUDIO_REF>,
 		 <&zynqmp_clk DP_VIDEO_REF>;
+	assigned-clocks = <&zynqmp_clk DP_STC_REF>,
+			  <&zynqmp_clk DP_AUDIO_REF>,
+			  <&zynqmp_clk DP_VIDEO_REF>;  /* rpll, rpll, vpll */
 };
diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts
index 22602d8c33f8..34fb592d4fa5 100644
--- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts
+++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts
@@ -115,10 +115,12 @@
 	status = "disabled";
 	phy-names = "dp-phy0", "dp-phy1";
 	phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
+	assigned-clock-rates = <27000000>, <25000000>, <300000000>;
 };
 
 &zynqmp_dpdma {
 	status = "okay";
+	assigned-clock-rates = <600000000>;
 };
 
 &usb0 {
diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
index 01b14ebcb609..35247b0bbd2e 100644
--- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
+++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
@@ -95,10 +95,12 @@
 	status = "disabled";
 	phy-names = "dp-phy0", "dp-phy1";
 	phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
+	assigned-clock-rates = <27000000>, <25000000>, <300000000>;
 };
 
 &zynqmp_dpdma {
 	status = "okay";
+	assigned-clock-rates = <600000000>;
 };
 
 &usb0 {
-- 
2.35.1

[PATCH 3/6] arm64: zynqmp: Use assigned-clock-rates for setting up clock in SOM

[Michal Simek]

With limited low level configuration done via psu-init only IPs connected
on SOM are initialized and configured. All IPs connected to carrier card
are not initialized. There is a need to do proper reset, pin configuration
and also clock setting.
The patch targets the last part which is setting up proper clock for USBs
and SDs.
Also setup proper bus width for SD cards.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
---

 arch/arm/dts/zynqmp-clk-ccf.dtsi      | 4 ++++
 arch/arm/dts/zynqmp-sck-kv-g-revA.dts | 2 ++
 arch/arm/dts/zynqmp-sck-kv-g-revB.dts | 3 +++
 arch/arm/dts/zynqmp-sm-k26-revA.dts   | 1 +
 4 files changed, 10 insertions(+)

diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi
index 86b99070c4a8..7b09d7515186 100644
--- a/arch/arm/dts/zynqmp-clk-ccf.dtsi
+++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi
@@ -215,10 +215,12 @@
 
 &sdhci0 {
 	clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>;
+	assigned-clocks = <&zynqmp_clk SDIO0_REF>;
 };
 
 &sdhci1 {
 	clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>;
+	assigned-clocks = <&zynqmp_clk SDIO1_REF>;
 };
 
 &spi0 {
@@ -255,10 +257,12 @@
 
 &usb0 {
 	clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
+	assigned-clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
 };
 
 &usb1 {
 	clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
+	assigned-clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
 };
 
 &watchdog0 {
diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts
index 34fb592d4fa5..f58ad69be311 100644
--- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts
+++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts
@@ -154,6 +154,8 @@
 	no-1-8-v;
 	disable-wp;
 	xlnx,mio-bank = <1>;
+	assigned-clock-rates = <187498123>;
+	bus-width = <8>;
 };
 
 &gem3 { /* required by spec */
diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
index 35247b0bbd2e..7236e03a5a74 100644
--- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
+++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
@@ -109,6 +109,7 @@
 	pinctrl-0 = <&pinctrl_usb0_default>;
 	phy-names = "usb3-phy";
 	phys = <&psgtr 2 PHY_TYPE_USB3 0 1>;
+	assigned-clock-rates = <250000000>, <20000000>;
 
 	usb5744: usb-hub { /* u43 */
 		status = "okay";
@@ -140,6 +141,8 @@
 	clk-phase-sd-hs = <126>, <60>;
 	clk-phase-uhs-sdr25 = <120>, <60>;
 	clk-phase-uhs-ddr50 = <126>, <48>;
+	assigned-clock-rates = <187498123>;
+	bus-width = <8>;
 };
 
 &gem3 { /* required by spec */
diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts
index 5f55df28f331..e9baf4cb4148 100644
--- a/arch/arm/dts/zynqmp-sm-k26-revA.dts
+++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts
@@ -189,6 +189,7 @@
 	disable-wp;
 	bus-width = <8>;
 	xlnx,mio-bank = <0>;
+	assigned-clock-rates = <187498123>;
 };
 
 &spi1 { /* MIO6, 9-11 */
-- 
2.35.1

[PATCH 4/6] arm64: zynqmp: Switch to ethernet-phy-id in kv260

[Michal Simek]

Use ethernet-phy-id compatible string to properly describe phy reset on
kv260 boards. Previous description wasn't correct because reset was done
for mdio bus to operate and it was in this case used for different purpose
which was eth phy reset. With ethernet-phy-id phy reset happens only for
the phy via phy framework.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

 arch/arm/dts/zynqmp-sck-kv-g-revA.dts | 6 ++++--
 arch/arm/dts/zynqmp-sck-kv-g-revB.dts | 6 ++++--
 2 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts
index f58ad69be311..9445dace7393 100644
--- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts
+++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts
@@ -168,16 +168,18 @@
 	mdio: mdio {
 		#address-cells = <1>;
 		#size-cells = <0>;
-		reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
-		reset-delay-us = <2>;
 
 		phy0: ethernet-phy@1 {
 			#phy-cells = <1>;
 			reg = <1>;
+			compatible = "ethernet-phy-id2000.a231";
 			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
 			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
 			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
 			ti,dp83867-rxctrl-strap-quirk;
+			reset-assert-us = <100>;
+			reset-deassert-us = <280>;
+			reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
 		};
 	};
 };
diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
index 7236e03a5a74..6ea950a13f45 100644
--- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
+++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
@@ -155,16 +155,18 @@
 	mdio: mdio {
 		#address-cells = <1>;
 		#size-cells = <0>;
-		reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
-		reset-delay-us = <2>;
 
 		phy0: ethernet-phy@1 {
 			#phy-cells = <1>;
 			reg = <1>;
+			compatible = "ethernet-phy-id2000.a231";
 			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
 			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
 			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
 			ti,dp83867-rxctrl-strap-quirk;
+			reset-assert-us = <100>;
+			reset-deassert-us = <280>;
+			reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
 		};
 	};
 };
-- 
2.35.1

[PATCH 5/6] arm64: zynqmp: Enable DP driver for SOMs

[Michal Simek]

The main reason is to send pmufw cfg overlay from U-Boot to PMUFW to enable
access to DP. Overlay is sent when cls command is called and for that IP
has to be enabled in carrier cards.
And IP needs to be also enabled in SOM dt because with DTB reselection new
DT is not parsed in pre reloc U-Boot instance. It is called from board_f
via embedded_dtb_select(). That's why bind function is not able to allocate
memory and it ends up with error:
"Video device 'display@fd4a0000' cannot allocate frame buffer memory
-ensure the device is set up before relocation"

To avoid this situation DP is placed also to SOM where bind function is
called and frame buffer memory is allocated and just reused after DTB
reselection. Result is the same. There could be a problem in Linux with
different DP configurations but that's need to be solved there because
console should be on from u-boot already.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

 arch/arm/dts/zynqmp-sck-kv-g-revB.dts | 2 +-
 arch/arm/dts/zynqmp-sm-k26-revA.dts   | 4 ++++
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
index 6ea950a13f45..28a3f3c21992 100644
--- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
+++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
@@ -92,7 +92,7 @@
 };
 
 &zynqmp_dpsub {
-	status = "disabled";
+	status = "okay";
 	phy-names = "dp-phy0", "dp-phy1";
 	phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
 	assigned-clock-rates = <27000000>, <25000000>, <300000000>;
diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts
index e9baf4cb4148..d242f8712b84 100644
--- a/arch/arm/dts/zynqmp-sm-k26-revA.dts
+++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts
@@ -317,3 +317,7 @@
 &ams_pl {
 	status = "okay";
 };
+
+&zynqmp_dpsub {
+	status = "okay";
+};
-- 
2.35.1

[PATCH 6/6] arm64: zynqmp: Fix level of gpio reset for usb on kv260 boards

[Michal Simek]

Active level is low that's why it should be fixed.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

 arch/arm/dts/zynqmp-sck-kv-g-revA.dts | 2 +-
 arch/arm/dts/zynqmp-sck-kv-g-revB.dts | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts
index 9445dace7393..85994bef7cc0 100644
--- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts
+++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts
@@ -131,7 +131,7 @@
 	phys = <&psgtr 2 PHY_TYPE_USB3 0 1>;
 	usbhub: usb5744 { /* u43 */
 		compatible = "microchip,usb5744";
-		reset-gpios = <&gpio 44 GPIO_ACTIVE_HIGH>;
+		reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
 	};
 };
 
diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
index 28a3f3c21992..b81c2e6b7543 100644
--- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
+++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
@@ -115,7 +115,7 @@
 		status = "okay";
 		compatible = "microchip,usb5744";
 		i2c-bus = <&i2c1>;
-		reset-gpios = <&gpio 44 GPIO_ACTIVE_HIGH>;
+		reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
 	};
 };
 
-- 
2.35.1

Re: [PATCH 0/6] arm64: zynqmp: Update SOM boards

[Michal Simek]

st 23. 2. 2022 v 16:17 odesílatel Michal Simek <michal.simek@xilinx.com> napsal:
>
> Hi,
>
> kv-g boards have been moved to new model where u-boot configures a lot of
> things at run time which requires updates in DTs especially in connection
> to enabling clocks for these platforms.
> There are also small adjustment to match the latest state.
>
> Thanks,
> Michal
>
>
> Michal Simek (6):
>   arm64: zynqmp: Move usb hub from i2c to usb node
>   arm64: zynqmp: Setup clock for DP and DPDMA
>   arm64: zynqmp: Use assigned-clock-rates for setting up clock in SOM
>   arm64: zynqmp: Switch to ethernet-phy-id in kv260
>   arm64: zynqmp: Enable DP driver for SOMs
>   arm64: zynqmp: Fix level of gpio reset for usb on kv260 boards
>
>  arch/arm/dts/zynqmp-clk-ccf.dtsi      |  8 ++++++++
>  arch/arm/dts/zynqmp-sck-kv-g-revA.dts | 12 +++++++++---
>  arch/arm/dts/zynqmp-sck-kv-g-revB.dts | 26 ++++++++++++++++++--------
>  arch/arm/dts/zynqmp-sm-k26-revA.dts   |  5 +++++
>  4 files changed, 40 insertions(+), 11 deletions(-)
>
> --
> 2.35.1
>

Applied.
M

-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs