* [PATCH 01/11] arm64: zynqmp: Add support for KD240 Kria SOM CC
2023-09-27 9:53 [PATCH 00/11] xilinx: add missing boards/SC descriptions Michal Simek
@ 2023-09-27 9:53 ` Michal Simek
2023-09-27 9:53 ` [PATCH 02/11] arm64: zynqmp: Remove xlnx,fclk nodes Michal Simek
` (10 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Michal Simek @ 2023-09-27 9:53 UTC (permalink / raw)
To: u-boot, git
Add support for KD240 Kria SOM CC. It is pretty much subset of KR260 board
from PS perspective.
Signed-off-by: Michal Simek <michal.simek@amd.com>
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/zynqmp-sck-kd-g-revA.dtso | 353 +++++++++++++++++++++++++
2 files changed, 354 insertions(+)
create mode 100644 arch/arm/dts/zynqmp-sck-kd-g-revA.dtso
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index bde2176ec7f6..e42261233758 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -409,6 +409,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
zynqmp-smk-k24-revA.dtb \
zynqmp-sm-k26-revA.dtb \
zynqmp-smk-k26-revA.dtb \
+ zynqmp-sck-kd-g-revA.dtbo \
zynqmp-sck-kr-g-revA.dtbo \
zynqmp-sck-kr-g-revB.dtbo \
zynqmp-sck-kv-g-revA.dtbo \
diff --git a/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso
new file mode 100644
index 000000000000..5a5c1efd6b96
--- /dev/null
+++ b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso
@@ -0,0 +1,353 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for KD240 revA Carrier Card
+ *
+ * Copyright (C) 2021 - 2022, Xilinx, Inc.
+ * Copyright (C) 2022 - 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+ compatible = "xlnx,zynqmp-sk-kd240-rev1",
+ "xlnx,zynqmp-sk-kd240-revB",
+ "xlnx,zynqmp-sk-kd240-revA",
+ "xlnx,zynqmp-sk-kd240", "xlnx,zynqmp";
+ model = "ZynqMP KD240 revA/B/1";
+
+ ina260-u3 {
+ compatible = "iio-hwmon";
+ io-channels = <&u3 0>, <&u3 1>, <&u3 2>;
+ };
+
+ clk_26: clock2 { /* u17 - USB */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ };
+};
+
+&can0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can0_default>;
+};
+
+&i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+
+ u3: ina260@40 { /* u3 */
+ compatible = "ti,ina260";
+ #io-channel-cells = <1>;
+ label = "ina260-u14";
+ reg = <0x40>;
+ };
+
+ slg7xl45106: gpio@11 { /* u13 - reset logic */
+ compatible = "dlg,slg7xl45106";
+ reg = <0x11>;
+ label = "resetchip";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names = "USB0_PHY_RESET_B", "",
+ "SD_RESET_B", "USB0_HUB_RESET_B",
+ "", "PS_GEM0_RESET_B",
+ "", "";
+ };
+
+ /* usb5744@2d */
+};
+
+/* USB 3.0 */
+&psgtr {
+ status = "okay";
+ /* usb */
+ clocks = <&clk_26>;
+ clock-names = "ref2";
+};
+
+&usb0 { /* mio52 - mio63 */
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0_default>;
+ phy-names = "usb3-phy";
+ phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
+ reset-gpios = <&slg7xl45106 0 GPIO_ACTIVE_LOW>;
+ assigned-clock-rates = <250000000>, <20000000>;
+
+ usbhub0: usb-hub { /* u36 */
+ i2c-bus = <&i2c1>;
+ compatible = "microchip,usb5744";
+ reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>;
+ };
+
+ usb2244: usb-sd { /* u41 */
+ compatible = "microchip,usb2244";
+ reset-gpios = <&slg7xl45106 2 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&dwc3_0 {
+ status = "okay";
+ dr_mode = "host";
+ snps,usb3_lpm_capable;
+ maximum-speed = "super-speed";
+};
+
+&gem1 { /* mdio mio50/51 */
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gem1_default>;
+ assigned-clock-rates = <250000000>;
+
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy0: ethernet-phy@8 { /* Adin u31 */
+ reg = <8>;
+ adi,rx-internal-delay-ps = <2000>;
+ adi,tx-internal-delay-ps = <2000>;
+ adi,fifo-depth-bits = <8>;
+ reset-assert-us = <10>;
+ reset-deassert-us = <5000>;
+ reset-gpios = <&gpio 77 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+/* 2 more ethernet phys u32@2 and u34@3 */
+
+&pinctrl0 { /* required by spec */
+ status = "okay";
+
+ pinctrl_can0_default: can0-default {
+ mux {
+ function = "can0";
+ groups = "can0_16_grp";
+ };
+
+ conf {
+ groups = "can0_16_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO66";
+ bias-pull-up;
+ };
+
+ conf-tx {
+ pins = "MIO67";
+ bias-pull-up;
+ drive-strength = <4>;
+ };
+ };
+
+ pinctrl_uart0_default: uart0-default {
+ conf {
+ groups = "uart0_17_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ drive-strength = <12>;
+ };
+
+ conf-rx {
+ pins = "MIO70";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO71";
+ bias-disable;
+ };
+
+ mux {
+ groups = "uart0_17_grp";
+ function = "uart0";
+ };
+ };
+
+ pinctrl_uart1_default: uart1-default {
+ conf {
+ groups = "uart1_9_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ drive-strength = <12>;
+ };
+
+ conf-rx {
+ pins = "MIO37";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO36";
+ bias-disable;
+ output-enable;
+ };
+
+ mux {
+ groups = "uart1_9_grp";
+ function = "uart1";
+ };
+ };
+
+ pinctrl_i2c1_default: i2c1-default {
+ conf {
+ groups = "i2c1_6_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux {
+ groups = "i2c1_6_grp";
+ function = "i2c1";
+ };
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpio {
+ conf {
+ groups = "gpio0_24_grp", "gpio0_25_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux {
+ groups = "gpio0_24_grp", "gpio0_25_grp";
+ function = "gpio0";
+ };
+ };
+
+ pinctrl_gem1_default: gem1-default {
+ conf {
+ groups = "ethernet1_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO45", "MIO46", "MIO47", "MIO48";
+ bias-disable;
+ low-power-disable;
+ };
+
+ conf-bootstrap {
+ pins = "MIO44", "MIO49";
+ bias-disable;
+ output-enable;
+ low-power-disable;
+ };
+
+ conf-tx {
+ pins = "MIO38", "MIO39", "MIO40",
+ "MIO41", "MIO42", "MIO43";
+ bias-disable;
+ output-enable;
+ low-power-enable;
+ };
+
+ conf-mdio {
+ groups = "mdio1_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ output-enable;
+ };
+
+ mux-mdio {
+ function = "mdio1";
+ groups = "mdio1_0_grp";
+ };
+
+ mux {
+ function = "ethernet1";
+ groups = "ethernet1_0_grp";
+ };
+ };
+
+ pinctrl_usb0_default: usb0-default {
+ conf {
+ groups = "usb0_0_grp";
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO52", "MIO53", "MIO55";
+ bias-high-impedance;
+ drive-strength = <12>;
+ slew-rate = <SLEW_RATE_FAST>;
+ };
+
+ conf-tx {
+ pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
+ "MIO60", "MIO61", "MIO62", "MIO63";
+ bias-disable;
+ output-enable;
+ drive-strength = <4>;
+ slew-rate = <SLEW_RATE_SLOW>;
+ };
+
+ mux {
+ groups = "usb0_0_grp";
+ function = "usb0";
+ };
+ };
+
+ pinctrl_usb1_default: usb1-default {
+ conf {
+ groups = "usb1_0_grp";
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO64", "MIO65", "MIO67";
+ bias-high-impedance;
+ drive-strength = <12>;
+ slew-rate = <SLEW_RATE_FAST>;
+ };
+
+ conf-tx {
+ pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71",
+ "MIO72", "MIO73", "MIO74", "MIO75";
+ bias-disable;
+ output-enable;
+ drive-strength = <4>;
+ slew-rate = <SLEW_RATE_SLOW>;
+ };
+
+ mux {
+ groups = "usb1_0_grp";
+ function = "usb1";
+ };
+ };
+};
+
+&uart0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0_default>;
+ assigned-clock-rates = <100000000>;
+};
+
+&uart1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_default>;
+};
--
2.36.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 02/11] arm64: zynqmp: Remove xlnx,fclk nodes
2023-09-27 9:53 [PATCH 00/11] xilinx: add missing boards/SC descriptions Michal Simek
2023-09-27 9:53 ` [PATCH 01/11] arm64: zynqmp: Add support for KD240 Kria SOM CC Michal Simek
@ 2023-09-27 9:53 ` Michal Simek
2023-09-27 9:53 ` [PATCH 03/11] arm64: zynqmp: Add support for vck190 revB system controller Michal Simek
` (9 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Michal Simek @ 2023-09-27 9:53 UTC (permalink / raw)
To: u-boot, git
xlnx,fclk nodes are not described in dtschema that's why remove them.
Signed-off-by: Michal Simek <michal.simek@amd.com>
---
arch/arm/dts/zynqmp-clk-ccf.dtsi | 18 ------------------
1 file changed, 18 deletions(-)
diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi
index 4044b62d27a2..5f1b0b23c124 100644
--- a/arch/arm/dts/zynqmp-clk-ccf.dtsi
+++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi
@@ -16,24 +16,6 @@
clocks = <&zynqmp_clk PL0_REF>;
};
- fclk1: fclk1 {
- status = "okay";
- compatible = "xlnx,fclk";
- clocks = <&zynqmp_clk PL1_REF>;
- };
-
- fclk2: fclk2 {
- status = "okay";
- compatible = "xlnx,fclk";
- clocks = <&zynqmp_clk PL2_REF>;
- };
-
- fclk3: fclk3 {
- status = "okay";
- compatible = "xlnx,fclk";
- clocks = <&zynqmp_clk PL3_REF>;
- };
-
pss_ref_clk: pss_ref_clk {
bootph-all;
compatible = "fixed-clock";
--
2.36.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 03/11] arm64: zynqmp: Add support for vck190 revB system controller
2023-09-27 9:53 [PATCH 00/11] xilinx: add missing boards/SC descriptions Michal Simek
2023-09-27 9:53 ` [PATCH 01/11] arm64: zynqmp: Add support for KD240 Kria SOM CC Michal Simek
2023-09-27 9:53 ` [PATCH 02/11] arm64: zynqmp: Remove xlnx,fclk nodes Michal Simek
@ 2023-09-27 9:53 ` Michal Simek
2023-09-27 9:53 ` [PATCH 04/11] arm64: zynqmp: Add x-prc-01/02/03/04/05 revA support from SC Michal Simek
` (8 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Michal Simek @ 2023-09-27 9:53 UTC (permalink / raw)
To: u-boot, git
There are some changes between revA and revB boards. u39 8T49N240 was
removed and also three ina226 at 42/43/44 addresses (u178/u180/u182).
Signed-off-by: Michal Simek <michal.simek@amd.com>
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/zynqmp-e-a2197-00-revB.dts | 34 +++++++++++++++++++++++++
configs/xilinx_zynqmp_virt_defconfig | 2 +-
3 files changed, 36 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/zynqmp-e-a2197-00-revB.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index e42261233758..e060081cdea5 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -395,6 +395,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
zynqmp-a2197-revA.dtb \
zynqmp-dlc21-revA.dtb \
zynqmp-e-a2197-00-revA.dtb \
+ zynqmp-e-a2197-00-revB.dtb \
zynqmp-g-a2197-00-revA.dtb \
zynqmp-m-a2197-01-revA.dtb \
zynqmp-m-a2197-02-revA.dtb \
diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revB.dts b/arch/arm/dts/zynqmp-e-a2197-00-revB.dts
new file mode 100644
index 000000000000..8310df9ed369
--- /dev/null
+++ b/arch/arm/dts/zynqmp-e-a2197-00-revB.dts
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx Versal a2197 RevB System Controller
+ *
+ * (C) Copyright 2019 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+#include "zynqmp-e-a2197-00-revA.dts"
+
+/ {
+ model = "Versal System Controller on a2197 Eval board RevB"; /* VCK190/VMK180 */
+ compatible = "xlnx,zynqmp-e-a2197-00-revB", "xlnx,zynqmp-a2197-revB",
+ "xlnx,zynqmp-a2197", "xlnx,zynqmp";
+
+ /delete-node/ ina226-vcco-500;
+ /delete-node/ ina226-vcco-501;
+ /delete-node/ ina226-vcco-502;
+};
+
+&i2c0 {
+ i2c-mux@74 { /* u33 */
+ i2c@2 { /* PCIE_CLK */
+ /delete-node/ clock-generator@6c;
+ };
+ i2c@3 { /* PMBUS2_INA226 */
+ /delete-node/ ina226@42;
+ /delete-node/ ina226@43;
+ /delete-node/ ina226@44;
+ };
+ };
+};
diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig
index 30e420951dad..d72fac40a516 100644
--- a/configs/xilinx_zynqmp_virt_defconfig
+++ b/configs/xilinx_zynqmp_virt_defconfig
@@ -103,7 +103,7 @@ CONFIG_CMD_UBI=y
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_BOARD=y
-CONFIG_OF_LIST="avnet-ultra96-rev1 zynqmp-a2197-revA zynqmp-e-a2197-00-revA zynqmp-g-a2197-00-revA zynqmp-m-a2197-01-revA zynqmp-m-a2197-02-revA zynqmp-m-a2197-03-revA zynqmp-p-a2197-00-revA zynqmp-zc1232-revA zynqmp-zc1254-revA zynqmp-zc1751-xm015-dc1 zynqmp-zc1751-xm016-dc2 zynqmp-zc1751-xm017-dc3 zynqmp-zc1751-xm018-dc4 zynqmp-zc1751-xm019-dc5 zynqmp-zcu100-revC zynqmp-zcu102-rev1.1 zynqmp-zcu102-rev1.0 zynqmp-zcu102-revA zynqmp-zcu102-revB zynqmp-zcu104-revA zynqmp-zcu104-revC zynqmp-zcu106-revA zynqmp-zcu106-rev1.0 zynqmp-zcu111-revA zynqmp-zcu1275-revA zynqmp-zcu1275-revB zynqmp-zcu1285-revA zynqmp-zcu208-revA zynqmp-zcu216-revA zynqmp-topic-miamimp-xilinx-xdp-v1r1 zynqmp-sm-k26-revA zynqmp-smk-k26-revA zynqmp-dlc21-revA"
+CONFIG_OF_LIST="avnet-ultra96-rev1 zynqmp-a2197-revA zynqmp-e-a2197-00-revA zynqmp-e-a2197-00-revB zynqmp-g-a2197-00-revA zynqmp-m-a2197-01-revA zynqmp-m-a2197-02-revA zynqmp-m-a2197-03-revA zynqmp-p-a2197-00-revA zynqmp-zc1232-revA zynqmp-zc1254-revA zynqmp-zc1751-xm015-dc1 zynqmp-zc1751-xm016-dc2 zynqmp-zc1751-xm017-dc3 zynqmp-zc1751-xm018-dc4 zynqmp-zc1751-xm019-dc5 zynqmp-zcu100-revC zynqmp-zcu102-rev1.1 zynqmp-zcu102-rev1.0 zynqmp-zcu102-revA zynqmp-zcu102-revB zynqmp-zcu104-revA zynqmp-zcu104-revC zynqmp-zcu106-revA zynqmp-zcu106-rev1.0 zynqmp-zcu111-revA zynqmp-zcu1275-revA zynqmp-zcu1275-revB zynqmp-zcu1285-revA zynqmp-zcu208-revA zynqmp-zcu216-revA zynqmp-topic-miamimp-xilinx-xdp-v1r1 zynqmp-sm-k26-revA zynqmp-smk-k26-revA zynqmp-dlc21-revA"
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent interrupts iommus power-domains"
CONFIG_ENV_IS_NOWHERE=y
CONFIG_ENV_IS_IN_FAT=y
--
2.36.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 04/11] arm64: zynqmp: Add x-prc-01/02/03/04/05 revA support from SC
2023-09-27 9:53 [PATCH 00/11] xilinx: add missing boards/SC descriptions Michal Simek
` (2 preceding siblings ...)
2023-09-27 9:53 ` [PATCH 03/11] arm64: zynqmp: Add support for vck190 revB system controller Michal Simek
@ 2023-09-27 9:53 ` Michal Simek
2023-09-27 9:53 ` [PATCH 05/11] arm64: zynqmp: Add support for vpk120-revA Michal Simek
` (7 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Michal Simek @ 2023-09-27 9:53 UTC (permalink / raw)
To: u-boot, git
Add i2c accessible devices with description.
There is versal specific eeprom and i2c-gpio controller.
SE3 has also clock chip present.
Also remove x-prc description from SC dts.
Signed-off-by: Michal Simek <michal.simek@amd.com>
---
arch/arm/dts/Makefile | 5 ++
.../zynqmp-p-a2197-00-revA-x-prc-01-revA.dtso | 76 ++++++++++++++++
.../zynqmp-p-a2197-00-revA-x-prc-02-revA.dtso | 76 ++++++++++++++++
.../zynqmp-p-a2197-00-revA-x-prc-03-revA.dtso | 80 +++++++++++++++++
.../zynqmp-p-a2197-00-revA-x-prc-04-revA.dtso | 86 +++++++++++++++++++
.../zynqmp-p-a2197-00-revA-x-prc-05-revA.dtso | 86 +++++++++++++++++++
6 files changed, 409 insertions(+)
create mode 100644 arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-01-revA.dtso
create mode 100644 arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-02-revA.dtso
create mode 100644 arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-03-revA.dtso
create mode 100644 arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-04-revA.dtso
create mode 100644 arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-05-revA.dtso
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index e060081cdea5..d1b28a6d02ed 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -401,6 +401,11 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
zynqmp-m-a2197-02-revA.dtb \
zynqmp-m-a2197-03-revA.dtb \
zynqmp-p-a2197-00-revA.dtb \
+ zynqmp-p-a2197-00-revA-x-prc-01-revA.dtbo \
+ zynqmp-p-a2197-00-revA-x-prc-02-revA.dtbo \
+ zynqmp-p-a2197-00-revA-x-prc-03-revA.dtbo \
+ zynqmp-p-a2197-00-revA-x-prc-04-revA.dtbo \
+ zynqmp-p-a2197-00-revA-x-prc-05-revA.dtbo \
zynqmp-mini.dtb \
zynqmp-mini-emmc0.dtb \
zynqmp-mini-emmc1.dtb \
diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-01-revA.dtso b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-01-revA.dtso
new file mode 100644
index 000000000000..197dc2523531
--- /dev/null
+++ b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-01-revA.dtso
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP System Controller X-PRC-01 revA (SE1)
+ *
+ * (C) Copyright 2019 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+/dts-v1/;
+/plugin/;
+
+/{
+ compatible = "xlnx,zynqmp-x-prc-01-revA", "xlnx,zynqmp-x-prc-01";
+
+ fragment@0 {
+ target = <&dc_i2c>;
+
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ x_prc_eeprom: eeprom@52 { /* u120 */
+ compatible = "atmel,24c02";
+ reg = <0x52>;
+ };
+
+ x_prc_tca9534: gpio@22 { /* u121 tca9534 */
+ compatible = "nxp,pca9534";
+ reg = <0x22>;
+ gpio-controller; /* IRQ not connected */
+ #gpio-cells = <2>;
+ gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4",
+ "", "", "", "";
+ gtr-sel0 {
+ gpio-hog;
+ gpios = <0 0>;
+ input; /* FIXME add meaning */
+ line-name = "sw4_1";
+ };
+ gtr-sel1 {
+ gpio-hog;
+ gpios = <1 0>;
+ input; /* FIXME add meaning */
+ line-name = "sw4_2";
+ };
+ gtr-sel2 {
+ gpio-hog;
+ gpios = <2 0>;
+ input; /* FIXME add meaning */
+ line-name = "sw4_3";
+ };
+ gtr-sel3 {
+ gpio-hog;
+ gpios = <3 0>;
+ input; /* FIXME add meaning */
+ line-name = "sw4_4";
+ };
+ };
+ };
+ };
+
+ fragment@1 {
+ target = <&i2c1>; /* Must be enabled via J242 */
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eeprom_versal: eeprom@51 { /* u116 */
+ compatible = "atmel,24c02";
+ reg = <0x51>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-02-revA.dtso b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-02-revA.dtso
new file mode 100644
index 000000000000..8eb6e40dd9dd
--- /dev/null
+++ b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-02-revA.dtso
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP System Controller X-PRC-02 revA (SE2)
+ *
+ * (C) Copyright 2019 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+/dts-v1/;
+/plugin/;
+
+/{
+ compatible = "xlnx,zynqmp-x-prc-02-revA", "xlnx,zynqmp-x-prc-02";
+
+ fragment@0 {
+ target = <&dc_i2c>;
+
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ x_prc_eeprom: eeprom@52 { /* u16 */
+ compatible = "atmel,24c02";
+ reg = <0x52>;
+ };
+
+ x_prc_tca9534: gpio@22 { /* u17 tca9534 */
+ compatible = "nxp,pca9534";
+ reg = <0x22>;
+ gpio-controller; /* IRQ not connected */
+ #gpio-cells = <2>;
+ gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4",
+ "", "", "", "";
+ gtr-sel0 {
+ gpio-hog;
+ gpios = <0 0>;
+ input; /* FIXME add meaning */
+ line-name = "sw4_1";
+ };
+ gtr-sel1 {
+ gpio-hog;
+ gpios = <1 0>;
+ input; /* FIXME add meaning */
+ line-name = "sw4_2";
+ };
+ gtr-sel2 {
+ gpio-hog;
+ gpios = <2 0>;
+ input; /* FIXME add meaning */
+ line-name = "sw4_3";
+ };
+ gtr-sel3 {
+ gpio-hog;
+ gpios = <3 0>;
+ input; /* FIXME add meaning */
+ line-name = "sw4_4";
+ };
+ };
+ };
+ };
+
+ fragment@1 {
+ target = <&i2c1>; /* Must be enabled via J242 */
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eeprom_versal: eeprom@51 { /* u12 */
+ compatible = "atmel,24c02";
+ reg = <0x51>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-03-revA.dtso b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-03-revA.dtso
new file mode 100644
index 000000000000..af7a3ce9c1a6
--- /dev/null
+++ b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-03-revA.dtso
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP System Controller X-PRC-03 revA (SE3)
+ *
+ * (C) Copyright 2019 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+/dts-v1/;
+/plugin/;
+
+/{
+ compatible = "xlnx,zynqmp-x-prc-03-revA", "xlnx,zynqmp-x-prc-03";
+
+ fragment@0 {
+ target = <&dc_i2c>;
+
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ x_prc_eeprom: eeprom@52 { /* u1 */
+ compatible = "atmel,24c02";
+ reg = <0x52>;
+ };
+
+ x_prc_tca9534: gpio@22 { /* u3 tca9534 */
+ compatible = "nxp,pca9534";
+ reg = <0x22>;
+ gpio-controller; /* IRQ not connected */
+ #gpio-cells = <2>;
+ gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4",
+ "", "", "", "";
+ gtr-sel0 {
+ gpio-hog;
+ gpios = <0 0>;
+ input; /* FIXME add meaning */
+ line-name = "sw4_1";
+ };
+ gtr-sel1 {
+ gpio-hog;
+ gpios = <1 0>;
+ input; /* FIXME add meaning */
+ line-name = "sw4_2";
+ };
+ gtr-sel2 {
+ gpio-hog;
+ gpios = <2 0>;
+ input; /* FIXME add meaning */
+ line-name = "sw4_3";
+ };
+ gtr-sel3 {
+ gpio-hog;
+ gpios = <3 0>;
+ input; /* FIXME add meaning */
+ line-name = "sw4_4";
+ };
+ };
+ x_prc_si5338: clock-generator@70 { /* U9 */
+ compatible = "silabs,si5338";
+ reg = <0x70>; /* FIXME */
+ };
+ };
+ };
+
+ fragment@1 {
+ target = <&i2c1>; /* Must be enabled via J90/J91 */
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eeprom_versal: eeprom@51 { /* u2 */
+ compatible = "atmel,24c02";
+ reg = <0x51>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-04-revA.dtso b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-04-revA.dtso
new file mode 100644
index 000000000000..29a6c2a627bf
--- /dev/null
+++ b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-04-revA.dtso
@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP System Controller X-PRC-04 revA (SE4)
+ *
+ * (C) Copyright 2019 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+/dts-v1/;
+/plugin/;
+
+/{
+ compatible = "xlnx,zynqmp-x-prc-04-revA", "xlnx,zynqmp-x-prc-04";
+
+ fragment@0 {
+ target = <&dc_i2c>;
+
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ x_prc_eeprom: eeprom@52 { /* u120 */
+ compatible = "atmel,24c02";
+ reg = <0x52>;
+ };
+
+ x_prc_tca9534: gpio@22 { /* u121 tca9534 */
+ compatible = "nxp,pca9534";
+ reg = <0x22>;
+ gpio-controller; /* IRQ not connected */
+ #gpio-cells = <2>;
+ gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4",
+ "", "", "", "";
+ gtr-sel0 {
+ gpio-hog;
+ gpios = <0 0>;
+ input; /* FIXME add meaning */
+ line-name = "sw4_1";
+ };
+ gtr-sel1 {
+ gpio-hog;
+ gpios = <1 0>;
+ input; /* FIXME add meaning */
+ line-name = "sw4_2";
+ };
+ gtr-sel2 {
+ gpio-hog;
+ gpios = <2 0>;
+ input; /* FIXME add meaning */
+ line-name = "sw4_3";
+ };
+ gtr-sel3 {
+ gpio-hog;
+ gpios = <3 0>;
+ input; /* FIXME add meaning */
+ line-name = "sw4_4";
+ };
+ };
+
+ si570_gem_tsu: clock-generator@5d { /* u164 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>;
+ temperature-stability = <50>;
+ factory-fout = <300000000>; /* FIXME */
+ clock-frequency = <300000000>;
+ clock-output-names = "si570_gem_tsu_clk";
+ };
+ };
+ };
+
+ fragment@1 {
+ target = <&i2c1>;
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eeprom_versal: eeprom@51 { /* u153 */
+ compatible = "atmel,24c02";
+ reg = <0x51>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-05-revA.dtso b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-05-revA.dtso
new file mode 100644
index 000000000000..6ddf18cf6430
--- /dev/null
+++ b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-05-revA.dtso
@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP System Controller X-PRC-05 revA (SE5)
+ *
+ * (C) Copyright 2019 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+/dts-v1/;
+/plugin/;
+
+/{
+ compatible = "xlnx,zynqmp-x-prc-05-revA", "xlnx,zynqmp-x-prc-05";
+
+ fragment@0 {
+ target = <&dc_i2c>;
+
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ x_prc_eeprom: eeprom@52 { /* u120 */
+ compatible = "atmel,24c02";
+ reg = <0x52>;
+ };
+
+ x_prc_tca9534: gpio@22 { /* u121 tca9534 */
+ compatible = "nxp,pca9534";
+ reg = <0x22>;
+ gpio-controller; /* IRQ not connected */
+ #gpio-cells = <2>;
+ gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4",
+ "", "", "", "";
+ gtr-sel0 {
+ gpio-hog;
+ gpios = <0 0>;
+ input; /* FIXME add meaning */
+ line-name = "sw4_1";
+ };
+ gtr-sel1 {
+ gpio-hog;
+ gpios = <1 0>;
+ input; /* FIXME add meaning */
+ line-name = "sw4_2";
+ };
+ gtr-sel2 {
+ gpio-hog;
+ gpios = <2 0>;
+ input; /* FIXME add meaning */
+ line-name = "sw4_3";
+ };
+ gtr-sel3 {
+ gpio-hog;
+ gpios = <3 0>;
+ input; /* FIXME add meaning */
+ line-name = "sw4_4";
+ };
+ };
+
+ si570_gem_tsu: clock-generator@5d { /* u164 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>;
+ temperature-stability = <50>;
+ factory-fout = <300000000>; /* FIXME */
+ clock-frequency = <300000000>;
+ clock-output-names = "si570_gem_tsu_clk";
+ };
+ };
+ };
+
+ fragment@1 {
+ target = <&i2c1>;
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eeprom_versal: eeprom@51 { /* u153 */
+ compatible = "atmel,24c02";
+ reg = <0x51>;
+ };
+ };
+ };
+};
--
2.36.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 05/11] arm64: zynqmp: Add support for vpk120-revA
2023-09-27 9:53 [PATCH 00/11] xilinx: add missing boards/SC descriptions Michal Simek
` (3 preceding siblings ...)
2023-09-27 9:53 ` [PATCH 04/11] arm64: zynqmp: Add x-prc-01/02/03/04/05 revA support from SC Michal Simek
@ 2023-09-27 9:53 ` Michal Simek
2023-09-27 9:53 ` [PATCH 06/11] arm64: zynqmp: Create description for generic SC (vpk120-revB) Michal Simek
` (6 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Michal Simek @ 2023-09-27 9:53 UTC (permalink / raw)
To: u-boot, git
Board contains two systems. The primary is Versal VP1202 ACAP device and
the secondary is ZynqMP zu4 which acts as system controller. The patch is
describing only ZynqMP system controller part.
Signed-off-by: Michal Simek <michal.simek@amd.com>
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/zynqmp-vpk120-revA.dts | 574 ++++++++++++++++++++++++++++
2 files changed, 575 insertions(+)
create mode 100644 arch/arm/dts/zynqmp-vpk120-revA.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index d1b28a6d02ed..fbce328acafe 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -421,6 +421,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
zynqmp-sck-kv-g-revA.dtbo \
zynqmp-sck-kv-g-revB.dtbo \
zynqmp-topic-miamimp-xilinx-xdp-v1r1.dtb \
+ zynqmp-vpk120-revA.dtb \
zynqmp-zcu100-revC.dtb \
zynqmp-zcu102-revA.dtb \
zynqmp-zcu102-revB.dtb \
diff --git a/arch/arm/dts/zynqmp-vpk120-revA.dts b/arch/arm/dts/zynqmp-vpk120-revA.dts
new file mode 100644
index 000000000000..66919f578e02
--- /dev/null
+++ b/arch/arm/dts/zynqmp-vpk120-revA.dts
@@ -0,0 +1,574 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP VPK120 RevA System Controller
+ *
+ * (C) Copyright 2021 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
+#include <dt-bindings/phy/phy.h>
+
+/ {
+ model = "ZynqMP System Controller on VPK120 board RevA";
+ compatible = "xlnx,zynqmp-vpk120-revA",
+ "xlnx,zynqmp-vpk120", "xlnx,zynqmp";
+
+ aliases {
+ ethernet0 = &gem0;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ mmc0 = &sdhci0;
+ serial0 = &uart0;
+ serial1 = &dcc;
+ spi0 = &qspi;
+ usb0 = &usb0;
+ usb1 = &usb1;
+ nvmem0 = &eeprom;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+ sw16 {
+ label = "sw16";
+ gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
+ linux,code = <BTN_MISC>;
+ wakeup-source;
+ autorepeat;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ heartbeat-led { /* ds40 */
+ label = "heartbeat";
+ gpios = <&gpio 9 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ si5332_0: si5332_0 { /* ps_ref_clk */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <33333333>;
+ };
+
+ si5332_1: si5332_1 { /* clk0_sgmii */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <33333333>; /* FIXME */
+ };
+
+ si5332_2: si5332_2 { /* clk1_usb */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <27000000>;
+ };
+};
+
+&qspi { /* MIO 0-5 */
+ status = "okay";
+ flash@0 {
+ compatible = "m25p80", "jedec,spi-nor"; /* mt25qu512abb8e12 512Mib */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <108000000>;
+ partition@0 { /* for testing purpose */
+ label = "qspi";
+ reg = <0 0x4000000>;
+ };
+ };
+};
+
+&sdhci0 { /* emmc MIO 13-23 - with some settings MTFC16GAPALBH 16GB */
+ status = "okay";
+ non-removable;
+ disable-wp;
+ bus-width = <8>;
+ xlnx,mio-bank = <0>;
+};
+
+&uart0 { /* uart0 MIO38-39 */
+ status = "okay";
+ bootph-all;
+};
+
+&gem0 {
+ status = "okay";
+ phy-handle = <&phy0>;
+ phy-mode = "sgmii"; /* DTG generates this properly 1512 */
+ is-internal-pcspma;
+ /* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */
+ /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+};
+
+&gpio {
+ status = "okay";
+ gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */
+ "QSPI_CS_B", "", "", "SYSCTLR_GPIO", "SYSCTLR_LED", /* 5 - 9 */
+ "SYSCTLR_PB", "PMC_ZU4_TRIGGER", "", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */
+ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */
+ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */
+ "", "", "", "", "", /* 25 - 29 */
+ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */
+ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */
+ "", "", "ETH_RESET_B", "", "", /* 40 - 44 */
+ "", "", "", "", "", /* 45 - 49 */
+ "", "", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */
+ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */
+ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "", /* 60 - 64 */
+ "", "", "", "", "", /* 65 - 69 */
+ "", "", "", "", "", /* 70 - 74 */
+ "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
+ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */
+ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "", "", /* 80 - 84 */
+ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "", /* 85 - 89 */
+ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */
+ "SYSCTLR_GPIO5", "", "", "", "", /* 95 - 99 */
+ "", "", "", "", "", /* 100 - 104 */
+ "", "", "", "", "", /* 105 - 109 */
+ "", "", "", "", "", /* 110 - 114 */
+ "", "", "", "", "", /* 115 - 119 */
+ "", "", "", "", "", /* 120 - 124 */
+ "", "", "", "", "", /* 125 - 129 */
+ "", "", "", "", "", /* 130 - 134 */
+ "", "", "", "", "", /* 135 - 139 */
+ "", "", "", "", "", /* 140 - 144 */
+ "", "", "", "", "", /* 145 - 149 */
+ "", "", "", "", "", /* 150 - 154 */
+ "", "", "", "", "", /* 155 - 159 */
+ "", "", "", "", "", /* 160 - 164 */
+ "", "", "", "", "", /* 165 - 169 */
+ "", "", "", ""; /* 170 - 173 */
+};
+
+&i2c0 { /* MIO 34-35 - can't stay here */
+ status = "okay";
+ clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c0_default>;
+ pinctrl-1 = <&pinctrl_i2c0_gpio>;
+ scl-gpios = <&gpio 34 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio 35 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+
+ tca6416_u233: gpio@20 { /* u233 */ /* FIXME - address maybe wrong */
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller; /* interrupt not connected */
+ #gpio-cells = <2>;
+ gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "QSFPDD1_MODSELL", "QSFPDD1_MODSELL", /* 0 - 3 */
+ "PMBUS2_INA226_ALERT", "", "", "MAX6643_FULL_SPEED", /* 4 - 7 */
+ "FMCP1_FMC_PRSNT_M2C_B", "", "FMCP1_FMCP_PRSNT_M2C_B", "", /* 10 - 13 */
+ "VCCINT_VRHOT_B", "8A34001_EXP_RST_B", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */
+ };
+
+ i2c-mux@74 { /* u33 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
+ pmbus_i2c: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* On connector J325 */
+ ir38060_41: regulator@41 { /* IR38060 - u259 */
+ compatible = "infineon,ir38060", "infineon,ir38064";
+ reg = <0x41>; /* i2c addr 0x11 */
+ };
+ ir38164_43: regulator@43 { /* IR38164 - u13 */
+ compatible = "infineon,ir38164";
+ reg = <0x43>; /* i2c addr 0x13 */
+ };
+ ir35221_45: pmic@46 { /* IR35221 - u152 */
+ compatible = "infineon,ir35221";
+ reg = <0x46>; /* PMBUS - 0x16 */
+ };
+ irps5401_47: pmic5401@47 { /* IRPS5401 - u160 */
+ compatible = "infineon,irps5401";
+ reg = <0x47>; /* i2c addr 0x17 */
+ };
+ ir38164_49: regulator@49 { /* IR38164 - u189 */
+ compatible = "infineon,ir38164";
+ reg = <0x49>; /* i2c addr 0x19 */
+ };
+ irps5401_4c: pmic@4c { /* IRPS5401 - u167 */
+ compatible = "infineon,irps5401";
+ reg = <0x4c>; /* i2c addr 0x1c */
+ };
+ irps5401_4d: pmic@4d { /* IRPS5401 - u175 */
+ compatible = "infineon,irps5401";
+ reg = <0x4d>; /* i2c addr 0x1c */
+ };
+ ir38164_4e: regulator@4e { /* IR38164 - u184 */
+ compatible = "infineon,ir38164";
+ reg = <0x4e>; /* i2c addr 0x1e */
+ };
+ ir38164_4f: regulator@4f { /* IR38164 - u187 */
+ compatible = "infineon,ir38164";
+ reg = <0x4f>; /* i2c addr 0x1f */
+ };
+ };
+ pmbus1_ina226_i2c: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* FIXME check alerts coming to SC */
+ vccint: ina226@40 { /* u65 */
+ compatible = "ti,ina226";
+ reg = <0x40>;
+ shunt-resistor = <5000>;
+ };
+ vcc_soc: ina226@41 { /* u161 */
+ compatible = "ti,ina226";
+ reg = <0x41>;
+ shunt-resistor = <5000>;
+ };
+ vcc_pmc: ina226@42 { /* u163 */
+ compatible = "ti,ina226";
+ reg = <0x42>;
+ shunt-resistor = <5000>;
+ };
+ vcc_ram: ina226@43 { /* u5 */
+ compatible = "ti,ina226";
+ reg = <0x43>;
+ shunt-resistor = <5000>;
+ };
+ vcc_pslp: ina226@44 { /* u165 */
+ compatible = "ti,ina226";
+ reg = <0x44>;
+ shunt-resistor = <5000>;
+ };
+ vcc_psfp: ina226@45 { /* u164 */
+ compatible = "ti,ina226";
+ reg = <0x45>;
+ shunt-resistor = <5000>;
+ };
+ };
+ i2c@2 { /* NC */ /* FIXME maybe remove */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+ pmbus2_ina226_i2c: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ /* FIXME check alerts coming to SC */
+ vccaux: ina226@40 { /* u166 */
+ compatible = "ti,ina226";
+ reg = <0x40>;
+ shunt-resistor = <5000>;
+ };
+ vccaux_pmc: ina226@41 { /* u168 */
+ compatible = "ti,ina226";
+ reg = <0x41>;
+ shunt-resistor = <5000>;
+ };
+ mgtavcc: ina226@42 { /* u265 */
+ compatible = "ti,ina226";
+ reg = <0x42>;
+ shunt-resistor = <5000>;
+ };
+ vcc1v5: ina226@43 { /* u264 */
+ compatible = "ti,ina226";
+ reg = <0x43>;
+ shunt-resistor = <5000>;
+ };
+ vcco_mio: ina226@45 { /* u172 */
+ compatible = "ti,ina226";
+ reg = <0x45>;
+ shunt-resistor = <5000>;
+ };
+ mgtavtt: ina226@46 { /* u188 */
+ compatible = "ti,ina226";
+ reg = <0x46>;
+ shunt-resistor = <2000>;
+ };
+ vcco_502: ina226@47 { /* u174 */
+ compatible = "ti,ina226";
+ reg = <0x47>;
+ shunt-resistor = <5000>;
+ };
+ mgtvccaux: ina226@48 { /* u176 */
+ compatible = "ti,ina226";
+ reg = <0x48>;
+ shunt-resistor = <5000>;
+ };
+ vcc1v1_lp4: ina226@49 { /* u186 */
+ compatible = "ti,ina226";
+ reg = <0x49>;
+ shunt-resistor = <2000>;
+ };
+ vadj_fmc: ina226@4a { /* u184 */
+ compatible = "ti,ina226";
+ reg = <0x4a>;
+ shunt-resistor = <2000>;
+ };
+ lpdmgtyavcc: ina226@4b { /* u177 */
+ compatible = "ti,ina226";
+ reg = <0x4b>;
+ shunt-resistor = <5000>;
+ };
+ lpdmgtyavtt: ina226@4c { /* u260 */
+ compatible = "ti,ina226";
+ reg = <0x4c>;
+ shunt-resistor = <2000>;
+ };
+ lpdmgtyvccaux: ina226@4d { /* u234 */
+ compatible = "ti,ina226";
+ reg = <0x4d>;
+ shunt-resistor = <5000>;
+ };
+ };
+ i2c@4 { /* NC */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ };
+ i2c@5 { /* NC */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ };
+ user_si570: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ user_si570_1: clock-generator@5f { /* USER C0 SI570 - u205 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5f>;
+ temperature-stability = <50>;
+ factory-fout = <100000000>;
+ clock-frequency = <100000000>;
+ clock-output-names = "fmc_si570";
+ };
+
+ };
+ /* 7 unused */
+ };
+};
+
+&i2c1 { /* i2c1 MIO 36-37 */
+ status = "okay";
+ clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio 36 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio 37 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+
+ i2c-mux@74 { /* u35 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */
+ ref_clk_i2c: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* Use for storing information about SC board */
+ eeprom: eeprom@54 { /* u34 - m24128 16kB */
+ compatible = "st,24c128", "atmel,24c128";
+ reg = <0x54>; /* & 0x5c */
+ };
+ ref_clk: clock-generator@5d { /* u32 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>;
+ temperature-stability = <50>;
+ factory-fout = <33333333>;
+ clock-frequency = <33333333>;
+ clock-output-names = "ref_clk";
+ silabs,skip-recall;
+ };
+ };
+ fmcp1_i2c: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* FIXME connection to Samtec J51C */
+ /* expected eeprom 0x50 SE cards */
+ };
+ i2c@2 { /* NC - FIXME */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+ lpddr4_si570_clk3_i2c: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ lpddr4_clk3: clock-generator@60 { /* u4 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x60>;
+ temperature-stability = <50>;
+ factory-fout = <200000000>;
+ clock-frequency = <200000000>;
+ clock-output-names = "lpddr4_clk3";
+ };
+ };
+ lpddr4_si570_clk2_i2c: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ lpddr4_clk2: clock-generator@60 { /* u3 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x60>;
+ temperature-stability = <50>;
+ factory-fout = <200000000>;
+ clock-frequency = <200000000>;
+ clock-output-names = "lpddr4_clk2";
+ };
+ };
+ lpddr4_si570_clk1_i2c: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ lpddr4_clk1: clock-generator@60 { /* u248 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x60>;
+ temperature-stability = <50>;
+ factory-fout = <200000000>;
+ clock-frequency = <200000000>;
+ clock-output-names = "lpddr4_clk1";
+ };
+ };
+ qsfpdd_i2c: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ /* J1/J2 connectors */
+ };
+ idt8a34001_i2c: i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ /* Via J310 connector */
+ idt_8a34001: phc@5b {
+ compatible = "idt,8a34001"; /* u219B */
+ reg = <0x5b>; /* FIXME not in schematics */
+ };
+ };
+ };
+};
+
+&usb0 { /* MIO52 - MIO63 */
+ status = "okay";
+ phy-names = "usb3-phy";
+ phys = <&psgtr 1 PHY_TYPE_USB3 0 1>;
+};
+
+&psgtr {
+ status = "okay";
+ /* sgmii, usb3 */
+ clocks = <&si5332_1>, <&si5332_2>;
+ clock-names = "ref0", "ref1";
+};
+
+&dwc3_0 {
+ status = "okay";
+ dr_mode = "peripheral";
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ maximum-speed = "super-speed";
+};
+
+&xilinx_ams {
+ status = "okay";
+};
+
+&ams_ps {
+ status = "okay";
+};
+
+&ams_pl {
+ status = "okay";
+};
+
+&pinctrl0 {
+ status = "okay";
+ pinctrl_i2c0_default: i2c0-default {
+ mux {
+ groups = "i2c0_8_grp";
+ function = "i2c0";
+ };
+
+ conf {
+ groups = "i2c0_8_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c0_gpio: i2c0-gpio {
+ mux {
+ groups = "gpio0_34_grp", "gpio0_35_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_34_grp", "gpio0_35_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c1_default: i2c1-default {
+ mux {
+ groups = "i2c1_9_grp";
+ function = "i2c1";
+ };
+
+ conf {
+ groups = "i2c1_9_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpio {
+ mux {
+ groups = "gpio0_36_grp", "gpio0_37_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_36_grp", "gpio0_37_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+};
--
2.36.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 06/11] arm64: zynqmp: Create description for generic SC (vpk120-revB)
2023-09-27 9:53 [PATCH 00/11] xilinx: add missing boards/SC descriptions Michal Simek
` (4 preceding siblings ...)
2023-09-27 9:53 ` [PATCH 05/11] arm64: zynqmp: Add support for vpk120-revA Michal Simek
@ 2023-09-27 9:53 ` Michal Simek
2023-09-27 9:53 ` [PATCH 07/11] arm64: zynqmp: Add support for SC revC Michal Simek
` (5 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Michal Simek @ 2023-09-27 9:53 UTC (permalink / raw)
To: u-boot, git
System controllers are pretty much the same on the all boards that's why
use autodetection based on i2c eeprom. This should end up with having only
one BSP for all SCs with only DT overlays to cover different i2c
structures.
All MIOs are fixed by the spec that's why not a problem to description
pinctrl setting.
Apart from eth phy reset, it also set proper phy delays.
The TI DP83867 PHY datasheet says:
T1: Post RESET stabilization time == 195us
T3: Hardware configuration pins transition to output drivers == 64us
T4: RESET pulse width == 1us
So with a little overhead set 'reset-assert-us' to 100us (T4) and
'reset-deassert-us' to 280us (T1+T3).
NOTE: The tuning of TI DP83867 phy reset delay is derived from linux
upstream commit: 5dbadc848259(arm64: dts: fsl: add support for Kontron
pitx-imx8m board).
i2c structure on Xilinx Versal evaluation platforms contain a lot of
devices but also connection to connectors like SFP. Because of this
complicated structure with also all level shifters, i2c muxes, etc. not all
devices are able to reliably work on 400kHz even if they are compatible
with this speed. That's why set i2c frequency to 100KHz to increase
reliability of the i2c bus.
Signed-off-by: Michal Simek <michal.simek@amd.com>
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/zynqmp-sc-revB.dts | 430 ++++++++++++++++++++++++++++++++
2 files changed, 431 insertions(+)
create mode 100644 arch/arm/dts/zynqmp-sc-revB.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index fbce328acafe..29c40d1c3b66 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -411,6 +411,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
zynqmp-mini-emmc1.dtb \
zynqmp-mini-nand.dtb \
zynqmp-mini-qspi.dtb \
+ zynqmp-sc-revB.dtb \
zynqmp-sm-k24-revA.dtb \
zynqmp-smk-k24-revA.dtb \
zynqmp-sm-k26-revA.dtb \
diff --git a/arch/arm/dts/zynqmp-sc-revB.dts b/arch/arm/dts/zynqmp-sc-revB.dts
new file mode 100644
index 000000000000..e0b554c9c545
--- /dev/null
+++ b/arch/arm/dts/zynqmp-sc-revB.dts
@@ -0,0 +1,430 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP Generic System Controller
+ *
+ * (C) Copyright 2021 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/net/ti-dp83867.h>
+#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
+#include <dt-bindings/phy/phy.h>
+
+/ {
+ model = "ZynqMP Generic System Controller";
+ compatible = "xlnx,zynqmp-sc-revB", "xlnx,zynqmp-sc", "xlnx,zynqmp";
+
+ aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ mmc0 = &sdhci0;
+ mmc1 = &sdhci1;
+ nvmem0 = &eeprom;
+ rtc0 = &rtc;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &dcc;
+ spi0 = &qspi;
+ spi1 = &spi0;
+ spi2 = &spi1;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial1:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+ fwuen {
+ label = "sw16";
+ gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
+ linux,code = <BTN_MISC>;
+ wakeup-source;
+ autorepeat;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ ds40-led {
+ label = "heartbeat";
+ gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ ds44-led {
+ label = "status";
+ gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ si5332_2: si5332_2 { /* u42 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ };
+
+ pwm-fan {
+ compatible = "pwm-fan";
+ status = "okay";
+ pwms = <&ttc0 2 40000 1>;
+ };
+};
+
+&gpio {
+ status = "okay";
+ gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */
+ "QSPI_CS_B", "", "LED1", "LED2", "", /* 5 - 9 */
+ "", "ZU4_TRIGGER", "FWUEN", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */
+ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */
+ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "I2C1_SCL", /* 20 - 24 */
+ "I2C1_SDA", "UART0_RXD", "UART0_TXD", "", "", /* 25 - 29 */
+ "", "", "", "", "I2C0_SCL", /* 30 - 34 */
+ "I2C0_SDA", "UART1_TXD", "UART1_RXD", "GEM_TX_CLK", "GEM_TX_D0", /* 35 - 39 */
+ "GEM_TX_D1", "GEM_TX_D2", "GEM_TX_D3", "GEM_TX_CTL", "GEM_RX_CLK", /* 40 - 44 */
+ "GEM_RX_D0", "GEM_RX_D1", "GEM_RX_D2", "GEM_RX_D3", "GEM_RX_CTL", /* 45 - 49 */
+ "GEM_MDC", "GEM_MDIO", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */
+ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */
+ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "", /* 60 - 64 */
+ "", "", "", "", "", /* 65 - 69 */
+ "", "", "", "", "", /* 70 - 74 */
+ "", "", "ETH_RESET_B", /* 75 - 77, MIO end and EMIO start */
+ "", "", /* 78 - 79 */
+ "", "", "", "", "", /* 80 - 84 */
+ "", "", "", "", "", /* 85 -89 */
+ "", "", "", "", "", /* 90 - 94 */
+ "", "", "", "", "", /* 95 - 99 */
+ "", "", "", "", "", /* 100 - 104 */
+ "", "", "", "", "", /* 105 - 109 */
+ "", "", "", "", "", /* 110 - 114 */
+ "", "", "", "", "", /* 115 - 119 */
+ "", "", "", "", "", /* 120 - 124 */
+ "", "", "", "", "", /* 125 - 129 */
+ "", "", "", "", "", /* 130 - 134 */
+ "", "", "", "", "", /* 135 - 139 */
+ "", "", "", "", "", /* 140 - 144 */
+ "", "", "", "", "", /* 145 - 149 */
+ "", "", "", "", "", /* 150 - 154 */
+ "", "", "", "", "", /* 155 - 159 */
+ "", "", "", "", "", /* 160 - 164 */
+ "", "", "", "", "", /* 165 - 169 */
+ "", "", "", ""; /* 170 - 173 */
+};
+
+&gem1 { /* gem1 MIO38-49, MDIO MIO50/51 */
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <&phy0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gem1_default>;
+
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy0: ethernet-phy@1 {
+ #phy-cells = <1>;
+ compatible = "ethernet-phy-id2000.a231";
+ reg = <1>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ ti,dp83867-rxctrl-strap-quirk;
+ reset-gpios = <&gpio 77 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <100>;
+ reset-deassert-us = <280>;
+ };
+ };
+};
+
+&i2c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ clock-frequency = <100000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c0_default>;
+ pinctrl-1 = <&pinctrl_i2c0_gpio>;
+ scl-gpios = <&gpio 34 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio 35 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+};
+
+&i2c1 { /* i2c1 MIO 24-25 */
+ status = "okay";
+ bootph-all;
+ clock-frequency = <100000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+
+ /* Use for storing information about SC board */
+ eeprom: eeprom@54 { /* u34 - m24128 16kB */
+ compatible = "st,24c128", "atmel,24c128";
+ reg = <0x54>; /* & 0x5c */
+ bootph-all;
+ };
+};
+
+/* USB 3.0 only */
+&psgtr {
+ status = "okay";
+ /* nc, nc, usb3 */
+ clocks = <&si5332_2>;
+ clock-names = "ref2";
+};
+
+&qspi { /* MIO 0-5 */
+ status = "okay";
+ /* QSPI should also have PINCTRL setup */
+ flash@0 {
+ compatible = "mt25qu512a", "m25p80", "jedec,spi-nor"; /* mt25qu512abb8e12 512Mib */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <40000000>; /* 40MHz */
+ partition@0 {
+ label = "Image Selector";
+ reg = <0x0 0x80000>; /* 512KB */
+ read-only;
+ lock;
+ };
+ partition@80000 {
+ label = "Image Selector Golden";
+ reg = <0x80000 0x80000>; /* 512KB */
+ read-only;
+ lock;
+ };
+ partition@100000 {
+ label = "Persistent Register";
+ reg = <0x100000 0x20000>; /* 128KB */
+ };
+ partition@120000 {
+ label = "Persistent Register Backup";
+ reg = <0x120000 0x20000>; /* 128KB */
+ };
+ partition@140000 {
+ label = "Open_1";
+ reg = <0x140000 0xC0000>; /* 768KB */
+ };
+ partition@200000 {
+ label = "Image A (FSBL, PMU, ATF, U-Boot)";
+ reg = <0x200000 0xD00000>; /* 13MB */
+ };
+ partition@f00000 {
+ label = "ImgSel Image A Catch";
+ reg = <0xF00000 0x80000>; /* 512KB */
+ read-only;
+ lock;
+ };
+ partition@f80000 {
+ label = "Image B (FSBL, PMU, ATF, U-Boot)";
+ reg = <0xF80000 0xD00000>; /* 13MB */
+ };
+ partition@1c80000 {
+ label = "ImgSel Image B Catch";
+ reg = <0x1C80000 0x80000>; /* 512KB */
+ read-only;
+ lock;
+ };
+ partition@1d00000 {
+ label = "Open_2";
+ reg = <0x1D00000 0x100000>; /* 1MB */
+ };
+ partition@1e00000 {
+ label = "Recovery Image";
+ reg = <0x1E00000 0x200000>; /* 2MB */
+ read-only;
+ lock;
+ };
+ partition@2000000 {
+ label = "Recovery Image Backup";
+ reg = <0x2000000 0x200000>; /* 2MB */
+ read-only;
+ lock;
+ };
+ partition@2200000 {
+ label = "U-Boot storage variables";
+ reg = <0x2200000 0x20000>; /* 128KB */
+ };
+ partition@2220000 {
+ label = "U-Boot storage variables backup";
+ reg = <0x2220000 0x20000>; /* 128KB */
+ };
+ partition@2240000 {
+ label = "SHA256";
+ reg = <0x2240000 0x40000>; /* 256B but 256KB sector */
+ read-only;
+ lock;
+ };
+ partition@2280000 {
+ label = "Secure OS Storage";
+ reg = <0x2280000 0x20000>; /* 128KB */
+ };
+ partition@22A0000 {
+ label = "User";
+ reg = <0x22A0000 0x1d60000>; /* 29.375 MB */
+ };
+ };
+};
+
+&sdhci0 { /* emmc MIO 13-23 - with some settings MTFC16GAPALBH 16GB */
+ status = "okay";
+ non-removable;
+ disable-wp;
+ bus-width = <8>;
+ xlnx,mio-bank = <0>;
+};
+
+&ttc0 {
+ status = "okay";
+ #pwm-cells = <3>;
+};
+
+&uart1 { /* uart0 MIO36-37 */
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_default>;
+};
+
+&pinctrl0 { /* required by spec */
+ status = "okay";
+
+ pinctrl_uart1_default: uart1-default {
+ conf {
+ groups = "uart1_9_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ drive-strength = <12>;
+ };
+
+ conf-rx {
+ pins = "MIO37";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO36";
+ bias-disable;
+ };
+
+ mux {
+ groups = "uart1_9_grp";
+ function = "uart1";
+ };
+ };
+
+ pinctrl_i2c0_default: i2c0-default {
+ mux {
+ groups = "i2c0_8_grp";
+ function = "i2c0";
+ };
+
+ conf {
+ groups = "i2c0_8_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c0_gpio: i2c0-gpio {
+ mux {
+ groups = "gpio0_34_grp", "gpio0_35_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_34_grp", "gpio0_35_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c1_default: i2c1-default {
+ conf {
+ groups = "i2c1_6_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux {
+ groups = "i2c1_6_grp";
+ function = "i2c1";
+ };
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpio {
+ conf {
+ groups = "gpio0_24_grp", "gpio0_25_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux {
+ groups = "gpio0_24_grp", "gpio0_25_grp";
+ function = "gpio0";
+ };
+ };
+
+ pinctrl_gem1_default: gem1-default {
+ conf {
+ groups = "ethernet1_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO44", "MIO46", "MIO48";
+ bias-high-impedance;
+ low-power-disable;
+ };
+
+ conf-bootstrap {
+ pins = "MIO45", "MIO47", "MIO49";
+ bias-disable;
+ low-power-disable;
+ };
+
+ conf-tx {
+ pins = "MIO38", "MIO39", "MIO40",
+ "MIO41", "MIO42", "MIO43";
+ bias-disable;
+ low-power-enable;
+ };
+
+ conf-mdio {
+ groups = "mdio1_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+
+ mux-mdio {
+ function = "mdio1";
+ groups = "mdio1_0_grp";
+ };
+
+ mux {
+ function = "ethernet1";
+ groups = "ethernet1_0_grp";
+ };
+ };
+};
--
2.36.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 07/11] arm64: zynqmp: Add support for SC revC
2023-09-27 9:53 [PATCH 00/11] xilinx: add missing boards/SC descriptions Michal Simek
` (5 preceding siblings ...)
2023-09-27 9:53 ` [PATCH 06/11] arm64: zynqmp: Create description for generic SC (vpk120-revB) Michal Simek
@ 2023-09-27 9:53 ` Michal Simek
2023-09-27 9:53 ` [PATCH 08/11] arm64: zynqmp: Describe i2c structures for SCs Michal Simek
` (4 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Michal Simek @ 2023-09-27 9:53 UTC (permalink / raw)
To: u-boot, git
System controller revC is using ADI ethernet phy instead of TI because of
supply chain issues.
Describe reset assert and de-assert times to 10us and 5ms respectively
according to the datasheet. Also setup RGMII RX and TX delay values to
2400ps as per board bring up observations.
Signed-off-by: Michal Simek <michal.simek@amd.com>
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/zynqmp-sc-revC.dts | 37 +++++++++++++++++++++++++++++++++
2 files changed, 38 insertions(+)
create mode 100644 arch/arm/dts/zynqmp-sc-revC.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 29c40d1c3b66..3cde86d9eb38 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -412,6 +412,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
zynqmp-mini-nand.dtb \
zynqmp-mini-qspi.dtb \
zynqmp-sc-revB.dtb \
+ zynqmp-sc-revC.dtb \
zynqmp-sm-k24-revA.dtb \
zynqmp-smk-k24-revA.dtb \
zynqmp-sm-k26-revA.dtb \
diff --git a/arch/arm/dts/zynqmp-sc-revC.dts b/arch/arm/dts/zynqmp-sc-revC.dts
new file mode 100644
index 000000000000..530a4a5f080f
--- /dev/null
+++ b/arch/arm/dts/zynqmp-sc-revC.dts
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP Generic System Controller
+ *
+ * Copyright (C) 2021 - 2022, Xilinx, Inc.
+ * Copyright (C) 2022 - 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+#include "zynqmp-sc-revB.dts"
+
+/ {
+ model = "ZynqMP Generic System Controller";
+ compatible = "xlnx,zynqmp-sc-revC", "xlnx,zynqmp-sc", "xlnx,zynqmp";
+};
+
+&gem1 { /* gem1 MIO38-49, MDIO MIO50/51 */
+ /delete-node/ mdio;
+
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy0: ethernet-phy@1 { /* ADI1300 */
+ #phy-cells = <1>;
+ compatible = "ethernet-phy-id0283.bc30";
+ reg = <1>;
+ adi,rx-internal-delay-ps = <2400>;
+ adi,tx-internal-delay-ps = <2400>;
+ adi,fifo-depth-bits = <8>;
+ reset-gpios = <&gpio 77 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <10>;
+ reset-deassert-us = <5000>;
+ };
+ };
+};
--
2.36.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 08/11] arm64: zynqmp: Describe i2c structures for SCs
2023-09-27 9:53 [PATCH 00/11] xilinx: add missing boards/SC descriptions Michal Simek
` (6 preceding siblings ...)
2023-09-27 9:53 ` [PATCH 07/11] arm64: zynqmp: Add support for SC revC Michal Simek
@ 2023-09-27 9:53 ` Michal Simek
2023-09-27 9:53 ` [PATCH 09/11] arm64: zynqmp: Add support for VPXA2785 Michal Simek
` (3 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Michal Simek @ 2023-09-27 9:53 UTC (permalink / raw)
To: u-boot, git
Generic system controller (SC) covers connection defined by specification
but different boards have different i2c devices. That's why describe i2c
devices available on multiple boards.
Signed-off-by: Michal Simek <michal.simek@amd.com>
---
arch/arm/dts/Makefile | 7 +
arch/arm/dts/zynqmp-sc-vek280-revA.dtso | 230 +++++++++
arch/arm/dts/zynqmp-sc-vek280-revB.dtso | 15 +
arch/arm/dts/zynqmp-sc-vhk158-revA.dtso | 321 ++++++++++++
.../arm/dts/zynqmp-sc-vn-p-b2197-00-revA.dtso | 460 ++++++++++++++++++
arch/arm/dts/zynqmp-sc-vpk120-revB.dtso | 326 +++++++++++++
arch/arm/dts/zynqmp-sc-vpk180-revA.dtso | 371 ++++++++++++++
arch/arm/dts/zynqmp-sc-vpk180-revB.dtso | 337 +++++++++++++
8 files changed, 2067 insertions(+)
create mode 100644 arch/arm/dts/zynqmp-sc-vek280-revA.dtso
create mode 100644 arch/arm/dts/zynqmp-sc-vek280-revB.dtso
create mode 100644 arch/arm/dts/zynqmp-sc-vhk158-revA.dtso
create mode 100644 arch/arm/dts/zynqmp-sc-vn-p-b2197-00-revA.dtso
create mode 100644 arch/arm/dts/zynqmp-sc-vpk120-revB.dtso
create mode 100644 arch/arm/dts/zynqmp-sc-vpk180-revA.dtso
create mode 100644 arch/arm/dts/zynqmp-sc-vpk180-revB.dtso
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 3cde86d9eb38..a15ecd4bc70b 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -413,6 +413,13 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
zynqmp-mini-qspi.dtb \
zynqmp-sc-revB.dtb \
zynqmp-sc-revC.dtb \
+ zynqmp-sc-vek280-revA.dtbo \
+ zynqmp-sc-vek280-revB.dtbo \
+ zynqmp-sc-vhk158-revA.dtbo \
+ zynqmp-sc-vpk120-revB.dtbo \
+ zynqmp-sc-vpk180-revA.dtbo \
+ zynqmp-sc-vpk180-revB.dtbo \
+ zynqmp-sc-vn-p-b2197-00-revA.dtbo \
zynqmp-sm-k24-revA.dtb \
zynqmp-smk-k24-revA.dtb \
zynqmp-sm-k26-revA.dtb \
diff --git a/arch/arm/dts/zynqmp-sc-vek280-revA.dtso b/arch/arm/dts/zynqmp-sc-vek280-revA.dtso
new file mode 100644
index 000000000000..3320bbc11fcd
--- /dev/null
+++ b/arch/arm/dts/zynqmp-sc-vek280-revA.dtso
@@ -0,0 +1,230 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP VEK280 revA
+ *
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+ compatible = "xlnx,zynqmp-sc-vek280-revA", "xlnx,zynqmp-vek280-revA",
+ "xlnx,zynqmp-vek280", "xlnx,zynqmp";
+
+ vc7_xin: vc7-xin {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ };
+};
+
+&i2c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tca6416_u233: gpio@20 { /* u233 */
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller; /* interrupt not connected */
+ #gpio-cells = <2>;
+ gpio-line-names = "", "", "SFP_MOD_ABS", "SFP_TX_DISABLE", /* 0 - 3 */
+ "PMBUS2_INA226_ALERT", "", "", "", /* 4 - 7 */
+ "FMCP1_FMC_PRSNT_M2C_B", "", "FMCP1_FMCP_PRSNT_M2C_B", "", /* 10 - 13 */
+ "VCCINT_VRHOT_B", "8A34001_EXP_RST_B", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */
+ };
+
+ i2c-mux@74 { /* u33 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
+ pmbus_i2c: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* On connector J325 */
+ ir35215_46: pmic@46 { /* IR35215 - u152 */
+ compatible = "infineon,ir35215";
+ reg = <0x46>; /* i2c addr - 0x16 */
+ };
+ irps5401_47: pmic5401@47 { /* IRPS5401 - u160 */
+ compatible = "infineon,irps5401";
+ reg = <0x47>; /* i2c addr 0x17 */
+ };
+ irps5401_48: pmic@48 { /* IRPS5401 - u279 */
+ compatible = "infineon,irps5401";
+ reg = <0x48>; /* i2c addr 0x18 */
+ };
+ ir38064_49: regulator@49 { /* IR38064 - u295 */
+ compatible = "infineon,ir38064";
+ reg = <0x49>; /* i2c addr 0x19 */
+ };
+ irps5401_4c: pmic@4c { /* IRPS5401 - u167 */
+ compatible = "infineon,irps5401";
+ reg = <0x4c>; /* i2c addr 0x1c */
+ };
+ irps5401_4d: pmic@4d { /* IRPS5401 - u175 */
+ compatible = "infineon,irps5401";
+ reg = <0x4d>; /* i2c addr 0x1d */
+ };
+ ir38060_4e: regulator@4e { /* IR38060 - u282 */
+ compatible = "infineon,ir38060";
+ reg = <0x4e>; /* i2c addr 0x1e */
+ };
+ };
+ pmbus1_ina226_i2c: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* alerts coming to u233 and SC */
+ vccint: ina226@40 { /* u65 */
+ compatible = "ti,ina226";
+ reg = <0x40>;
+ shunt-resistor = <500>; /* r440 */
+ };
+ vcc_soc: ina226@41 { /* u161 */
+ compatible = "ti,ina226";
+ reg = <0x41>;
+ shunt-resistor = <500>; /* r1702 */
+ };
+ vcc_pmc: ina226@42 { /* u163 */
+ compatible = "ti,ina226";
+ reg = <0x42>;
+ shunt-resistor = <5000>; /* r382 */
+ };
+ vcc_ram: ina226@43 { /* u355 */
+ compatible = "ti,ina226";
+ reg = <0x43>;
+ shunt-resistor = <5000>; /* r2417 */
+ };
+ vcc_pslp: ina226@44 { /* u165 */
+ compatible = "ti,ina226";
+ reg = <0x44>;
+ shunt-resistor = <5000>; /* r1830 */
+ };
+ vcc_psfp: ina226@45 { /* u260 */
+ compatible = "ti,ina226";
+ reg = <0x45>;
+ shunt-resistor = <5000>; /* r2386 */
+ };
+ vcco_hdio: ina226@46 { /* u356 */
+ compatible = "ti,ina226";
+ reg = <0x46>;
+ shunt-resistor = <5000>; /* r2392 */
+ };
+ };
+ i2c@2 { /* NC */ /* FIXME maybe remove */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+ pmbus2_ina226_i2c: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ /* alerts coming to u233 and SC */
+ vccaux: ina226@40 { /* u166 */
+ compatible = "ti,ina226";
+ reg = <0x40>;
+ shunt-resistor = <5000>; /* r2384 */
+ };
+ vccaux_pmc: ina226@41 { /* u168 */
+ compatible = "ti,ina226";
+ reg = <0x41>;
+ shunt-resistor = <5000>; /* r2000 */
+ };
+ mgtavcc: ina226@42 { /* u265 */
+ compatible = "ti,ina226";
+ reg = <0x42>;
+ shunt-resistor = <5000>; /* r1829 */
+ };
+ vcc1v5: ina226@43 { /* u264 */
+ compatible = "ti,ina226";
+ reg = <0x43>;
+ shunt-resistor = <5000>; /* r2397 */
+ };
+ vcco_mio: ina226@45 { /* u172 */
+ compatible = "ti,ina226";
+ reg = <0x45>;
+ shunt-resistor = <5000>; /* r2401 */
+ };
+ mgtavtt: ina226@46 { /* u188 */
+ compatible = "ti,ina226";
+ reg = <0x46>;
+ shunt-resistor = <500>; /* r1384 */
+ };
+ vcco_502: ina226@47 { /* u174 */
+ compatible = "ti,ina226";
+ reg = <0x47>;
+ shunt-resistor = <5000>; /* r1994 */
+ };
+ mgtvccaux: ina226@48 { /* u176 */
+ compatible = "ti,ina226";
+ reg = <0x48>;
+ shunt-resistor = <5000>; /* r2384 */
+ };
+ vcc1v1_lp4: ina226@49 { /* u306 */
+ compatible = "ti,ina226";
+ reg = <0x49>;
+ shunt-resistor = <500>; /* r2064 */
+ };
+ vadj_fmc: ina226@4a { /* u281 */
+ compatible = "ti,ina226";
+ reg = <0x4a>;
+ shunt-resistor = <5000>; /* r2031 */
+ };
+ lpdmgtyavcc: ina226@4b { /* u177 */
+ compatible = "ti,ina226";
+ reg = <0x4b>;
+ shunt-resistor = <5000>; /* r2004 */
+ };
+ lpdmgtyavtt: ina226@4c { /* u309 */
+ compatible = "ti,ina226";
+ reg = <0x4c>;
+ shunt-resistor = <5000>; /* r1229 */
+ };
+ lpdmgtyvccaux: ina226@4d { /* u234 */
+ compatible = "ti,ina226";
+ reg = <0x4d>;
+ shunt-resistor = <5000>; /* r1679 */
+ };
+ };
+ i2c@4 { /* NC */ /* FIXME maybe remove */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ };
+ rc21008a_gtclk1: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ /* connector j374 */
+ /* rc21008a at 0x9 u299 */
+ vc7: clock-generator@9 {
+ compatible = "renesas,rc21008a";
+ reg = <0x9>;
+ #clock-cells = <1>;
+ clocks = <&vc7_xin>;
+ clock-names = "xin";
+ };
+ };
+ fmcp1_iic: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ /* to j51c */
+ };
+ sfp: i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ /* sfp+ connector J376 */
+ };
+ };
+};
diff --git a/arch/arm/dts/zynqmp-sc-vek280-revB.dtso b/arch/arm/dts/zynqmp-sc-vek280-revB.dtso
new file mode 100644
index 000000000000..a3983f330d07
--- /dev/null
+++ b/arch/arm/dts/zynqmp-sc-vek280-revB.dtso
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP VEK280 revB
+ *
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+#include "zynqmp-sc-vek280-revA.dtso"
+
+&{/} {
+ compatible = "xlnx,zynqmp-sc-vek280-revB", "xlnx,zynqmp-vek280-revB",
+ "xlnx,zynqmp-vek280", "xlnx,zynqmp";
+};
diff --git a/arch/arm/dts/zynqmp-sc-vhk158-revA.dtso b/arch/arm/dts/zynqmp-sc-vhk158-revA.dtso
new file mode 100644
index 000000000000..2ce69374c154
--- /dev/null
+++ b/arch/arm/dts/zynqmp-sc-vhk158-revA.dtso
@@ -0,0 +1,321 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP VHK158 revA
+ *
+ * (C) Copyright 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+ compatible = "xlnx,zynqmp-sc-vhk158-revA", "xlnx,zynqmp-vhk158-revA",
+ "xlnx,zynqmp-vhk158", "xlnx,zynqmp";
+
+ vc7_xin: vc7-xin {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ };
+};
+
+&i2c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tca6416_u233: gpio@20 { /* u233 */
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller; /* interrupt not connected */
+ #gpio-cells = <2>;
+ gpio-line-names = "", "", "QSFPDD1_MODSELL", "QSFPDD2_MODSELL", /* 0 - 3 */
+ "PMBUS2_INA226_ALERT", "", "", "", /* 4 - 7 */
+ "FMCP1_FMC_PRSNT_M2C_B", "", "FMCP1_FMCP_PRSNT_M2C_B", "", /* 10 - 13 */
+ "VCCINT_VRHOT_B", "8A34001_EXP_RST_B", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */
+ };
+
+ i2c-mux@74 { /* u33 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
+ pmbus_i2c: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* On connector J325 */
+ ir38064_41: regulator@41 { /* IR38064 - u294 */
+ compatible = "infineon,ir38064";
+ reg = <0x41>; /* i2c addr 0x11 */
+ };
+ irps5401_45: pmic5401@45 { /* IRPS5401 - u280 */
+ compatible = "infineon,irps5401";
+ reg = <0x45>; /* i2c addr 0x15 */
+ };
+ ir35221_46: pmic@46 { /* IR35221 - u152 */
+ compatible = "infineon,ir35221";
+ reg = <0x46>; /* i2c addr - 0x16 */
+ };
+ irps5401_47: pmic5401@47 { /* IRPS5401 - u160 */
+ compatible = "infineon,irps5401";
+ reg = <0x47>; /* i2c addr 0x17 */
+ };
+ irps5401_48: regulator@48 { /* IRPS5401 - u279 */
+ compatible = "infineon,irps5401";
+ reg = <0x48>; /* i2c addr 0x18 */
+ };
+ ir38164_49: regulator@49 { /* IR38164 - u295 */
+ compatible = "infineon,ir38164";
+ reg = <0x49>; /* i2c addr 0x19 */
+ };
+ ir38060_4a: regulator@4a { /* IR38060 - u259 */
+ compatible = "infineon,ir38164";
+ reg = <0x4a>; /* i2c addr 0x1a */
+ };
+ irps5401_4c: pmic@4c { /* IRPS5401 - u167 */
+ compatible = "infineon,irps5401";
+ reg = <0x4c>; /* i2c addr 0x1c */
+ };
+ irps5401_4d: pmic@4d { /* IRPS5401 - u175 */
+ compatible = "infineon,irps5401";
+ reg = <0x4d>; /* i2c addr 0x1d */
+ };
+ ir38060_4e: regulator@4e { /* IR38060 - u282 */
+ compatible = "infineon,ir38164";
+ reg = <0x4e>; /* i2c addr 0x1e */
+ };
+ };
+ pmbus1_ina226_i2c: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* FIXME check alerts coming to SC */
+ vccint: ina226@40 { /* u65 */
+ compatible = "ti,ina226";
+ reg = <0x40>;
+ shunt-resistor = <500>; /* R440 */
+ };
+ vcc_soc: ina226@41 { /* u161 */
+ compatible = "ti,ina226";
+ reg = <0x41>;
+ shunt-resistor = <500>; /* R1702 */
+ };
+ vcc_pmc: ina226@42 { /* u163 */
+ compatible = "ti,ina226";
+ reg = <0x42>;
+ shunt-resistor = <5000>; /* R382 */
+ };
+ vcc_ram: ina226@43 { /* u5 */
+ compatible = "ti,ina226";
+ reg = <0x43>;
+ shunt-resistor = <500>; /* R121 */
+ };
+ vcc_pslp: ina226@44 { /* u165 */
+ compatible = "ti,ina226";
+ reg = <0x44>;
+ shunt-resistor = <5000>; /* R1830 */
+ };
+ vcc_psfp: ina226@45 { /* u260 */
+ compatible = "ti,ina226";
+ reg = <0x45>;
+ shunt-resistor = <5000>; /* R1834 */
+ };
+ vcco_hbm: ina226@46 { /* u164 */
+ compatible = "ti,ina226";
+ reg = <0x46>;
+ shunt-resistor = <500>; /* R2056 */
+ };
+ vcc_hbm: ina226@47 { /* u307 */
+ compatible = "ti,ina226";
+ reg = <0x47>;
+ shunt-resistor = <500>; /* R2068 */
+ };
+ vccaux_hbm: ina226@48 { /* u308 */
+ compatible = "ti,ina226";
+ reg = <0x48>;
+ shunt-resistor = <5000>; /* R2019 */
+ };
+ };
+ i2c@2 { /* NC */ /* FIXME maybe remove */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+ pmbus2_ina226_i2c: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ /* FIXME check alerts coming to SC */
+ vccaux: ina226@40 { /* u166 */
+ compatible = "ti,ina226";
+ reg = <0x40>;
+ shunt-resistor = <5000>; /* R2060 */
+ };
+ vccaux_pmc: ina226@41 { /* u168 */
+ compatible = "ti,ina226";
+ reg = <0x41>;
+ shunt-resistor = <500>; /* R2000 */
+ };
+ mgtavcc: ina226@42 { /* u265 */
+ compatible = "ti,ina226";
+ reg = <0x42>;
+ shunt-resistor = <500>; /* R1829 */
+ };
+ vcc1v5: ina226@43 { /* u264 */
+ compatible = "ti,ina226";
+ reg = <0x43>;
+ shunt-resistor = <500>; /* R1221 */
+ };
+ vcco_mio: ina226@45 { /* u172 */
+ compatible = "ti,ina226";
+ reg = <0x45>;
+ shunt-resistor = <500>; /* R2015 */
+ };
+ mgtavtt: ina226@46 { /* u188 */
+ compatible = "ti,ina226";
+ reg = <0x46>;
+ shunt-resistor = <500>; /* R1384 */
+ };
+ vcco_502: ina226@47 { /* u174 */
+ compatible = "ti,ina226";
+ reg = <0x47>;
+ shunt-resistor = <500>; /* R1994 */
+ };
+ mgtvccaux: ina226@48 { /* u176 */
+ compatible = "ti,ina226";
+ reg = <0x48>;
+ shunt-resistor = <500>; /* R1232 */
+ };
+ vcc1v2_rdimm: ina226@49 { /* u306 */
+ compatible = "ti,ina226";
+ reg = <0x49>;
+ shunt-resistor = <500>; /* R2064 */
+ };
+ vadj_fmc: ina226@4a { /* u281 */
+ compatible = "ti,ina226";
+ reg = <0x4a>;
+ shunt-resistor = <5000>; /* R2031 */
+ };
+ lpdmgtyavcc: ina226@4b { /* u177 */
+ compatible = "ti,ina226";
+ reg = <0x4b>;
+ shunt-resistor = <500>; /* R2004 */
+ };
+ lpdmgtyavtt: ina226@4c { /* u309 */
+ compatible = "ti,ina226";
+ reg = <0x4c>;
+ shunt-resistor = <500>; /* R1229 */
+ };
+ lpdmgtyvccaux: ina226@4d { /* u234 */
+ compatible = "ti,ina226";
+ reg = <0x4d>;
+ shunt-resistor = <500>; /* R1679 */
+ };
+ };
+ i2c@4 { /* NC */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ };
+ rc21008a_gtclk1: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ vc7_1: clock-generator@9 {
+ compatible = "renesas,rc21008a";
+ clock-output-names = "rc21008a-0";
+ reg = <0x9>;
+ #clock-cells = <1>;
+ clocks = <&vc7_xin>;
+ clock-names = "xin";
+ };
+ /* i2c@9 - U299 */
+ };
+ rc21008a_gtclk2: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ vc7_2: clock-generator@9 {
+ compatible = "renesas,rc21008a";
+ clock-output-names = "rc21008a-1";
+ reg = <0x9>;
+ #clock-cells = <1>;
+ clocks = <&vc7_xin>;
+ clock-names = "xin";
+ };
+ /* i2c@9 - U300 */
+ };
+ sync_8a34001: i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ /* U219 - i2c address UNKNOWN */
+ };
+ };
+};
+
+&i2c1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c-mux@74 { /* u35 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */
+ ddr4_dimm0: i2c@0 { /* wired but NC */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+ fmcp1_i2c: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* FIXME connection to Samtec J51C */
+ /* expected eeprom 0x50 SE cards */
+ };
+ qsfp1_i2c: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ /* J350 connector */
+ };
+ qsfp2_i2c: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ /* J351 connector */
+ };
+ qsfp3_i2c: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ /* J352 connector */
+ };
+ qsfp4_i2c: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ /* J353 connector */
+ };
+ qsfpdd_i2c: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ /* J1/J2 connectors */
+ };
+ ddr4_dimm1: i2c@7 { /* wired but NC */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ };
+ };
+};
diff --git a/arch/arm/dts/zynqmp-sc-vn-p-b2197-00-revA.dtso b/arch/arm/dts/zynqmp-sc-vn-p-b2197-00-revA.dtso
new file mode 100644
index 000000000000..5333767361f5
--- /dev/null
+++ b/arch/arm/dts/zynqmp-sc-vn-p-b2197-00-revA.dtso
@@ -0,0 +1,460 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP VN-P-B2197-00 (Tenzing2)
+ *
+ * Copyright (C) 2022 - 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ compatible = "xlnx,zynqmp-sc-vn-p-b2197-revA",
+ "xlnx,zynqmp-sc-vn-p-b2197", "xlnx,zynqmp";
+
+ aliases {
+ nvmem1 = &x_prc_eeprom;
+ };
+
+ ina226-u1700 {
+ compatible = "iio-hwmon";
+ io-channels = <&vcc_ram_ina 0>, <&vcc_ram_ina 1>, <&vcc_ram_ina 2>;
+ };
+ ina226-u1732 {
+ compatible = "iio-hwmon";
+ io-channels = <&vcc_lpd_ina 0>, <&vcc_lpd_ina 1>, <&vcc_lpd_ina 2>;
+ };
+ ina226-u1733 {
+ compatible = "iio-hwmon";
+ io-channels = <&vccaux_ina 0>, <&vccaux_ina 1>, <&vccaux_ina 2>;
+ };
+ ina226-u1736 {
+ compatible = "iio-hwmon";
+ io-channels = <&vccaux_lpd_ina 0>, <&vccaux_lpd_ina 1>, <&vccaux_lpd_ina 2>;
+ };
+ ina226-u1737 {
+ compatible = "iio-hwmon";
+ io-channels = <&vcco_500_ina 0>, <&vcco_500_ina 1>, <&vcco_500_ina 2>;
+ };
+ ina226-u1739 {
+ compatible = "iio-hwmon";
+ io-channels = <&vcco_501_ina 0>, <&vcco_501_ina 1>, <&vcco_501_ina 2>;
+ };
+ ina226-u1741 {
+ compatible = "iio-hwmon";
+ io-channels = <&vcco_502_ina 0>, <&vcco_502_ina 1>, <&vcco_502_ina 2>;
+ };
+ ina226-u1743 {
+ compatible = "iio-hwmon";
+ io-channels = <&vcco_503_ina 0>, <&vcco_503_ina 1>, <&vcco_503_ina 2>;
+ };
+ ina226-u1745 {
+ compatible = "iio-hwmon";
+ io-channels = <&vcco_700_ina 0>, <&vcco_700_ina 1>, <&vcco_700_ina 2>;
+ };
+ ina226-u1747 {
+ compatible = "iio-hwmon";
+ io-channels = <&vcco_706_ina 0>, <&vcco_706_ina 1>, <&vcco_706_ina 2>;
+ };
+ ina226-u1750 {
+ compatible = "iio-hwmon";
+ io-channels = <>yp_avcc_ina 0>, <>yp_avcc_ina 1>, <>yp_avcc_ina 2>;
+ };
+ ina226-u1752 {
+ compatible = "iio-hwmon";
+ io-channels = <>yp_avtt_ina 0>, <>yp_avtt_ina 1>, <>yp_avtt_ina 2>;
+ };
+ ina226-u1754 {
+ compatible = "iio-hwmon";
+ io-channels = <>yp_avccaux_ina 0>, <>yp_avccaux_ina 1>, <>yp_avccaux_ina 2>;
+ };
+ ina226-u1756 {
+ compatible = "iio-hwmon";
+ io-channels = <>m_avcc_ina 0>, <>m_avcc_ina 1>, <>m_avcc_ina 2>;
+ };
+ ina226-u1758 {
+ compatible = "iio-hwmon";
+ io-channels = <>m_avtt_ina 0>, <>m_avtt_ina 1>, <>m_avtt_ina 2>;
+ };
+ ina226-u1760 {
+ compatible = "iio-hwmon";
+ io-channels = <>m_avccaux_ina 0>, <>m_avccaux_ina 1>, <>m_avccaux_ina 2>;
+ };
+
+ /* sc_vpk180_axi_iic_0_0: i2c@80050000 - UNUSED NOW */ /* SI5332 */
+
+ /* Connect to J212G pin G29/G30 - sysmon connector */
+ /* sc_vpk180_axi_iic_1_0: i2c@80060000 */ /* SYSMON */
+
+ /* FIXME Fan control via u1702 - max6643 and mux via J1703 - not SW controllable - via EMIO */
+};
+
+&i2c1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* u97 eeprom at 0x54 described in sc-revB - WP protection via BOARD_EEPROM_WP - J1801 */
+ /* DC/SE eeprom at 0x52 */
+ x_prc_eeprom: eeprom@52 { /* u4 - DC card identification - possible WP */
+ compatible = "atmel,24c02";
+ reg = <0x52>;
+ bootph-all;
+ };
+
+ x_prc_tca9534: gpio@22 { /* u5 */
+ compatible = "nxp,pca9534";
+ reg = <0x22>;
+ gpio-controller; /* IRQ not connected */
+ #gpio-cells = <2>;
+ gpio-line-names = "xprc_sw_1", "xprc_sw_2", "xprc_sw_3", "xprc_sw_4",
+ "", "", "", "";
+ gtr-sel0 {
+ gpio-hog;
+ gpios = <0 0>;
+ input; /* FIXME add meaning */
+ line-name = "xprc_sw_1";
+ };
+ gtr-sel1 {
+ gpio-hog;
+ gpios = <1 0>;
+ input; /* FIXME add meaning */
+ line-name = "xprc_sw_1";
+ };
+ gtr-sel2 {
+ gpio-hog;
+ gpios = <2 0>;
+ input; /* FIXME add meaning */
+ line-name = "xprc_sw_1";
+ };
+ gtr-sel3 {
+ gpio-hog;
+ gpios = <3 0>;
+ input; /* FIXME add meaning */
+ line-name = "xprc_sw_1";
+ };
+ };
+
+ /* FMC eeproms at 0x50/0x51 */
+ /* via j3/j5 to 0x68 to u32/9FGV1006C
+
+ /* i2c_main_1 - u147 - j157 - disable translation, add 8 */
+ /* J1 - OE for u43@55 + 8 - 161,132813MHz - QSFP56G_0 */
+ qsfp56g_0_clk: clock-controller@5d {
+ compatible = "renesas,proxo-xp";
+ reg = <0x5d>;
+ #clock-cells = <0>;
+ clock-output-names = "qsfp56g_0_clk";
+ };
+
+ /* J2 - OE for u41@57 + 8 - 322,265625MHz - QSFP56G_1 */
+ qsfp56g_1_clk: clock-controller@5f {
+ compatible = "renesas,proxo-xp";
+ reg = <0x5f>;
+ #clock-cells = <0>;
+ clock-output-names = "qsfp56g_1_clk";
+ };
+
+ /* J81 - OE for u115@50 + 8 - 320MHz - LPDDR5_C0 */
+ lpddr5_c0_clk: clock-controller@58 {
+ compatible = "renesas,proxo-xp";
+ reg = <0x58>;
+ #clock-cells = <0>;
+ clock-output-names = "lpddr5_c0_clk";
+ };
+
+ /* i2c_main_2 - u148 - j122 - disable translation, add 9 */
+ /* J112 - OE for u63@50 + 9 - 320MHz - LPDDR5_C2 */
+ lpddr5_c2_clk: clock-controller@59 {
+ compatible = "renesas,proxo-xp";
+ reg = <0x59>;
+ #clock-cells = <0>;
+ clock-output-names = "lpddr5_c2_clk";
+ };
+
+ /* i2c_main_3 - u149 - j154 - disable translation, add 6 */
+ /* J78 - OE for u116@50 + 6 - 320MHz - DDR5_UDIMM */
+ ddr5_udimm_clk: clock-controller@56 {
+ compatible = "renesas,proxo-xp";
+ reg = <0x56>;
+ #clock-cells = <0>;
+ clock-output-names = "ddr5_udimm_clk";
+ };
+
+ /* i2c_main_4 - u150 - j146 - disable translation, add 5 */
+ /* J107 - OE for u39@50 + 5 - 33,3333MHz - PS_REFCLK */
+ ps_refclk: clock-controller@55 {
+ compatible = "renesas,proxo-xp";
+ reg = <0x55>;
+ #clock-cells = <0>;
+ clock-output-names = "ps_refclk";
+ };
+
+ /* i2c_main_5 - u1782 - j1798 - disable translation, add 7 */
+ /* J77 - OE for u1783@50 + 7 - 320MHz - DDR4 */
+ ddr4_clk: clock-controller@57 {
+ compatible = "renesas,proxo-xp";
+ reg = <0x57>;
+ #clock-cells = <0>;
+ clock-output-names = "ddr4_clk";
+ };
+
+ /* LTC4316 - not wired XORH/XORL - FIXME */
+ /* J3 gate - FIXME should be connected for SW handling */
+ /* i2c_main_1 bus */
+ i2c1_u32: clock-controller@68 {
+ compatible = "renesas,9fgv1006";
+ reg = <0x68>;
+ };
+
+ /* J71 - selection to LP_I2C_SCL_J or LP_I2C_PMC_SCL_J */
+ /* J70 - selection to LP_I2C_SDA_J or LP_I2C_PMC_SDA_J */
+ /* this should be SW controlable too */
+};
+
+&i2c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* Via j11/j12 can also go to u17/IML3112 - 1:2 multiplexer - also accessed from Versal NET */
+ /* Connection DDR5_UDIMM - SPD can be from 0x50-0x57 */
+ /* FIXME gpio should handle SYSCTLR_PMBUS_ALERT and also INA226_PMBUS_ALERT */
+
+ /* ina226_pmbus - J55 - disable INA226_PMBUS */
+ vcc_ram_ina: power-monitor@40 { /* u1700 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ reg = <0x40>;
+ shunt-resistor = <1000>; /* R1996 */
+ };
+
+ vcc_lpd_ina: power-monitor@41 { /* u1732 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ reg = <0x41>;
+ shunt-resistor = <1000>; /* R2017 */
+ };
+
+ vccaux_ina: power-monitor@42 { /* u1733 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ reg = <0x42>;
+ shunt-resistor = <1000>; /* R2037 */
+ };
+
+ vccaux_lpd_ina: power-monitor@43 { /* u1736 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ reg = <0x43>;
+ shunt-resistor = <1000>; /* R2057 */
+ };
+
+ vcco_500_ina: power-monitor@44 { /* u1737 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ reg = <0x44>;
+ shunt-resistor = <1000>; /* R2069 */
+ };
+
+ vcco_501_ina: power-monitor@45 { /* u1739 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ reg = <0x45>;
+ shunt-resistor = <1000>; /* R2089 */
+ };
+
+ vcco_502_ina: power-monitor@46 { /* u1741 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ reg = <0x46>;
+ shunt-resistor = <1000>; /* R2108 */
+ };
+
+ vcco_503_ina: power-monitor@47 { /* u1743 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ reg = <0x47>;
+ shunt-resistor = <1000>; /* R2127 */
+ };
+
+ vcco_700_ina: power-monitor@48 { /* u1745 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ reg = <0x48>;
+ shunt-resistor = <1000>; /* R2154 */
+ };
+
+ vcco_706_ina: power-monitor@49 { /* u1747 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ reg = <0x49>;
+ shunt-resistor = <1000>; /* R2175 */
+ };
+
+ gtyp_avcc_ina: power-monitor@4a { /* u1750 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ reg = <0x4a>;
+ shunt-resistor = <1000>; /* R2195 */
+ };
+
+ gtyp_avtt_ina: power-monitor@4b { /* u1752 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ reg = <0x4b>;
+ shunt-resistor = <1000>; /* R2215 */
+ };
+
+ gtyp_avccaux_ina: power-monitor@4c { /* u1754 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ reg = <0x4c>;
+ shunt-resistor = <5000>; /* R2235 */
+ };
+
+ gtm_avcc_ina: power-monitor@4d { /* u1756 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ reg = <0x4d>;
+ shunt-resistor = <1000>; /* R2256 */
+ };
+
+ gtm_avtt_ina: power-monitor@4e { /* u1758 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ reg = <0x4e>;
+ shunt-resistor = <1000>; /* R2276 */
+ };
+
+ gtm_avccaux_ina: power-monitor@4f { /* u1760 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ reg = <0x4f>;
+ shunt-resistor = <5000>; /* R2296 */
+ };
+
+ /* pmbus - J50 - disable main PMBUS - also going to j132 */
+ vcc_ram: regulator@a { /* u1730 */
+ compatible = "ti,tps544b25";
+ reg = <0xa>;
+ };
+
+ vcc_lpd: regulator@b { /* u1731 */
+ compatible = "ti,tps544b25";
+ reg = <0xb>;
+ };
+
+ vccaux: regulator@1a { /* u1734 */
+ compatible = "ti,tps544b25";
+ reg = <0x1a>;
+ };
+
+ vcco_503: regulator@12 { /* u1744 */
+ compatible = "ti,tps546b24a";
+ reg = <0x12>;
+ };
+
+ vcco_700: regulator@16 { /* u1746 */
+ compatible = "ti,tps544b25";
+ reg = <0x16>;
+ };
+
+ vcco_706: regulator@17 { /* u1748 */
+ compatible = "ti,tps544b25";
+ reg = <0x17>;
+ };
+
+ gtm_avcc: regulator@23 { /* u1755 */
+ compatible = "ti,tps544b25";
+ reg = <0x23>;
+ };
+
+ gtm_avtt: regulator@24 { /* u1757 */
+ compatible = "ti,tps544b25";
+ reg = <0x24>;
+ };
+
+ gtm_avccaux: regulator@25 { /* u1759 */
+ compatible = "ti,tps544b25";
+ reg = <0x25>;
+ };
+
+ util_1v8: regulator@15 { /* u1765 */
+ compatible = "ti,tps544b25";
+ reg = <0x15>;
+ };
+
+ ucd90320: power-sequencer@73 { /* u1768 */
+ compatible = "ti,ucd90320";
+ reg = <0x73>;
+ };
+
+ /* EXT_PMBUS main - J10 - disable extended PMBUS */
+ vccint: tps53681@60 { /* u1712 - J1770 reset jumper */
+ compatible = "ti,tps53681", "ti,tps53679";
+ reg = <0x60>;
+ /* vccint, vcc_cpm5n */
+ };
+
+ vcc_io_soc: tps53681@61 { /* u1721 - J1772 reset jumper */
+ compatible = "ti,tps53681", "ti,tps53679";
+ reg = <0x61>;
+ /* vcc_io_soc, vcc_fpd */
+ };
+
+ vccaux_lpd: regulator@d { /* u1735 */
+ compatible = "ti,tps544b25";
+ reg = <0xd>;
+ };
+
+ vcco_500: regulator@13 { /* u1738 */
+ compatible = "ti,tps546b24a";
+ reg = <0x13>;
+ };
+
+ vcco_501: regulator@10 { /* u1740 */
+ compatible = "ti,tps546b24a";
+ reg = <0x10>;
+ };
+
+ vcco_502: regulator@11 { /* u1742 */
+ compatible = "ti,tps546b24a";
+ reg = <0x11>;
+ };
+
+ gtyp_avcc: regulator@20 { /* u1749 */
+ compatible = "ti,tps544b25";
+ reg = <0x20>;
+ };
+
+ gtyp_avtt: regulator@21 { /* u1751 */
+ compatible = "ti,tps544b25";
+ reg = <0x21>;
+ };
+
+ gtyp_avccaux: regulator@22 { /* u1753 */
+ compatible = "ti,tps544b25";
+ reg = <0x22>;
+ };
+
+ lp5_vdd1_1v8: regulator@e { /* u1761 - FIXME no ina226 */
+ compatible = "ti,tps544b25";
+ reg = <0xe>;
+ };
+
+ lp5_vdd2_1v05: regulator@f { /* u1762 - FIXME no ina226 */
+ compatible = "ti,tps544b25";
+ reg = <0xf>;
+ };
+
+ lp5_vddq_0v5: regulator@14 { /* u1763 - FIXME no ina226 */
+ compatible = "ti,tps546b24a";
+ reg = <0x14>;
+ };
+};
diff --git a/arch/arm/dts/zynqmp-sc-vpk120-revB.dtso b/arch/arm/dts/zynqmp-sc-vpk120-revB.dtso
new file mode 100644
index 000000000000..750bc39139cc
--- /dev/null
+++ b/arch/arm/dts/zynqmp-sc-vpk120-revB.dtso
@@ -0,0 +1,326 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP VPK120 revB
+ *
+ * (C) Copyright 2021 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+/dts-v1/;
+/plugin/;
+
+
+&{/} {
+ compatible = "xlnx,zynqmp-sc-vpk120-revB", "xlnx,zynqmp-vpk120-revB",
+ "xlnx,zynqmp-vpk120", "xlnx,zynqmp";
+};
+
+&i2c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tca6416_u233: gpio@20 { /* u233 */
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller; /* interrupt not connected */
+ #gpio-cells = <2>;
+ gpio-line-names = "", "", "QSFPDD1_MODSELL", "QSFPDD2_MODSELL", /* 0 - 3 */
+ "PMBUS2_INA226_ALERT", "", "", "", /* 4 - 7 */
+ "FMCP1_FMC_PRSNT_M2C_B", "", "FMCP1_FMCP_PRSNT_M2C_B", "", /* 10 - 13 */
+ "VCCINT_VRHOT_B", "8A34001_EXP_RST_B", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */
+ };
+
+ i2c-mux@74 { /* u33 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
+ pmbus_i2c: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* On connector J325 */
+ ir38060_41: regulator@41 { /* IR38060 - u259 */
+ compatible = "infineon,ir38060", "infineon,ir38064";
+ reg = <0x41>; /* i2c addr 0x11 */
+ };
+ ir38164_43: regulator@43 { /* IR38164 - u13 */
+ compatible = "infineon,ir38164";
+ reg = <0x43>; /* i2c addr 0x13 */
+ };
+ ir35221_46: pmic@46 { /* IR35221 - u152 */
+ compatible = "infineon,ir35221";
+ reg = <0x46>; /* i2c addr - 0x16 */
+ };
+ irps5401_47: pmic5401@47 { /* IRPS5401 - u160 */
+ compatible = "infineon,irps5401";
+ reg = <0x47>; /* i2c addr 0x17 */
+ };
+ ir38164_49: regulator@49 { /* IR38164 - u189 */
+ compatible = "infineon,ir38164";
+ reg = <0x49>; /* i2c addr 0x19 */
+ };
+ irps5401_4c: pmic@4c { /* IRPS5401 - u167 */
+ compatible = "infineon,irps5401";
+ reg = <0x4c>; /* i2c addr 0x1c */
+ };
+ irps5401_4d: pmic@4d { /* IRPS5401 - u175 */
+ compatible = "infineon,irps5401";
+ reg = <0x4d>; /* i2c addr 0x1d */
+ };
+ ir38164_4e: regulator@4e { /* IR38164 - u185 */
+ compatible = "infineon,ir38164";
+ reg = <0x4e>; /* i2c addr 0x1e */
+ };
+ ir38164_4f: regulator@4f { /* IR38164 - u187 */
+ compatible = "infineon,ir38164";
+ reg = <0x4f>; /* i2c addr 0x1f */
+ };
+ };
+ pmbus1_ina226_i2c: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* FIXME check alerts coming to SC */
+ vccint: ina226@40 { /* u65 */
+ compatible = "ti,ina226";
+ reg = <0x40>;
+ shunt-resistor = <5000>;
+ };
+ vcc_soc: ina226@41 { /* u161 */
+ compatible = "ti,ina226";
+ reg = <0x41>;
+ shunt-resistor = <5000>;
+ };
+ vcc_pmc: ina226@42 { /* u163 */
+ compatible = "ti,ina226";
+ reg = <0x42>;
+ shunt-resistor = <5000>;
+ };
+ vcc_ram: ina226@43 { /* u5 */
+ compatible = "ti,ina226";
+ reg = <0x43>;
+ shunt-resistor = <5000>;
+ };
+ vcc_pslp: ina226@44 { /* u165 */
+ compatible = "ti,ina226";
+ reg = <0x44>;
+ shunt-resistor = <5000>;
+ };
+ vcc_psfp: ina226@45 { /* u164 */
+ compatible = "ti,ina226";
+ reg = <0x45>;
+ shunt-resistor = <5000>;
+ };
+ };
+ i2c@2 { /* NC */ /* FIXME maybe remove */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+ pmbus2_ina226_i2c: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ /* FIXME check alerts coming to SC */
+ vccaux: ina226@40 { /* u166 */
+ compatible = "ti,ina226";
+ reg = <0x40>;
+ shunt-resistor = <5000>;
+ };
+ vccaux_pmc: ina226@41 { /* u168 */
+ compatible = "ti,ina226";
+ reg = <0x41>;
+ shunt-resistor = <5000>;
+ };
+ mgtavcc: ina226@42 { /* u265 */
+ compatible = "ti,ina226";
+ reg = <0x42>;
+ shunt-resistor = <5000>;
+ };
+ vcc1v5: ina226@43 { /* u264 */
+ compatible = "ti,ina226";
+ reg = <0x43>;
+ shunt-resistor = <5000>;
+ };
+ vcco_mio: ina226@45 { /* u172 */
+ compatible = "ti,ina226";
+ reg = <0x45>;
+ shunt-resistor = <5000>;
+ };
+ mgtavtt: ina226@46 { /* u188 */
+ compatible = "ti,ina226";
+ reg = <0x46>;
+ shunt-resistor = <2000>;
+ };
+ vcco_502: ina226@47 { /* u174 */
+ compatible = "ti,ina226";
+ reg = <0x47>;
+ shunt-resistor = <5000>;
+ };
+ mgtvccaux: ina226@48 { /* u176 */
+ compatible = "ti,ina226";
+ reg = <0x48>;
+ shunt-resistor = <5000>;
+ };
+ vcc1v1_lp4: ina226@49 { /* u186 */
+ compatible = "ti,ina226";
+ reg = <0x49>;
+ shunt-resistor = <2000>;
+ };
+ vadj_fmc: ina226@4a { /* u184 */
+ compatible = "ti,ina226";
+ reg = <0x4a>;
+ shunt-resistor = <2000>;
+ };
+ lpdmgtyavcc: ina226@4b { /* u177 */
+ compatible = "ti,ina226";
+ reg = <0x4b>;
+ shunt-resistor = <5000>;
+ };
+ lpdmgtyavtt: ina226@4c { /* u260 */
+ compatible = "ti,ina226";
+ reg = <0x4c>;
+ shunt-resistor = <2000>;
+ };
+ lpdmgtyvccaux: ina226@4d { /* u234 */
+ compatible = "ti,ina226";
+ reg = <0x4d>;
+ shunt-resistor = <5000>;
+ };
+ };
+ i2c@4 { /* NC */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ };
+ i2c@5 { /* NC */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ };
+ user_si570: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ user_si570_1: clock-generator@5f { /* USER C0 SI570 - u205 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5f>;
+ temperature-stability = <50>;
+ factory-fout = <100000000>;
+ clock-frequency = <100000000>;
+ clock-output-names = "fmc_si570";
+ silabs,skip-recall;
+ };
+
+ };
+ /* 7 unused */
+ };
+};
+
+&i2c1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c-mux@74 { /* u35 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */
+ ref_clk_i2c: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ ref_clk: clock-generator@5d { /* u32 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>;
+ temperature-stability = <50>;
+ factory-fout = <33333333>;
+ clock-frequency = <33333333>;
+ clock-output-names = "ref_clk";
+ silabs,skip-recall;
+ };
+ };
+ fmcp1_i2c: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* FIXME connection to Samtec J51C */
+ /* expected eeprom 0x50 SE cards */
+ };
+ i2c@2 { /* NC - FIXME */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+ lpddr4_si570_clk3_i2c: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ lpddr4_clk3: clock-generator@60 { /* u4 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x60>;
+ temperature-stability = <50>;
+ factory-fout = <200000000>;
+ clock-frequency = <200000000>;
+ clock-output-names = "lpddr4_clk3";
+ silabs,skip-recall;
+ };
+ };
+ lpddr4_si570_clk2_i2c: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ lpddr4_clk2: clock-generator@60 { /* u3 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x60>;
+ temperature-stability = <50>;
+ factory-fout = <200000000>;
+ clock-frequency = <200000000>;
+ clock-output-names = "lpddr4_clk2";
+ silabs,skip-recall;
+ };
+ };
+ lpddr4_si570_clk1_i2c: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ lpddr4_clk1: clock-generator@60 { /* u248 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x60>;
+ temperature-stability = <50>;
+ factory-fout = <200000000>;
+ clock-frequency = <200000000>;
+ clock-output-names = "lpddr4_clk1";
+ silabs,skip-recall;
+ };
+ };
+ qsfpdd_i2c: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ /* J1/J2 connectors */
+ };
+ idt8a34001_i2c: i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ /* Via J310 connector */
+ idt_8a34001: phc@5b {
+ compatible = "idt,8a34001"; /* u219B */
+ reg = <0x5b>; /* FIXME not in schematics */
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/zynqmp-sc-vpk180-revA.dtso b/arch/arm/dts/zynqmp-sc-vpk180-revA.dtso
new file mode 100644
index 000000000000..551341f31bd1
--- /dev/null
+++ b/arch/arm/dts/zynqmp-sc-vpk180-revA.dtso
@@ -0,0 +1,371 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP VPK180 revA
+ *
+ * (C) Copyright 2021 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+/dts-v1/;
+/plugin/;
+
+
+&{/} {
+ compatible = "xlnx,zynqmp-sc-vpk180-revA", "xlnx,zynqmp-vpk180-revA",
+ "xlnx,zynqmp-vpk180", "xlnx,zynqmp";
+};
+
+&i2c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tca6416_u233: gpio@20 { /* u233 */
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller; /* interrupt not connected */
+ #gpio-cells = <2>;
+ gpio-line-names = "QSFPDD1_MODSELL", "QSFPDD2_MODSELL", "QSFPDD3_MODSELL", "QSFPDD4_MODSELL", /* 0 - 3 */
+ "PMBUS2_INA226_ALERT", "QSFPDD5_MODSELL", "QSFPDD6_MODSELL", "", /* 4 - 7 */
+ "FMCP1_FMC_PRSNT_M2C_B", "", "FMCP1_FMCP_PRSNT_M2C_B", "UTIL_3V3_VRHOT_B", /* 10 - 13 */
+ "VCCINT_VRHOT_B", "8A34001_EXP_RST_B", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */
+ };
+
+ i2c-mux@74 { /* u33 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
+ pmbus_i2c: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* On connector J325 */
+ ir38060_41: regulator@41 { /* IR38060 - u259 */
+ compatible = "infineon,ir38060", "infineon,ir38064";
+ reg = <0x41>; /* i2c addr 0x11 */
+ };
+ ir35221_45: pmic@45 { /* IR35221 - u291 */
+ compatible = "infineon,ir35221";
+ reg = <0x45>; /* i2c addr - 0x15 */
+ };
+ ir35221_46: pmic@46 { /* IR35221 - u152 */
+ compatible = "infineon,ir35221";
+ reg = <0x46>; /* i2c addr - 0x16 */
+ };
+ irps5401_47: pmic5401@47 { /* IRPS5401 - u160 */
+ compatible = "infineon,irps5401";
+ reg = <0x47>; /* i2c addr 0x17 */
+ };
+ irps5401_48: pmic@48 { /* IRPS5401 - u295 */
+ compatible = "infineon,irps5401";
+ reg = <0x48>; /* i2c addr 0x18 */
+ };
+ ir38164_49: regulator@49 { /* IR38164 - u189 */
+ compatible = "infineon,ir38164";
+ reg = <0x49>; /* i2c addr 0x19 */
+ };
+ irps5401_4c: pmic@4c { /* IRPS5401 - u167 */
+ compatible = "infineon,irps5401";
+ reg = <0x4c>; /* i2c addr 0x1c */
+ };
+ irps5401_4d: pmic@4d { /* IRPS5401 - u175 */
+ compatible = "infineon,irps5401";
+ reg = <0x4d>; /* i2c addr 0x1d */
+ };
+ ir38164_4e: regulator@4e { /* IR38164 - u185 */
+ compatible = "infineon,ir38164";
+ reg = <0x4e>; /* i2c addr 0x1e */
+ };
+ ir38164_4f: regulator@4f { /* IR38164 - u187 */
+ compatible = "infineon,ir38164";
+ reg = <0x4f>; /* i2c addr 0x1f */
+ };
+ };
+ pmbus1_ina226_i2c: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* FIXME check alerts coming to SC */
+ vccint: ina226@40 { /* u65 */
+ compatible = "ti,ina226";
+ reg = <0x40>;
+ shunt-resistor = <5000>; /* r440 */
+ };
+ vcc_soc: ina226@41 { /* u161 */
+ compatible = "ti,ina226";
+ reg = <0x41>;
+ shunt-resistor = <5000>; /* r2174 */
+ };
+ vcc_pmc: ina226@42 { /* u163 */
+ compatible = "ti,ina226";
+ reg = <0x42>;
+ shunt-resistor = <5000>; /* r1214 */
+ };
+ vcc_ram: ina226@43 { /* u5 */
+ compatible = "ti,ina226";
+ reg = <0x43>;
+ shunt-resistor = <5000>; /* r2108 */
+ };
+ vcc_pslp: ina226@44 { /* u165 */
+ compatible = "ti,ina226";
+ reg = <0x44>;
+ shunt-resistor = <5000>; /* r1830 */
+ };
+ vcc_psfp: ina226@45 { /* u164 */
+ compatible = "ti,ina226";
+ reg = <0x45>;
+ shunt-resistor = <5000>; /* r2086 */
+ };
+ };
+ i2c@2 { /* NC */ /* FIXME maybe remove */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+ pmbus2_ina226_i2c: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ /* FIXME check alerts coming to SC */
+ vccaux: ina226@40 { /* u166 */
+ compatible = "ti,ina226";
+ reg = <0x40>;
+ shunt-resistor = <2000>; /* r2109 */
+ };
+ vccaux_pmc: ina226@41 { /* u168 */
+ compatible = "ti,ina226";
+ reg = <0x41>;
+ shunt-resistor = <5000>; /* r1246 */
+ };
+ mgtavcc: ina226@42 { /* u265 */
+ compatible = "ti,ina226";
+ reg = <0x42>;
+ shunt-resistor = <5000>; /* r1829 */
+ };
+ vcc1v5: ina226@43 { /* u264 */
+ compatible = "ti,ina226";
+ reg = <0x43>;
+ shunt-resistor = <5000>; /* r1221 */
+ };
+ vcco_mio: ina226@45 { /* u172 */
+ compatible = "ti,ina226";
+ reg = <0x45>;
+ shunt-resistor = <5000>; /* r1219 */
+ };
+ mgtavtt: ina226@46 { /* u188 */
+ compatible = "ti,ina226";
+ reg = <0x46>;
+ shunt-resistor = <2000>; /* r1384 */
+ };
+ vcco_502: ina226@47 { /* u174 */
+ compatible = "ti,ina226";
+ reg = <0x47>;
+ shunt-resistor = <5000>; /* r1825 */
+ };
+ mgtvccaux: ina226@48 { /* u176 */
+ compatible = "ti,ina226";
+ reg = <0x48>;
+ shunt-resistor = <5000>; /* r1232 */
+ };
+ vcc1v1_lp4: ina226@49 { /* u186 */
+ compatible = "ti,ina226";
+ reg = <0x49>;
+ shunt-resistor = <2000>; /* r1367 */
+ };
+ vadj_fmc: ina226@4a { /* u184 */
+ compatible = "ti,ina226";
+ reg = <0x4a>;
+ shunt-resistor = <2000>; /* r1350 */
+ };
+ lpdmgtyavcc: ina226@4b { /* u177 */
+ compatible = "ti,ina226";
+ reg = <0x4b>;
+ shunt-resistor = <5000>; /* r2097 */
+ };
+ lpdmgtyavtt: ina226@4c { /* u260 */
+ compatible = "ti,ina226";
+ reg = <0x4c>;
+ shunt-resistor = <2000>; /* r1834 */
+ };
+ lpdmgtyvccaux: ina226@4d { /* u234 */
+ compatible = "ti,ina226";
+ reg = <0x4d>;
+ shunt-resistor = <5000>; /* r1679 */
+ };
+ };
+ /* 4 - 7 unused */
+ };
+};
+
+&i2c1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c-mux@74 { /* u35 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ i2c-mux-idle-disconnect;
+ /* reset-gpios = <&PL_GPIO SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */
+ ref_clk_i2c: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ ref_clk: clock-generator@5d { /* u32 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>;
+ temperature-stability = <50>;
+ factory-fout = <33333333>;
+ clock-frequency = <33333333>;
+ clock-output-names = "ref_clk";
+ silabs,skip-recall;
+ };
+ };
+ fmcp1_i2c: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* connection to Samtec J51C */
+ /* expected eeprom 0x50 SE cards */
+ };
+ osfp_i2c: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ /* J362 connector */
+ };
+ lpddr4_si570_clk3_i2c: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ lpddr4_clk3: clock-generator@60 { /* u4 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x60>;
+ temperature-stability = <50>;
+ factory-fout = <200000000>;
+ clock-frequency = <200000000>;
+ clock-output-names = "lpddr4_clk3";
+ silabs,skip-recall;
+ };
+ /* alternative option DNP - u305 at 0x50 */
+ };
+ lpddr4_si570_clk2_i2c: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ lpddr4_clk2: clock-generator@60 { /* u3 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x60>;
+ temperature-stability = <50>;
+ factory-fout = <200000000>;
+ clock-frequency = <200000000>;
+ clock-output-names = "lpddr4_clk2";
+ silabs,skip-recall;
+ };
+ /* alternative option DNP - u303 at 0x50 */
+ };
+ lpddr4_si570_clk1_i2c: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ lpddr4_clk1: clock-generator@60 { /* u248 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x60>;
+ temperature-stability = <50>;
+ factory-fout = <200000000>;
+ clock-frequency = <200000000>;
+ clock-output-names = "lpddr4_clk1";
+ silabs,skip-recall;
+ };
+ /* alternative option DNP - u301 at 0x50 */
+ };
+ qsfpdd_i2c: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ /* J1/J2/J355/J354/J359/J358 connectors */
+ };
+ idt8a34001_i2c: i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ /* Via J310 connector */
+ idt_8a34001: phc@5b { /* u219B */
+ compatible = "idt,8a34001";
+ reg = <0x5b>;
+ };
+ };
+ };
+ i2c-mux@75 { /* u322 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x75>;
+ i2c-mux-idle-disconnect;
+ /* reset-gpios = <&PL_GPIO SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */
+ sfpdd1_i2c: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* J350 sfp-dd at 0x50 */
+ };
+ sfpdd2_i2c: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* J352 sfp-dd at 0x50 */
+ };
+ sfpdd3_i2c: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ /* J385 sfp-dd at 0x50 */
+ };
+ sfpdd4_i2c: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ /* J387 sfp-dd at 0x50 */
+ };
+ rc21008a_gtclk1_i2c: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ vc7_1: clock-generator@9 {
+ compatible = "renesas,rc21008a";
+ clock-output-names = "rc21008a-0";
+ reg = <0x9>;
+ #clock-cells = <1>;
+ clocks = <&vc7_xin>;
+ clock-names = "xin";
+ };
+ /* u298 - rc21008a at 0x9 */
+ /* connector J370 */
+ };
+ rc21008a_gtclk2_i2c: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ vc7_2: clock-generator@9 {
+ compatible = "renesas,rc21008a";
+ clock-output-names = "rc21008a-1";
+ reg = <0x9>;
+ #clock-cells = <1>;
+ clocks = <&vc7_xin>;
+ clock-names = "xin";
+ };
+ /* u299 - rc21008a at 0x9 */
+ /* connector J371 */
+ };
+ };
+};
diff --git a/arch/arm/dts/zynqmp-sc-vpk180-revB.dtso b/arch/arm/dts/zynqmp-sc-vpk180-revB.dtso
new file mode 100644
index 000000000000..e70eb4dc9478
--- /dev/null
+++ b/arch/arm/dts/zynqmp-sc-vpk180-revB.dtso
@@ -0,0 +1,337 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP VPK180 revA
+ *
+ * (C) Copyright 2021 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+/dts-v1/;
+/plugin/;
+
+
+&{/} {
+ compatible = "xlnx,zynqmp-sc-vpk180-revB", "xlnx,zynqmp-vpk180-revB",
+ "xlnx,zynqmp-vpk180", "xlnx,zynqmp";
+
+ vc7_xin: vc7-xin {
+ compatible = "fixed-clock";
+ #clock-cells = <0x0>;
+ clock-frequency = <50000000>;
+ };
+};
+
+&i2c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tca6416_u233: gpio@20 { /* u233 */
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller; /* interrupt not connected */
+ #gpio-cells = <2>;
+ gpio-line-names = "QSFPDD1_MODSELL", "QSFPDD2_MODSELL", "QSFPDD3_MODSELL", "QSFPDD4_MODSELL", /* 0 - 3 */
+ "PMBUS2_INA226_ALERT", "QSFPDD5_MODSELL", "QSFPDD6_MODSELL", "", /* 4 - 7 */
+ "FMCP1_FMC_PRSNT_M2C_B", "", "FMCP1_FMCP_PRSNT_M2C_B", "UTIL_3V3_VRHOT_B", /* 10 - 13 */
+ "VCCINT_VRHOT_B", "8A34001_EXP_RST_B", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */
+ };
+
+ i2c-mux@74 { /* u33 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
+ pmbus_i2c: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* On connector J325 */
+ ir38060_41: regulator@41 { /* IR38060 - u259 */
+ compatible = "infineon,ir38060", "infineon,ir38064";
+ reg = <0x41>; /* i2c addr 0x11 */
+ };
+ ir35221_45: pmic@45 { /* IR35221 - u291 */
+ compatible = "infineon,ir35221";
+ reg = <0x45>; /* i2c addr - 0x15 */
+ };
+ ir35221_46: pmic@46 { /* IR35221 - u152 */
+ compatible = "infineon,ir35221";
+ reg = <0x46>; /* i2c addr - 0x16 */
+ };
+ irps5401_47: pmic5401@47 { /* IRPS5401 - u160 */
+ compatible = "infineon,irps5401";
+ reg = <0x47>; /* i2c addr 0x17 */
+ };
+ irps5401_48: pmic@48 { /* IRPS5401 - u295 */
+ compatible = "infineon,irps5401";
+ reg = <0x48>; /* i2c addr 0x18 */
+ };
+ ir38164_49: regulator@49 { /* IR38164 - u189 */
+ compatible = "infineon,ir38164";
+ reg = <0x49>; /* i2c addr 0x19 */
+ };
+ irps5401_4c: pmic@4c { /* IRPS5401 - u167 */
+ compatible = "infineon,irps5401";
+ reg = <0x4c>; /* i2c addr 0x1c */
+ };
+ irps5401_4d: pmic@4d { /* IRPS5401 - u175 */
+ compatible = "infineon,irps5401";
+ reg = <0x4d>; /* i2c addr 0x1d */
+ };
+ ir38164_4e: regulator@4e { /* IR38164 - u185 */
+ compatible = "infineon,ir38164";
+ reg = <0x4e>; /* i2c addr 0x1e */
+ };
+ ir38164_4f: regulator@4f { /* IR38164 - u187 */
+ compatible = "infineon,ir38164";
+ reg = <0x4f>; /* i2c addr 0x1f */
+ };
+ };
+ pmbus1_ina226_i2c: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* FIXME check alerts coming to SC */
+ vccint: ina226@40 { /* u65 */
+ compatible = "ti,ina226";
+ reg = <0x40>;
+ shunt-resistor = <5000>; /* r440 */
+ };
+ vcc_soc: ina226@41 { /* u161 */
+ compatible = "ti,ina226";
+ reg = <0x41>;
+ shunt-resistor = <5000>; /* r2174 */
+ };
+ vcc_pmc: ina226@42 { /* u163 */
+ compatible = "ti,ina226";
+ reg = <0x42>;
+ shunt-resistor = <5000>; /* r1214 */
+ };
+ vcc_ram: ina226@43 { /* u5 */
+ compatible = "ti,ina226";
+ reg = <0x43>;
+ shunt-resistor = <5000>; /* r2108 */
+ };
+ vcc_pslp: ina226@44 { /* u165 */
+ compatible = "ti,ina226";
+ reg = <0x44>;
+ shunt-resistor = <5000>; /* r1830 */
+ };
+ vcc_psfp: ina226@45 { /* u164 */
+ compatible = "ti,ina226";
+ reg = <0x45>;
+ shunt-resistor = <5000>; /* r2086 */
+ };
+ };
+ i2c@2 { /* NC */ /* FIXME maybe remove */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+ pmbus2_ina226_i2c: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ /* FIXME check alerts coming to SC */
+ vccaux: ina226@40 { /* u166 */
+ compatible = "ti,ina226";
+ reg = <0x40>;
+ shunt-resistor = <2000>; /* r2109 */
+ };
+ vccaux_pmc: ina226@41 { /* u168 */
+ compatible = "ti,ina226";
+ reg = <0x41>;
+ shunt-resistor = <5000>; /* r1246 */
+ };
+ mgtavcc: ina226@42 { /* u265 */
+ compatible = "ti,ina226";
+ reg = <0x42>;
+ shunt-resistor = <5000>; /* r1829 */
+ };
+ vcc1v5: ina226@43 { /* u264 */
+ compatible = "ti,ina226";
+ reg = <0x43>;
+ shunt-resistor = <5000>; /* r1221 */
+ };
+ vcco_mio: ina226@45 { /* u172 */
+ compatible = "ti,ina226";
+ reg = <0x45>;
+ shunt-resistor = <5000>; /* r1219 */
+ };
+ mgtavtt: ina226@46 { /* u188 */
+ compatible = "ti,ina226";
+ reg = <0x46>;
+ shunt-resistor = <2000>; /* r1384 */
+ };
+ vcco_502: ina226@47 { /* u174 */
+ compatible = "ti,ina226";
+ reg = <0x47>;
+ shunt-resistor = <5000>; /* r1825 */
+ };
+ mgtvccaux: ina226@48 { /* u176 */
+ compatible = "ti,ina226";
+ reg = <0x48>;
+ shunt-resistor = <5000>; /* r1232 */
+ };
+ vcc1v1_lp4: ina226@49 { /* u186 */
+ compatible = "ti,ina226";
+ reg = <0x49>;
+ shunt-resistor = <2000>; /* r1367 */
+ };
+ vadj_fmc: ina226@4a { /* u184 */
+ compatible = "ti,ina226";
+ reg = <0x4a>;
+ shunt-resistor = <2000>; /* r1350 */
+ };
+ lpdmgtyavcc: ina226@4b { /* u177 */
+ compatible = "ti,ina226";
+ reg = <0x4b>;
+ shunt-resistor = <5000>; /* r2097 */
+ };
+ lpdmgtyavtt: ina226@4c { /* u260 */
+ compatible = "ti,ina226";
+ reg = <0x4c>;
+ shunt-resistor = <2000>; /* r1834 */
+ };
+ lpdmgtyvccaux: ina226@4d { /* u234 */
+ compatible = "ti,ina226";
+ reg = <0x4d>;
+ shunt-resistor = <5000>; /* r1679 */
+ };
+ };
+ /* 4 - 7 unused */
+ };
+};
+
+&i2c1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c-mux@74 { /* u35 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ i2c-mux-idle-disconnect;
+ /* reset-gpios = <&PL_GPIO SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+ fmcp1_i2c: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* connection to Samtec J51C */
+ /* expected eeprom 0x50 SE cards */
+ };
+ osfp_i2c: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ /* J362 connector */
+ };
+ i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ /* alternative option DNP - u305 at 0x50 */
+ };
+ i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ /* alternative option DNP - u303 at 0x50 */
+ };
+ i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ /* alternative option DNP - u301 at 0x50 */
+ };
+ qsfpdd_i2c: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ /* J1/J2/J355/J354/J359/J358 connectors */
+ };
+ idt8a34001_i2c: i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ /* Via J310 connector */
+ idt_8a34001: phc@5b { /* u219B */
+ compatible = "idt,8a34001";
+ reg = <0x5b>;
+ };
+ };
+ };
+ i2c-mux@75 { /* u322 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x75>;
+ i2c-mux-idle-disconnect;
+ /* reset-gpios = <&PL_GPIO SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */
+ sfpdd1_i2c: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* J350 sfp-dd at 0x50 */
+ };
+ sfpdd2_i2c: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* J352 sfp-dd at 0x50 */
+ };
+ sfpdd3_i2c: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ /* J385 sfp-dd at 0x50 */
+ };
+ sfpdd4_i2c: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ /* J387 sfp-dd at 0x50 */
+ };
+ rc21008a_gtclk1_i2c: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ vc7_1: clock-generator@9 {
+ compatible = "renesas,rc21008a";
+ clock-output-names = "rc21008a-0";
+ reg = <0x9>;
+ #clock-cells = <1>;
+ clocks = <&vc7_xin>;
+ clock-names = "xin";
+ };
+ /* u298 - rc21008a at 0x9 */
+ /* connector J370 */
+ };
+ rc21008a_gtclk2_i2c: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ vc7_2: clock-generator@9 {
+ compatible = "renesas,rc21008a";
+ clock-output-names = "rc21008a-1";
+ reg = <0x9>;
+ #clock-cells = <1>;
+ clocks = <&vc7_xin>;
+ clock-names = "xin";
+ };
+ /* u299 - rc21008a at 0x9 */
+ /* connector J371 */
+ };
+ };
+};
--
2.36.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 09/11] arm64: zynqmp: Add support for VPXA2785
2023-09-27 9:53 [PATCH 00/11] xilinx: add missing boards/SC descriptions Michal Simek
` (7 preceding siblings ...)
2023-09-27 9:53 ` [PATCH 08/11] arm64: zynqmp: Describe i2c structures for SCs Michal Simek
@ 2023-09-27 9:53 ` Michal Simek
2023-09-27 9:53 ` [PATCH 10/11] arm64: zynqmp: Add support for zcu670-revA Michal Simek
` (2 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Michal Simek @ 2023-09-27 9:53 UTC (permalink / raw)
To: u-boot, git
VPXA2785(vp-x-a2785-00) is evaluation board which contains two PCIe-Edge
fingers, one for PCIe-B(gen5x8) and one for CPM(dual gen5x8, gen5x16).
Each of the ports can operate in endpoint or root port mode. This allows
the single card to be used for both root port, endpoint, and switch modes.
The board is designed in the similar manner as others Versal boards. It
means board also have ZynqMP Zu4 System Controller which is described in a
separate file.
Signed-off-by: Michal Simek <michal.simek@amd.com>
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts | 438 +++++++++++++++++++++
2 files changed, 439 insertions(+)
create mode 100644 arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index a15ecd4bc70b..42def7a1178b 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -431,6 +431,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
zynqmp-sck-kv-g-revB.dtbo \
zynqmp-topic-miamimp-xilinx-xdp-v1r1.dtb \
zynqmp-vpk120-revA.dtb \
+ zynqmp-vp-x-a2785-00-revA.dtb \
zynqmp-zcu100-revC.dtb \
zynqmp-zcu102-revA.dtb \
zynqmp-zcu102-revB.dtb \
diff --git a/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts b/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts
new file mode 100644
index 000000000000..2f88aa4a0d28
--- /dev/null
+++ b/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts
@@ -0,0 +1,438 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP vp-x-a2785-00 RevA System Controller
+ *
+ * (C) Copyright 2021 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
+#include <dt-bindings/phy/phy.h>
+
+/ {
+ model = "ZynqMP System Controller on vp-x-a2785-00 board RevA";
+ compatible = "xlnx,zynqmp-vp-x-a2785-00-revA",
+ "xlnx,zynqmp-vp-x-a2785-00", "xlnx,zynqmp";
+
+ aliases {
+ ethernet0 = &gem0;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ mmc0 = &sdhci0;
+ serial0 = &uart0;
+ serial1 = &dcc;
+ spi0 = &qspi;
+ usb0 = &usb0;
+ usb1 = &usb1;
+ nvmem0 = &eeprom;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0 0 0 0x80000000>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+ j383 {
+ label = "j383";
+ gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
+ linux,code = <BTN_MISC>;
+ wakeup-source;
+ autorepeat;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ heartbeat-led { /* ds52 */
+ label = "heartbeat";
+ gpios = <&gpio 9 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ si5332_0: si5332_0 { /* ps_ref_clk - u142 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <33333333>;
+ };
+
+ si5332_1: si5332_1 { /* clk0_sgmii - u142 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <33333333>; /* FIXME */
+ };
+
+ si5332_2: si5332_2 { /* clk1_usb - u142 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <27000000>;
+ };
+};
+
+&qspi { /* MIO 0-5 */
+ status = "okay";
+ flash@0 {
+ compatible = "m25p80", "jedec,spi-nor"; /* u285 - mt25qu512abb8e12 512Mib */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+ spi-tx-bus-width = <4>; /* maybe 4 here */
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <108000000>;
+ partition@0 { /* for testing purpose */
+ label = "qspi";
+ reg = <0 0x4000000>;
+ };
+ };
+};
+
+&sdhci1 { /* sd MIO 45-51 */
+ status = "okay";
+ no-1-8-v;
+ disable-wp;
+ xlnx,mio-bank = <1>;
+};
+
+&uart0 { /* uart0 MIO38-39 */
+ status = "okay";
+ bootph-all;
+};
+
+&gem0 {
+ status = "okay";
+ phy-handle = <&phy0>;
+ phy-mode = "sgmii"; /* DTG generates this properly 1512 */
+ is-internal-pcspma;
+ /* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */
+ /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */
+ phy0: ethernet-phy@0 { /* u131 - M88e1512 */
+ reg = <0>;
+ };
+};
+
+&gpio {
+ status = "okay";
+ gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */
+ "QSPI_CS_B", "", "", "SYSCTLR_GPIO", "SYSCTLR_LED", /* 5 - 9 */
+ "SYSCTLR_PB", "PMC_ZU4_TRIGGER", "", "", "", /* 10 - 14 */
+ "", "", "", "", "", /* 15 - 19 */
+ "", "", "", "", "", /* 20 - 24 */
+ "", "", "", "", "", /* 25 - 29 */
+ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */
+ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */
+ "", "", "ETH_RESET_B", "", "", /* 40 - 44 */
+ "SD1_CD", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */
+ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */
+ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */
+ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "", /* 60 - 64 */
+ "", "", "", "", "", /* 65 - 69 */
+ "", "", "", "", "", /* 70 - 74 */
+ "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
+ "", "", /* 78 - 79 */
+ "", "", "", "", "", /* 80 - 84 */
+ "", "", "", "", "", /* 85 - 89 */
+ "", "", "", "", "", /* 90 - 94 */
+ "", "", "", "", "", /* 95 - 99 */
+ "", "", "", "", "", /* 100 - 104 */
+ "", "", "", "", "", /* 105 - 109 */
+ "", "", "", "", "", /* 110 - 114 */
+ "", "", "", "", "", /* 115 - 119 */
+ "", "", "", "", "", /* 120 - 124 */
+ "", "", "", "", "", /* 125 - 129 */
+ "", "", "", "", "", /* 130 - 134 */
+ "", "", "", "", "", /* 135 - 139 */
+ "", "", "", "", "", /* 140 - 144 */
+ "", "", "", "", "", /* 145 - 149 */
+ "", "", "", "", "", /* 150 - 154 */
+ "", "", "", "", "", /* 155 - 159 */
+ "", "", "", "", "", /* 160 - 164 */
+ "", "", "", "", "", /* 165 - 169 */
+ "", "", "", ""; /* 170 - 173 */
+};
+
+&i2c0 { /* MIO 34-35 - can't stay here */
+ status = "okay";
+ clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c0_default>;
+ pinctrl-1 = <&pinctrl_i2c0_gpio>;
+ scl-gpios = <&gpio 34 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio 35 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+
+ tca6416_u233: gpio@20 { /* u233 */ /* FIXME - address maybe wrong */
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller; /* interrupt not connected */
+ #gpio-cells = <2>;
+ gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "", "", /* 0 - 3 */
+ "", "", "", "MAX6643_FULL_SPEED", /* 4 - 7 */
+ "", "", "", "VCCINT_FAULT_B", /* 10 - 13 */
+ "VCCINT_VRHOT_B", "", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */
+ };
+
+ i2c-mux@74 { /* u33 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
+ pmbus_i2c: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* On connector J325 */
+ reg_vccint: tps53681@60 { /* u266 - 0xc0 */
+ compatible = "ti,tps53681", "ti,tps53679";
+ reg = <0x60>;
+ };
+ reg_vcc1v1_lp4: tps544@d { /* u85 */
+ compatible = "ti,tps544b25";
+ reg = <0xd>;
+ };
+ reg_mgtyavcc: tps544@10 { /* u274 */
+ compatible = "ti,tps544b25";
+ reg = <0x10>;
+ };
+ reg_mgtyavtt: tps544@11 { /* u275 */
+ compatible = "ti,tps544b25";
+ reg = <0x11>;
+ };
+ reg_vccaux: tps544@12 { /* u276 */
+ compatible = "ti,tps544b25";
+ reg = <0x12>;
+ };
+ reg_vcc_cpm: tps544@14 { /* u272 */
+ compatible = "ti,tps544b25";
+ reg = <0x14>;
+ };
+ reg_util_3v3: tps544@1d { /* u278 */
+ compatible = "ti,tps544b25";
+ reg = <0x1d>;
+ };
+ };
+ pmbus1_ina226_i2c: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* FIXME check alerts coming to SC */
+ vcc_cpm: ina226@44 { /* u273 */
+ compatible = "ti,ina226";
+ reg = <0x44>;
+ shunt-resistor = <1000>;
+ };
+ };
+ i2c@2 { /* NC */ /* FIXME maybe remove */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+ pcie_smbus: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+ pcie2_smbus: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ };
+ i2c@5 { /* NC */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ };
+ user_si570: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ };
+ /* 7 unused */
+ };
+};
+
+&i2c1 { /* i2c1 MIO 36-37 */
+ status = "okay";
+ clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio 36 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio 37 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+
+ i2c-mux@74 { /* u35 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */
+ dc_i2c: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* Use for storing information about SC board */
+ eeprom: eeprom@54 { /* u34 - m24128 16kB */
+ compatible = "st,24c128", "atmel,24c128";
+ reg = <0x54>; /* & 0x5c */
+ };
+ si570_ref_clk: clock-generator@5d { /* u32 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>;
+ temperature-stability = <50>;
+ factory-fout = <33333333>;
+ clock-frequency = <33333333>;
+ clock-output-names = "ref_clk";
+ silabs,skip-recall;
+ };
+ };
+ i2c@1 { /* NC - FIXME */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ i2c@2 { /* NC - FIXME */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+ i2c@3 { /* NC - FIXME */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+ lpddr4_si570_clk2_i2c: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ lpddr4_clk2: clock-generator@60 { /* u3 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x60>;
+ temperature-stability = <50>;
+ factory-fout = <200000000>;
+ clock-frequency = <200000000>;
+ clock-output-names = "lpddr4_clk2";
+ };
+ };
+ lpddr4_si570_clk1_i2c: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ lpddr4_clk1: clock-generator@60 { /* u248 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x60>;
+ temperature-stability = <50>;
+ factory-fout = <200000000>;
+ clock-frequency = <200000000>;
+ clock-output-names = "lpddr4_clk1";
+ };
+ };
+ /* 6-7 unused */
+ };
+};
+
+&usb0 { /* MIO52 - MIO63 */
+ status = "okay";
+ phy-names = "usb3-phy";
+ phys = <&psgtr 1 PHY_TYPE_USB3 0 1>;
+};
+
+&psgtr {
+ status = "okay";
+ /* sgmii, usb3 */
+ clocks = <&si5332_1>, <&si5332_2>;
+ clock-names = "ref0", "ref1";
+};
+
+&dwc3_0 {
+ status = "okay";
+ dr_mode = "peripheral";
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ maximum-speed = "super-speed";
+};
+
+&xilinx_ams {
+ status = "okay";
+};
+
+&ams_ps {
+ status = "okay";
+};
+
+&ams_pl {
+ status = "okay";
+};
+
+&pinctrl0 {
+ status = "okay";
+ pinctrl_i2c0_default: i2c0-default {
+ mux {
+ groups = "i2c0_8_grp";
+ function = "i2c0";
+ };
+
+ conf {
+ groups = "i2c0_8_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c0_gpio: i2c0-gpio {
+ mux {
+ groups = "gpio0_34_grp", "gpio0_35_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_34_grp", "gpio0_35_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c1_default: i2c1-default {
+ mux {
+ groups = "i2c1_9_grp";
+ function = "i2c1";
+ };
+
+ conf {
+ groups = "i2c1_9_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpio {
+ mux {
+ groups = "gpio0_36_grp", "gpio0_37_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_36_grp", "gpio0_37_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+};
--
2.36.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 10/11] arm64: zynqmp: Add support for zcu670-revA
2023-09-27 9:53 [PATCH 00/11] xilinx: add missing boards/SC descriptions Michal Simek
` (8 preceding siblings ...)
2023-09-27 9:53 ` [PATCH 09/11] arm64: zynqmp: Add support for VPXA2785 Michal Simek
@ 2023-09-27 9:53 ` Michal Simek
2023-09-27 9:53 ` [PATCH 11/11] arm64: zynqmp: Add support for zcu670-revB Michal Simek
2023-10-09 10:12 ` [PATCH 00/11] xilinx: add missing boards/SC descriptions Michal Simek
11 siblings, 0 replies; 13+ messages in thread
From: Michal Simek @ 2023-09-27 9:53 UTC (permalink / raw)
To: u-boot, git
The board is sharing a lot of components with zcu208 but it contains
differet silicon and also several components are done differently.
The board has 4GB memory connected to PS and additional 4GB connected to
PL. Compare to zcu208 sata support has been dropped and only USB3.0 is
using GTR (lane2). Others GTRs are routed to connectors.
MIO configuration is also shared with zcu111.
The board is using si5381 chip compare to si5341 which is normally used.
And as of now there is no Linux driver for this chip. PS reference clock is
generated out of si570 chip which is also new approach compare to zcu208.
Signed-off-by: Michal Simek <michal.simek@amd.com>
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/zynqmp-zcu670-revA.dts | 669 ++++++++++++++++++++++++++++
2 files changed, 670 insertions(+)
create mode 100644 arch/arm/dts/zynqmp-zcu670-revA.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 42def7a1178b..4c31a923aebc 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -447,6 +447,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
zynqmp-zcu1285-revA.dtb \
zynqmp-zcu208-revA.dtb \
zynqmp-zcu216-revA.dtb \
+ zynqmp-zcu670-revA.dtb \
zynqmp-zc1232-revA.dtb \
zynqmp-zc1254-revA.dtb \
zynqmp-zc1751-xm015-dc1.dtb \
diff --git a/arch/arm/dts/zynqmp-zcu670-revA.dts b/arch/arm/dts/zynqmp-zcu670-revA.dts
new file mode 100644
index 000000000000..edbbf0b30e7b
--- /dev/null
+++ b/arch/arm/dts/zynqmp-zcu670-revA.dts
@@ -0,0 +1,669 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP ZCU670 (67DR)
+ *
+ * (C) Copyright 2017 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
+#include <dt-bindings/phy/phy.h>
+
+/ {
+ model = "ZynqMP ZCU670 RevA";
+ compatible = "xlnx,zynqmp-zcu670-revA", "xlnx,zynqmp-zcu670",
+ "xlnx,zynqmp";
+
+ aliases {
+ ethernet0 = &gem3;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ mmc0 = &sdhci1;
+ nvmem0 = &eeprom;
+ rtc0 = &rtc;
+ serial0 = &uart0;
+ serial1 = &dcc;
+ spi0 = &qspi;
+ usb0 = &usb0;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0 0 0 0x80000000>, <0x8 0x0 0x0 0x80000000>;
+ /* Another 4GB connected to PL */
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+ sw1 {
+ label = "sw1";
+ gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
+ linux,code = <BTN_MISC>;
+ wakeup-source;
+ autorepeat;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ heartbeat-led {
+ label = "heartbeat"; /* DS1 */
+ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ ina226-vccint {
+ compatible = "iio-hwmon";
+ io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;
+ };
+ ina226-vccint-io-bram-ps {
+ compatible = "iio-hwmon";
+ io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;
+ };
+ ina226-vcc1v8 {
+ compatible = "iio-hwmon";
+ io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>;
+ };
+ ina226-vcc1v2 {
+ compatible = "iio-hwmon";
+ io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>;
+ };
+ ina226-vadj-fmc {
+ compatible = "iio-hwmon";
+ io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;
+ };
+ ina226-mgtavcc {
+ compatible = "iio-hwmon";
+ io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>;
+ };
+ ina226-mgt1v2 {
+ compatible = "iio-hwmon";
+ io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>;
+ };
+ ina226-mgt1v8 {
+ compatible = "iio-hwmon";
+ io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>;
+ };
+ ina226-vccint-ams {
+ compatible = "iio-hwmon";
+ io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>;
+ };
+ ina226-dac-avtt {
+ compatible = "iio-hwmon";
+ io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>;
+ };
+ ina226-dac-avccaux {
+ compatible = "iio-hwmon";
+ io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>;
+ };
+ ina226-adc-avcc {
+ compatible = "iio-hwmon";
+ io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>;
+ };
+ ina226-adc-avccaux {
+ compatible = "iio-hwmon";
+ io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>;
+ };
+ ina226-dac-avcc {
+ compatible = "iio-hwmon";
+ io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>;
+ };
+
+ /* 48MHz reference crystal */
+ ref48: ref48M {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <48000000>;
+ };
+
+ si5381_6: si5381_6 { /* refclk_usb3 - u43 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ };
+};
+
+&dcc {
+ status = "okay";
+};
+
+&fpd_dma_chan1 {
+ status = "okay";
+};
+
+&fpd_dma_chan2 {
+ status = "okay";
+};
+
+&fpd_dma_chan3 {
+ status = "okay";
+};
+
+&fpd_dma_chan4 {
+ status = "okay";
+};
+
+&fpd_dma_chan5 {
+ status = "okay";
+};
+
+&fpd_dma_chan6 {
+ status = "okay";
+};
+
+&fpd_dma_chan7 {
+ status = "okay";
+};
+
+&fpd_dma_chan8 {
+ status = "okay";
+};
+
+&gem3 {
+ status = "okay";
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy0: ethernet-phy@c {
+ #phy-cells = <1>;
+ compatible = "ethernet-phy-id2000.a231";
+ reg = <0xc>;
+ ti,rx-internal-delay = <0x8>;
+ ti,tx-internal-delay = <0xa>;
+ ti,fifo-depth = <0x1>;
+ ti,dp83867-rxctrl-strap-quirk;
+ reset-gpios = <&tca6416_u15 6 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&gpio {
+ status = "okay";
+ gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */
+ "QSPI_LWR_CS_B", "", "QSPI_UPR_CS_B", "QSPI_UPR_DQ0", "QSPI_UPR_DQ1", /* 5 - 9 */
+ "QSPI_UPR_DQ2", "QSPI_UPR_DQ3", "QSPI_UPR_CLK", "PS_GPIO2", "I2C0_SCL", /* 10 - 14 */
+ "I2C0_SDA", "I2C1_SCL", "I2C1_SDA", "UART0_TXD", "UART0_RXD", /* 15 - 19 */
+ "", "", "BUTTON", "LED", "", /* 20 - 24 */
+ "", "PMU_INPUT", "SFP3_TX_DISABLE", "SFP2_TX_DISABLE", "SFP1_TX_DISABLE", /* 25 - 29 */
+ "SFP0_TX_DISABLE", "", "PMU_GPO0", "PMU_GPO1", "PMU_GPO2", /* 30 - 34 */
+ "PMU_GPO3", "PMU_GPO4", "PMU_GPO5", "PS_GPIO1", "SDIO_SEL", /* 35 - 39 */
+ "SDIO_DIR_CMD", "SDIO_DIR_DAT0", "SDIO_DIR_DAT1", "SD_PWR_RST", "", /* 40 - 44 */
+ "SDIO_DETECT", "SDIO_DAT0", "SDIO_DAT1", "SDIO_DAT2", "SDIO_DAT3", /* 45 - 49 */
+ "SDIO_CMD", "SDIO_CLK", "USB_CLK", "USB_DIR", "USB_DATA2", /* 50 - 54 */
+ "USB_NXT", "USB_DATA0", "USB_DATA1", "USB_STP", "USB_DATA3", /* 55 - 59 */
+ "USB_DATA4", "USB_DATA5", "USB_DATA6", "USB_DATA7", "ENET_TX_CLK", /* 60 - 64 */
+ "ENET_TX_D0", "ENET_TX_D1", "ENET_TX_D2", "ENET_TX_D3", "ENET_TX_CTRL", /* 65 - 69 */
+ "ENET_RX_CLK", "ENET_RX_D0", "ENET_RX_D1", "ENET_RX_D2", "ENET_RX_D3", /* 70 - 74 */
+ "ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */
+ "", "", /* 78 - 79 */
+ "", "", "", "", "", /* 80 - 84 */
+ "", "", "", "", "", /* 85 - 89 */
+ "", "", "", "", "", /* 90 - 94 */
+ "", "", "", "", "", /* 95 - 99 */
+ "", "", "", "", "", /* 100 - 104 */
+ "", "", "", "", "", /* 105 - 109 */
+ "", "", "", "", "", /* 110 - 114 */
+ "", "", "", "", "", /* 115 - 119 */
+ "", "", "", "", "", /* 120 - 124 */
+ "", "", "", "", "", /* 125 - 129 */
+ "", "", "", "", "", /* 130 - 134 */
+ "", "", "", "", "", /* 135 - 139 */
+ "", "", "", "", "", /* 140 - 144 */
+ "", "", "", "", "", /* 145 - 149 */
+ "", "", "", "", "", /* 150 - 154 */
+ "", "", "", "", "", /* 155 - 159 */
+ "", "", "", "", "", /* 160 - 164 */
+ "", "", "", "", "", /* 165 - 169 */
+ "", "", "", ""; /* 170 - 173 */
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c0_default>;
+ pinctrl-1 = <&pinctrl_i2c0_gpio>;
+ scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+
+ tca6416_u15: gpio@20 { /* u15 */
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller; /* interrupt not connected */
+ #gpio-cells = <2>;
+ gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "MIO26_PMU_INPUT_LS", "DAC_AVTT_VOUT_SEL", /* 0 - 3 */
+ "SI5381_INT_ALM", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "MAX6643_FULL_SPEED", /* 4 - 7 */
+ "FMCP_HSPC_PRSNT_M2C_B", "", "", "VCCINT_VRHOT_B", /* 10 - 13 */
+ "", "8A34001_EXP_RST_B", "IRPS5401_ALERT_B", "INA226_PMBUS_ALERT"; /* 14 - 17 */
+ };
+
+ i2c-mux@75 { /* u17 */
+ compatible = "nxp,pca9544";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x75>;
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* PS_PMBUS */
+ /* PMBUS_ALERT done via pca9544 */
+ vccint: ina226@40 { /* u65 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-vccint";
+ reg = <0x40>;
+ shunt-resistor = <5000>;
+ };
+ vccint_io_bram_ps: ina226@41 { /* u57 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-vccint-io-bram-ps";
+ reg = <0x41>;
+ shunt-resistor = <5000>;
+ };
+ vcc1v8: ina226@42 { /* u60 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-vcc1v8";
+ reg = <0x42>;
+ shunt-resistor = <2000>;
+ };
+ vcc1v2: ina226@43 { /* u58 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-vcc1v2";
+ reg = <0x43>;
+ shunt-resistor = <5000>;
+ };
+ vadj_fmc: ina226@45 { /* u62 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-vadj-fmc";
+ reg = <0x45>;
+ shunt-resistor = <5000>;
+ };
+ mgtavcc: ina226@46 { /* u67 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-mgtavcc";
+ reg = <0x46>;
+ shunt-resistor = <2000>;
+ };
+ mgt1v2: ina226@47 { /* u63 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-mgt1v2";
+ reg = <0x47>;
+ shunt-resistor = <5000>; /* Not in schematics */
+ };
+ mgt1v8: ina226@48 { /* u64 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-mgt1v8";
+ reg = <0x48>;
+ shunt-resistor = <5000>;
+ };
+ vccint_ams: ina226@49 { /* u61 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-vccint-ams";
+ reg = <0x49>;
+ shunt-resistor = <5000>;
+ };
+ dac_avtt: ina226@4a { /* u59 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-dac-avtt";
+ reg = <0x4a>;
+ shunt-resistor = <5000>;
+ };
+ dac_avccaux: ina226@4b { /* u124 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-dac-avccaux";
+ reg = <0x4b>;
+ shunt-resistor = <5000>;
+ };
+ adc_avcc: ina226@4c { /* u75 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-adc-avcc";
+ reg = <0x4c>;
+ shunt-resistor = <5000>;
+ };
+ adc_avccaux: ina226@4d { /* u71 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-adc-avccaux";
+ reg = <0x4d>;
+ shunt-resistor = <5000>;
+ };
+ dac_avcc: ina226@4e { /* u77 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-dac-avcc";
+ reg = <0x4e>;
+ shunt-resistor = <5000>;
+ };
+ };
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* NC */
+ };
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ /* u104 - ir35215 0x10/0x40 */
+ /* u127 - ir38164 0x1b/0x4b */
+ /* u112 - ir38164 0x13/0x43 */
+ /* u123 - ir38164 0x1c/0x4c */
+
+ irps5401_44: irps5401@44 { /* IRPS5401 - u53 */
+ compatible = "infineon,irps5401";
+ reg = <0x44>; /* i2c addr 0x14 */
+ };
+ irps5401_45: irps5401@45 { /* IRPS5401 - u55 */
+ compatible = "infineon,irps5401";
+ reg = <0x45>; /* i2c addr 0x15 */
+ };
+ /* J21 header too */
+
+ };
+ i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ /* SYSMON */
+ };
+ };
+ /* u38 MPS430 */
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+
+ i2c-mux@74 {
+ compatible = "nxp,pca9548"; /* u20 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
+ i2c_eeprom: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /*
+ * IIC_EEPROM 1kB memory which uses 256B blocks
+ * where every block has different address.
+ * 0 - 256B address 0x54
+ * 256B - 512B address 0x55
+ * 512B - 768B address 0x56
+ * 768B - 1024B address 0x57
+ */
+ eeprom: eeprom@54 { /* u21 */
+ compatible = "atmel,24c128";
+ reg = <0x54>;
+ };
+ };
+ i2c_si5381: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* SI5381 - u43 */
+ /* si5381: clock-generator@68 {
+ reg = <0x68>;
+ };*/
+ };
+ i2c_si570_user_c0: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ si570_1: clock-generator@5d { /* USER C0 SI570 - u47 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>;
+ temperature-stability = <50>;
+ factory-fout = <300000000>;
+ clock-frequency = <300000000>;
+ clock-output-names = "si570_user_c0";
+ };
+ };
+ i2c_si570_mgt: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ si570_2: clock-generator@5d { /* USER MGT SI570 - u48 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>;
+ temperature-stability = <50>;
+ factory-fout = <156250000>;
+ clock-frequency = <156250000>;
+ clock-output-names = "si570_mgt";
+ };
+ };
+ i2c_8a34001: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ /* U409B - 8a34001 */
+ };
+ i2c_clk104: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ /* CLK104_SDA */
+ };
+ i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ /* RFMCP connector */
+ };
+ /* 7 NC */
+ };
+
+ i2c-mux@75 {
+ compatible = "nxp,pca9548"; /* u22 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x75>;
+ /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* FMCP_HSPC_IIC */
+ };
+ i2c_si570_psrefclk: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ si570_3: clock-generator@5d { /* USER SI570 PSREFCLK - u130 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>;
+ temperature-stability = <50>;
+ factory-fout = <33333333>;
+ clock-frequency = <33333333>;
+ clock-output-names = "si570_ps_ref_clk";
+ silabs,skip-recall;
+ };
+ };
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ /* SYSMON */
+ };
+ i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ /* DDR4 SODIMM */
+ };
+ i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ /* SFP3 */
+ };
+ i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ /* SFP2 */
+ };
+ i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ /* SFP1 */
+ };
+ i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ /* SFP0 */
+ };
+ };
+ /* u38 MPS430 */
+};
+
+&pinctrl0 {
+ status = "okay";
+ pinctrl_i2c0_default: i2c0-default {
+ mux {
+ groups = "i2c0_3_grp";
+ function = "i2c0";
+ };
+
+ conf {
+ groups = "i2c0_3_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c0_gpio: i2c0-gpio {
+ mux {
+ groups = "gpio0_14_grp", "gpio0_15_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_14_grp", "gpio0_15_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c1_default: i2c1-default {
+ mux {
+ groups = "i2c1_4_grp";
+ function = "i2c1";
+ };
+
+ conf {
+ groups = "i2c1_4_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpio {
+ mux {
+ groups = "gpio0_16_grp", "gpio0_17_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_16_grp", "gpio0_17_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+};
+
+&qspi {
+ status = "okay";
+ num-cs = <2>;
+ flash@0 {
+ compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 2Gb */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>, <1>;
+ parallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
+ spi-max-frequency = <108000000>; /* Based on DC1 spec */
+ };
+};
+
+&rtc {
+ status = "okay";
+};
+
+/* SD1 with level shifter */
+&sdhci1 {
+ status = "okay";
+ disable-wp;
+ /*
+ * This property should be removed for supporting UHS mode
+ */
+ no-1-8-v;
+ xlnx,mio-bank = <1>;
+};
+
+&psgtr {
+ status = "okay";
+ /* hspc_dp4, hspc_dp5, usb3, hspc_dp6 */
+ clocks = <&si5381_6>;
+ clock-names = "ref2";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+/* ULPI SMSC USB3320 */
+&usb0 {
+ status = "okay";
+ phy-names = "usb3-phy";
+ phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
+};
+
+&dwc3_0 {
+ status = "okay";
+ dr_mode = "host";
+ snps,usb3_lpm_capable;
+};
--
2.36.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 11/11] arm64: zynqmp: Add support for zcu670-revB
2023-09-27 9:53 [PATCH 00/11] xilinx: add missing boards/SC descriptions Michal Simek
` (9 preceding siblings ...)
2023-09-27 9:53 ` [PATCH 10/11] arm64: zynqmp: Add support for zcu670-revA Michal Simek
@ 2023-09-27 9:53 ` Michal Simek
2023-10-09 10:12 ` [PATCH 00/11] xilinx: add missing boards/SC descriptions Michal Simek
11 siblings, 0 replies; 13+ messages in thread
From: Michal Simek @ 2023-09-27 9:53 UTC (permalink / raw)
To: u-boot, git
RevB has different SD level shifter compare to revA. There are couple of
changes between revisions but none of them requires SW alignment.
Signed-off-by: Michal Simek <michal.simek@amd.com>
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/zynqmp-zcu670-revB.dts | 672 ++++++++++++++++++++++++++++
2 files changed, 673 insertions(+)
create mode 100644 arch/arm/dts/zynqmp-zcu670-revB.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 4c31a923aebc..fa65821ff475 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -448,6 +448,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
zynqmp-zcu208-revA.dtb \
zynqmp-zcu216-revA.dtb \
zynqmp-zcu670-revA.dtb \
+ zynqmp-zcu670-revB.dtb \
zynqmp-zc1232-revA.dtb \
zynqmp-zc1254-revA.dtb \
zynqmp-zc1751-xm015-dc1.dtb \
diff --git a/arch/arm/dts/zynqmp-zcu670-revB.dts b/arch/arm/dts/zynqmp-zcu670-revB.dts
new file mode 100644
index 000000000000..97599c5658fb
--- /dev/null
+++ b/arch/arm/dts/zynqmp-zcu670-revB.dts
@@ -0,0 +1,672 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP ZCU670 (67DR) revB
+ *
+ * (C) Copyright 2017 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
+#include <dt-bindings/phy/phy.h>
+
+/ {
+ model = "ZynqMP ZCU670 RevB";
+ compatible = "xlnx,zynqmp-zcu670-revB", "xlnx,zynqmp-zcu670",
+ "xlnx,zynqmp";
+
+ aliases {
+ ethernet0 = &gem3;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ mmc0 = &sdhci1;
+ nvmem0 = &eeprom;
+ rtc0 = &rtc;
+ serial0 = &uart0;
+ serial1 = &dcc;
+ spi0 = &qspi;
+ usb0 = &usb0;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0 0 0 0x80000000>, <0x8 0x0 0x0 0x80000000>;
+ /* Another 4GB connected to PL */
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+ sw1 {
+ label = "sw1";
+ gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
+ linux,code = <BTN_MISC>;
+ wakeup-source;
+ autorepeat;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ heartbeat-led {
+ label = "heartbeat"; /* DS1 */
+ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ ina226-vccint {
+ compatible = "iio-hwmon";
+ io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;
+ };
+ ina226-vccint-io-bram-ps {
+ compatible = "iio-hwmon";
+ io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;
+ };
+ ina226-vcc1v8 {
+ compatible = "iio-hwmon";
+ io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>;
+ };
+ ina226-vcc1v2 {
+ compatible = "iio-hwmon";
+ io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>;
+ };
+ ina226-vadj-fmc {
+ compatible = "iio-hwmon";
+ io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;
+ };
+ ina226-mgtavcc {
+ compatible = "iio-hwmon";
+ io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>;
+ };
+ ina226-mgt1v2 {
+ compatible = "iio-hwmon";
+ io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>;
+ };
+ ina226-mgt1v8 {
+ compatible = "iio-hwmon";
+ io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>;
+ };
+ ina226-vccint-ams {
+ compatible = "iio-hwmon";
+ io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>;
+ };
+ ina226-dac-avtt {
+ compatible = "iio-hwmon";
+ io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>;
+ };
+ ina226-dac-avccaux {
+ compatible = "iio-hwmon";
+ io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>;
+ };
+ ina226-adc-avcc {
+ compatible = "iio-hwmon";
+ io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>;
+ };
+ ina226-adc-avccaux {
+ compatible = "iio-hwmon";
+ io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>;
+ };
+ ina226-dac-avcc {
+ compatible = "iio-hwmon";
+ io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>;
+ };
+
+ /* 48MHz reference crystal */
+ ref48: ref48M {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <48000000>;
+ };
+
+ si5381_6: si5381_6 { /* refclk_usb3 - u43 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ };
+};
+
+&dcc {
+ status = "okay";
+};
+
+&fpd_dma_chan1 {
+ status = "okay";
+};
+
+&fpd_dma_chan2 {
+ status = "okay";
+};
+
+&fpd_dma_chan3 {
+ status = "okay";
+};
+
+&fpd_dma_chan4 {
+ status = "okay";
+};
+
+&fpd_dma_chan5 {
+ status = "okay";
+};
+
+&fpd_dma_chan6 {
+ status = "okay";
+};
+
+&fpd_dma_chan7 {
+ status = "okay";
+};
+
+&fpd_dma_chan8 {
+ status = "okay";
+};
+
+&gem3 {
+ status = "okay";
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy0: ethernet-phy@c {
+ #phy-cells = <1>;
+ compatible = "ethernet-phy-id2000.a231";
+ reg = <0xc>;
+ ti,rx-internal-delay = <0x8>;
+ ti,tx-internal-delay = <0xa>;
+ ti,fifo-depth = <0x1>;
+ ti,dp83867-rxctrl-strap-quirk;
+ reset-gpios = <&tca6416_u15 6 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&gpio {
+ status = "okay";
+ gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */
+ "QSPI_LWR_CS_B", "", "QSPI_UPR_CS_B", "QSPI_UPR_DQ0", "QSPI_UPR_DQ1", /* 5 - 9 */
+ "QSPI_UPR_DQ2", "QSPI_UPR_DQ3", "QSPI_UPR_CLK", "PS_GPIO2", "I2C0_SCL", /* 10 - 14 */
+ "I2C0_SDA", "I2C1_SCL", "I2C1_SDA", "UART0_TXD", "UART0_RXD", /* 15 - 19 */
+ "", "", "BUTTON", "LED", "", /* 20 - 24 */
+ "", "PMU_INPUT", "SFP3_TX_DISABLE", "SFP2_TX_DISABLE", "SFP1_TX_DISABLE", /* 25 - 29 */
+ "SFP0_TX_DISABLE", "", "PMU_GPO0", "PMU_GPO1", "PMU_GPO2", /* 30 - 34 */
+ "PMU_GPO3", "PMU_GPO4", "PMU_GPO5", "PS_GPIO1", "SDIO_SEL", /* 35 - 39 */
+ "SDIO_DIR_CMD", "SDIO_DIR_DAT0", "SDIO_DIR_DAT1", "SD_PWR_RST", "", /* 40 - 44 */
+ "SDIO_DETECT", "SDIO_DAT0", "SDIO_DAT1", "SDIO_DAT2", "SDIO_DAT3", /* 45 - 49 */
+ "SDIO_CMD", "SDIO_CLK", "USB_CLK", "USB_DIR", "USB_DATA2", /* 50 - 54 */
+ "USB_NXT", "USB_DATA0", "USB_DATA1", "USB_STP", "USB_DATA3", /* 55 - 59 */
+ "USB_DATA4", "USB_DATA5", "USB_DATA6", "USB_DATA7", "ENET_TX_CLK", /* 60 - 64 */
+ "ENET_TX_D0", "ENET_TX_D1", "ENET_TX_D2", "ENET_TX_D3", "ENET_TX_CTRL", /* 65 - 69 */
+ "ENET_RX_CLK", "ENET_RX_D0", "ENET_RX_D1", "ENET_RX_D2", "ENET_RX_D3", /* 70 - 74 */
+ "ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */
+ "", "", /* 78 - 79 */
+ "", "", "", "", "", /* 80 - 84 */
+ "", "", "", "", "", /* 85 - 89 */
+ "", "", "", "", "", /* 90 - 94 */
+ "", "", "", "", "", /* 95 - 99 */
+ "", "", "", "", "", /* 100 - 104 */
+ "", "", "", "", "", /* 105 - 109 */
+ "", "", "", "", "", /* 110 - 114 */
+ "", "", "", "", "", /* 115 - 119 */
+ "", "", "", "", "", /* 120 - 124 */
+ "", "", "", "", "", /* 125 - 129 */
+ "", "", "", "", "", /* 130 - 134 */
+ "", "", "", "", "", /* 135 - 139 */
+ "", "", "", "", "", /* 140 - 144 */
+ "", "", "", "", "", /* 145 - 149 */
+ "", "", "", "", "", /* 150 - 154 */
+ "", "", "", "", "", /* 155 - 159 */
+ "", "", "", "", "", /* 160 - 164 */
+ "", "", "", "", "", /* 165 - 169 */
+ "", "", "", ""; /* 170 - 173 */
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c0_default>;
+ pinctrl-1 = <&pinctrl_i2c0_gpio>;
+ scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+
+ tca6416_u15: gpio@20 { /* u15 */
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller; /* interrupt not connected */
+ #gpio-cells = <2>;
+ gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "MIO26_PMU_INPUT_LS", "DAC_AVTT_VOUT_SEL", /* 0 - 3 */
+ "SI5381_INT_ALM", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "MAX6643_FULL_SPEED", /* 4 - 7 */
+ "FMCP_HSPC_PRSNT_M2C_B", "", "", "VCCINT_VRHOT_B", /* 10 - 13 */
+ "", "8A34001_EXP_RST_B", "IRPS5401_ALERT_B", "INA226_PMBUS_ALERT"; /* 14 - 17 */
+ };
+
+ i2c-mux@75 { /* u17 */
+ compatible = "nxp,pca9544";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x75>;
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* PS_PMBUS */
+ /* PMBUS_ALERT done via pca9544 */
+ vccint: ina226@40 { /* u65 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-vccint";
+ reg = <0x40>;
+ shunt-resistor = <5000>;
+ };
+ vccint_io_bram_ps: ina226@41 { /* u57 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-vccint-io-bram-ps";
+ reg = <0x41>;
+ shunt-resistor = <5000>;
+ };
+ vcc1v8: ina226@42 { /* u60 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-vcc1v8";
+ reg = <0x42>;
+ shunt-resistor = <2000>;
+ };
+ vcc1v2: ina226@43 { /* u58 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-vcc1v2";
+ reg = <0x43>;
+ shunt-resistor = <5000>;
+ };
+ vadj_fmc: ina226@45 { /* u62 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-vadj-fmc";
+ reg = <0x45>;
+ shunt-resistor = <5000>;
+ };
+ mgtavcc: ina226@46 { /* u67 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-mgtavcc";
+ reg = <0x46>;
+ shunt-resistor = <2000>;
+ };
+ mgt1v2: ina226@47 { /* u63 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-mgt1v2";
+ reg = <0x47>;
+ shunt-resistor = <5000>; /* Not in schematics */
+ };
+ mgt1v8: ina226@48 { /* u64 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-mgt1v8";
+ reg = <0x48>;
+ shunt-resistor = <5000>;
+ };
+ vccint_ams: ina226@49 { /* u61 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-vccint-ams";
+ reg = <0x49>;
+ shunt-resistor = <5000>;
+ };
+ dac_avtt: ina226@4a { /* u59 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-dac-avtt";
+ reg = <0x4a>;
+ shunt-resistor = <5000>;
+ };
+ dac_avccaux: ina226@4b { /* u124 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-dac-avccaux";
+ reg = <0x4b>;
+ shunt-resistor = <5000>;
+ };
+ adc_avcc: ina226@4c { /* u75 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-adc-avcc";
+ reg = <0x4c>;
+ shunt-resistor = <5000>;
+ };
+ adc_avccaux: ina226@4d { /* u71 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-adc-avccaux";
+ reg = <0x4d>;
+ shunt-resistor = <5000>;
+ };
+ dac_avcc: ina226@4e { /* u77 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-dac-avcc";
+ reg = <0x4e>;
+ shunt-resistor = <5000>;
+ };
+ };
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* NC */
+ };
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ /* u104 - ir35215 0x10/0x40 */
+ /* u127 - ir38164 0x1b/0x4b */
+ /* u112 - ir38164 0x13/0x43 */
+ /* u123 - ir38164 0x1c/0x4c */
+
+ irps5401_44: irps5401@44 { /* IRPS5401 - u53 */
+ compatible = "infineon,irps5401";
+ reg = <0x44>; /* i2c addr 0x14 */
+ };
+ irps5401_45: irps5401@45 { /* IRPS5401 - u55 */
+ compatible = "infineon,irps5401";
+ reg = <0x45>; /* i2c addr 0x15 */
+ };
+ /* J21 header too */
+
+ };
+ i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ /* SYSMON */
+ };
+ };
+ /* u38 MPS430 */
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+
+ i2c-mux@74 {
+ compatible = "nxp,pca9548"; /* u20 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
+ i2c_eeprom: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /*
+ * IIC_EEPROM 1kB memory which uses 256B blocks
+ * where every block has different address.
+ * 0 - 256B address 0x54
+ * 256B - 512B address 0x55
+ * 512B - 768B address 0x56
+ * 768B - 1024B address 0x57
+ */
+ eeprom: eeprom@54 { /* u21 */
+ compatible = "atmel,24c128";
+ reg = <0x54>;
+ };
+ };
+ i2c_si5381: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* SI5381 - u43 */
+ /* si5381: clock-generator@68 {
+ reg = <0x68>;
+ };*/
+ };
+ i2c_si570_user_c0: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ si570_1: clock-generator@5d { /* USER C0 SI570 - u47 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>;
+ temperature-stability = <50>;
+ factory-fout = <300000000>;
+ clock-frequency = <300000000>;
+ clock-output-names = "si570_user_c0";
+ };
+ };
+ i2c_si570_mgt: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ si570_2: clock-generator@5d { /* USER MGT SI570 - u48 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>;
+ temperature-stability = <50>;
+ factory-fout = <156250000>;
+ clock-frequency = <156250000>;
+ clock-output-names = "si570_mgt";
+ };
+ };
+ i2c_8a34001: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ /* U409B - 8a34001 */
+ };
+ i2c_clk104: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ /* CLK104_SDA */
+ };
+ i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ /* RFMCP connector */
+ };
+ /* 7 NC */
+ };
+
+ i2c-mux@75 {
+ compatible = "nxp,pca9548"; /* u22 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x75>;
+ /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* FMCP_HSPC_IIC */
+ };
+ i2c_si570_psrefclk: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ si570_3: clock-generator@5d { /* USER SI570 PSREFCLK - u130 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>;
+ temperature-stability = <50>;
+ factory-fout = <33333333>;
+ clock-frequency = <33333333>;
+ clock-output-names = "si570_ps_ref_clk";
+ silabs,skip-recall;
+ };
+ };
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ /* SYSMON */
+ };
+ i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ /* DDR4 SODIMM */
+ };
+ i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ /* SFP3 */
+ };
+ i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ /* SFP2 */
+ };
+ i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ /* SFP1 */
+ };
+ i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ /* SFP0 */
+ };
+ };
+ /* u38 MPS430 */
+};
+
+&pinctrl0 {
+ status = "okay";
+ pinctrl_i2c0_default: i2c0-default {
+ mux {
+ groups = "i2c0_3_grp";
+ function = "i2c0";
+ };
+
+ conf {
+ groups = "i2c0_3_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c0_gpio: i2c0-gpio {
+ mux {
+ groups = "gpio0_14_grp", "gpio0_15_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_14_grp", "gpio0_15_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c1_default: i2c1-default {
+ mux {
+ groups = "i2c1_4_grp";
+ function = "i2c1";
+ };
+
+ conf {
+ groups = "i2c1_4_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpio {
+ mux {
+ groups = "gpio0_16_grp", "gpio0_17_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_16_grp", "gpio0_17_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+};
+
+&qspi {
+ status = "okay";
+ num-cs = <2>;
+ flash@0 {
+ compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 2Gb */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>, <1>;
+ parallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
+ spi-max-frequency = <108000000>; /* Based on DC1 spec */
+ };
+};
+
+&rtc {
+ status = "okay";
+};
+
+/* SD1 with level shifter */
+&sdhci1 {
+ status = "okay";
+ disable-wp;
+ /*
+ * This property should be removed for supporting UHS mode
+ */
+ no-1-8-v;
+ xlnx,mio-bank = <1>;
+ clk-phase-sd-hs = <120>, <60>;
+ clk-phase-uhs-sdr25 = <132>, <60>;
+ clk-phase-uhs-ddr50 = <153>, <48>;
+};
+
+&psgtr {
+ status = "okay";
+ /* hspc_dp4, hspc_dp5, usb3, hspc_dp6 */
+ clocks = <&si5381_6>;
+ clock-names = "ref2";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+/* ULPI SMSC USB3320 */
+&usb0 {
+ status = "okay";
+ phy-names = "usb3-phy";
+ phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
+};
+
+&dwc3_0 {
+ status = "okay";
+ dr_mode = "host";
+ snps,usb3_lpm_capable;
+};
--
2.36.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH 00/11] xilinx: add missing boards/SC descriptions
2023-09-27 9:53 [PATCH 00/11] xilinx: add missing boards/SC descriptions Michal Simek
` (10 preceding siblings ...)
2023-09-27 9:53 ` [PATCH 11/11] arm64: zynqmp: Add support for zcu670-revB Michal Simek
@ 2023-10-09 10:12 ` Michal Simek
11 siblings, 0 replies; 13+ messages in thread
From: Michal Simek @ 2023-10-09 10:12 UTC (permalink / raw)
To: u-boot, git
On 9/27/23 11:53, Michal Simek wrote:
> Hi,
>
> I am sending series of zynqmp boards mostly related to system controller.
> System controller is small ZynqMP board sitting on Versal/Versal NET board
> doing board management. There is a internal spec about connection outside
> but pretty much DT description describe all connected IPs.
> The only thing what it is not covered in generic SC are i2c buses because
> they contain different devices. That's why they are described by DT
> overlays.
> The first version was created for vpk120-revA, next was generic SC revB and
> because of supply chain issue ethernet phy was replaced which ends up in
> revC version.
>
> The series also contain some cleanups and also adding new platforms like
> KD240.
>
> Thanks,
> Michal
>
>
> Michal Simek (11):
> arm64: zynqmp: Add support for KD240 Kria SOM CC
> arm64: zynqmp: Remove xlnx,fclk nodes
> arm64: zynqmp: Add support for vck190 revB system controller
> arm64: zynqmp: Add x-prc-01/02/03/04/05 revA support from SC
> arm64: zynqmp: Add support for vpk120-revA
> arm64: zynqmp: Create description for generic SC (vpk120-revB)
> arm64: zynqmp: Add support for SC revC
> arm64: zynqmp: Describe i2c structures for SCs
> arm64: zynqmp: Add support for VPXA2785
> arm64: zynqmp: Add support for zcu670-revA
> arm64: zynqmp: Add support for zcu670-revB
>
> arch/arm/dts/Makefile | 20 +
> arch/arm/dts/zynqmp-clk-ccf.dtsi | 18 -
> arch/arm/dts/zynqmp-e-a2197-00-revB.dts | 34 +
> .../zynqmp-p-a2197-00-revA-x-prc-01-revA.dtso | 76 ++
> .../zynqmp-p-a2197-00-revA-x-prc-02-revA.dtso | 76 ++
> .../zynqmp-p-a2197-00-revA-x-prc-03-revA.dtso | 80 +++
> .../zynqmp-p-a2197-00-revA-x-prc-04-revA.dtso | 86 +++
> .../zynqmp-p-a2197-00-revA-x-prc-05-revA.dtso | 86 +++
> arch/arm/dts/zynqmp-sc-revB.dts | 430 +++++++++++
> arch/arm/dts/zynqmp-sc-revC.dts | 37 +
> arch/arm/dts/zynqmp-sc-vek280-revA.dtso | 230 ++++++
> arch/arm/dts/zynqmp-sc-vek280-revB.dtso | 15 +
> arch/arm/dts/zynqmp-sc-vhk158-revA.dtso | 321 +++++++++
> .../arm/dts/zynqmp-sc-vn-p-b2197-00-revA.dtso | 460 ++++++++++++
> arch/arm/dts/zynqmp-sc-vpk120-revB.dtso | 326 +++++++++
> arch/arm/dts/zynqmp-sc-vpk180-revA.dtso | 371 ++++++++++
> arch/arm/dts/zynqmp-sc-vpk180-revB.dtso | 337 +++++++++
> arch/arm/dts/zynqmp-sck-kd-g-revA.dtso | 353 +++++++++
> arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts | 438 ++++++++++++
> arch/arm/dts/zynqmp-vpk120-revA.dts | 574 +++++++++++++++
> arch/arm/dts/zynqmp-zcu670-revA.dts | 669 +++++++++++++++++
> arch/arm/dts/zynqmp-zcu670-revB.dts | 672 ++++++++++++++++++
> configs/xilinx_zynqmp_virt_defconfig | 2 +-
> 23 files changed, 5692 insertions(+), 19 deletions(-)
> create mode 100644 arch/arm/dts/zynqmp-e-a2197-00-revB.dts
> create mode 100644 arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-01-revA.dtso
> create mode 100644 arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-02-revA.dtso
> create mode 100644 arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-03-revA.dtso
> create mode 100644 arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-04-revA.dtso
> create mode 100644 arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-05-revA.dtso
> create mode 100644 arch/arm/dts/zynqmp-sc-revB.dts
> create mode 100644 arch/arm/dts/zynqmp-sc-revC.dts
> create mode 100644 arch/arm/dts/zynqmp-sc-vek280-revA.dtso
> create mode 100644 arch/arm/dts/zynqmp-sc-vek280-revB.dtso
> create mode 100644 arch/arm/dts/zynqmp-sc-vhk158-revA.dtso
> create mode 100644 arch/arm/dts/zynqmp-sc-vn-p-b2197-00-revA.dtso
> create mode 100644 arch/arm/dts/zynqmp-sc-vpk120-revB.dtso
> create mode 100644 arch/arm/dts/zynqmp-sc-vpk180-revA.dtso
> create mode 100644 arch/arm/dts/zynqmp-sc-vpk180-revB.dtso
> create mode 100644 arch/arm/dts/zynqmp-sck-kd-g-revA.dtso
> create mode 100644 arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts
> create mode 100644 arch/arm/dts/zynqmp-vpk120-revA.dts
> create mode 100644 arch/arm/dts/zynqmp-zcu670-revA.dts
> create mode 100644 arch/arm/dts/zynqmp-zcu670-revB.dts
>
Applied.
M
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