public inbox for u-boot@lists.denx.de
 help / color / mirror / Atom feed
From: Tejas Bhumkar <tejas.arvind.bhumkar@amd.com>
To: <u-boot@lists.denx.de>
Cc: <jagan@amarulasolutions.com>, <n-francis@ti.com>,
	<michal.simek@amd.com>,  <venkatesh.abbarapu@amd.com>,
	<git@amd.com>
Subject: [PATCH 00/19] Add support for DDR PHY mode
Date: Mon, 11 Mar 2024 22:52:30 +0530	[thread overview]
Message-ID: <cover.1710098033.git.tejas.arvind.bhumkar@amd.com> (raw)

Enable DDR PHY mode support for Micron,ISSI,GIGA and
Macronix Flash.

We are dividing the below series into three sets. This 
represents the initial set, wherein we have activated 
DDR mode support for flashes.
https://lore.kernel.org/all/cover.1701853668.git.tejas.arvind.bhumkar@amd.com/

The series is based on:
https://lore.kernel.org/all/20240304031046.25998-1-venkatesh.abbarapu@amd.com/

---

Ashok Reddy Soma (7):
  spi: cadence_qspi: Write aligned byte length to ahbbase
  spi: cadence_qspi: Clean up registers in init
  spi: cadence_qspi: Initialize read and write watermark registers
  mtd: spi-nor: Enable mt35xu512aba_fixups for all mt35xx flashes
  mtd: spi-nor: Check SNOR_F_IO_MODE_EN_VOLATILE only if SFDP is enabled
  mtd: spi-nor: Add support for cross die read in dual flash
    configuration
  mtd: spi-nor: Enable DTR octal flash program

T Karthik Reddy (5):
  spi: cadence_qspi: Add support for DDR PHY mode
  spi: cadence-qspi: reset the ospi controller
  spi: cadence_ospi_versal: ospi ddr changes in cadence ospi versal
    driver
  spi: cadence_qspi: Add spi mem dtr support ops
  spi: mtd: Use split reads if multi-die flag is set

Tejas Bhumkar (6):
  arm64: versal: Enable defconfig for Micron octal flashes
  mtd: spi-nor: Update erase operation function
  arm64: versal: Enable soft reset support for xspi flashes
  mtd: spi-nor: Enable DDR mode functionality with ISSI flash
  mtd: spi-nor: Enable DDR mode functionality with Gigadevice flash
  mtd: spi-nor: Enable DDR mode functionality with Macronix flash

Venkatesh Yadav Abbarapu (1):
  mtd: spi-nor: Update block protection flags for flash parts

 configs/xilinx_versal_virt_defconfig |   3 +
 drivers/mtd/spi/sf_internal.h        |   2 +
 drivers/mtd/spi/spi-nor-core.c       | 185 ++++++++++---
 drivers/mtd/spi/spi-nor-ids.c        |  36 +--
 drivers/spi/cadence_ospi_versal.c    |  76 +++++-
 drivers/spi/cadence_qspi.c           | 378 ++++++++++++++++++++++++++-
 drivers/spi/cadence_qspi.h           |  57 ++++
 drivers/spi/cadence_qspi_apb.c       |  73 +++++-
 include/spi.h                        |   7 +-
 9 files changed, 740 insertions(+), 77 deletions(-)

-- 
2.27.0


             reply	other threads:[~2024-03-11 17:23 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-03-11 17:22 Tejas Bhumkar [this message]
2024-03-11 17:22 ` [PATCH 01/19] spi: cadence_qspi: Add support for DDR PHY mode Tejas Bhumkar
2024-03-13  8:57   ` Dan Carpenter
2024-03-20  6:58     ` Bhumkar, Tejas Arvind
2024-03-11 17:22 ` [PATCH 02/19] spi: cadence-qspi: reset the ospi controller Tejas Bhumkar
2024-03-11 17:22 ` [PATCH 03/19] spi: cadence_ospi_versal: ospi ddr changes in cadence ospi versal driver Tejas Bhumkar
2024-03-11 17:22 ` [PATCH 04/19] spi: cadence_qspi: Write aligned byte length to ahbbase Tejas Bhumkar
2024-03-11 17:22 ` [PATCH 05/19] spi: cadence_qspi: Clean up registers in init Tejas Bhumkar
2024-03-11 17:22 ` [PATCH 06/19] spi: cadence_qspi: Initialize read and write watermark registers Tejas Bhumkar
2024-03-11 17:22 ` [PATCH 07/19] mtd: spi-nor: Enable mt35xu512aba_fixups for all mt35xx flashes Tejas Bhumkar
2024-03-11 17:22 ` [PATCH 08/19] arm64: versal: Enable defconfig for Micron octal flashes Tejas Bhumkar
2024-03-11 17:22 ` [PATCH 09/19] mtd: spi-nor: Update block protection flags for flash parts Tejas Bhumkar
2024-03-11 17:22 ` [PATCH 10/19] mtd: spi-nor: Check SNOR_F_IO_MODE_EN_VOLATILE only if SFDP is enabled Tejas Bhumkar
2024-03-11 17:22 ` [PATCH 11/19] spi: cadence_qspi: Add spi mem dtr support ops Tejas Bhumkar
2024-03-11 17:22 ` [PATCH 12/19] mtd: spi-nor: Update erase operation function Tejas Bhumkar
2024-03-11 17:22 ` [PATCH 13/19] mtd: spi-nor: Add support for cross die read in dual flash configuration Tejas Bhumkar
2024-03-11 17:22 ` [PATCH 14/19] mtd: spi-nor: Enable DTR octal flash program Tejas Bhumkar
2024-03-11 17:22 ` [PATCH 15/19] spi: mtd: Use split reads if multi-die flag is set Tejas Bhumkar
2024-03-11 17:22 ` [PATCH 16/19] arm64: versal: Enable soft reset support for xspi flashes Tejas Bhumkar
2024-03-11 17:22 ` [PATCH 17/19] mtd: spi-nor: Enable DDR mode functionality with ISSI flash Tejas Bhumkar
2024-03-11 17:22 ` [PATCH 18/19] mtd: spi-nor: Enable DDR mode functionality with Gigadevice flash Tejas Bhumkar
2024-03-11 17:22 ` [PATCH 19/19] mtd: spi-nor: Enable DDR mode functionality with Macronix flash Tejas Bhumkar

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=cover.1710098033.git.tejas.arvind.bhumkar@amd.com \
    --to=tejas.arvind.bhumkar@amd.com \
    --cc=git@amd.com \
    --cc=jagan@amarulasolutions.com \
    --cc=michal.simek@amd.com \
    --cc=n-francis@ti.com \
    --cc=u-boot@lists.denx.de \
    --cc=venkatesh.abbarapu@amd.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox