[PATCH 0/3] net: zynq_gem: driver enhancement

[PATCH 0/3] net: zynq_gem: driver enhancement

[Michal Simek]

Hi,

on cache coherent system some operations are not working properly
hence these 3 patches.
Boardcast one is just optimization to ignore packets which are not for us.
TXSR is actual fix for coherent system.
dma-coherent flag handling is nice to have but don't expect any performance
improvement.

Thanks,
Michal


Michal Simek (2):
  net: zynq_gem: Disable broadcast packets
  net: zynq_gem: Add support for dma-coherent flag

Padmarao Begari (1):
  net: zynq_gem: clear TXSR transfer complete

 drivers/net/zynq_gem.c | 34 +++++++++++++++++++++++++---------
 1 file changed, 25 insertions(+), 9 deletions(-)

-- 
2.43.0

base-commit: 1f3f1426a8ad7123de58103913eea84c84ce08bf
branch: debian-sent3

[PATCH 1/3] net: zynq_gem: Disable broadcast packets

[Michal Simek]

There is no reason to react on broadcast packets that's why just ignore
them not to waste cycles on packets which are not for the platform.

Signed-off-by: Michal Simek <michal.simek@amd.com>
---

 drivers/net/zynq_gem.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 407b022508ca..b05c752b17eb 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -64,6 +64,7 @@
 #define ZYNQ_GEM_NWCFG_SPEED100		0x00000001 /* 100 Mbps operation */
 #define ZYNQ_GEM_NWCFG_SPEED1000	0x00000400 /* 1Gbps operation */
 #define ZYNQ_GEM_NWCFG_FDEN		0x00000002 /* Full Duplex mode */
+#define ZYNQ_GEM_NWCFG_NBC		0x00000020 /* No broadcast */
 #define ZYNQ_GEM_NWCFG_FSREM		0x00020000 /* FCS removal */
 #define ZYNQ_GEM_NWCFG_SGMII_ENBL	0x08000000 /* SGMII Enable */
 #define ZYNQ_GEM_NWCFG_PCS_SEL		0x00000800 /* PCS select */
@@ -76,6 +77,7 @@
 
 #define ZYNQ_GEM_NWCFG_INIT		(ZYNQ_GEM_DBUS_WIDTH | \
 					ZYNQ_GEM_NWCFG_FDEN | \
+					ZYNQ_GEM_NWCFG_NBC | \
 					ZYNQ_GEM_NWCFG_FSREM)
 
 #define ZYNQ_GEM_NWSR_MDIOIDLE_MASK	0x00000004 /* PHY management idle */
-- 
2.43.0

[PATCH 2/3] net: zynq_gem: clear TXSR transfer complete

[Michal Simek]

From: Padmarao Begari <padmarao.begari@amd.com>

The Zynq GEM TX status register retains the transfer‑complete bit
until it is explicitly cleared. The current flow waits for
transfer‑complete but never clears it, so on the next send the wait
loop returns immediately because transfer‑complete is already high.
This causes the driver to report TX completion before the new DMA
transfer has actually finished, which breaks back‑to‑back
transmissions. This issue causes timeouts during LWIP TFTP transfers
when cache coherency is enabled.
Fix this by explicitly clearing transfer‑complete (write‑to‑clear)
after the wait completes, so each transmit starts with a clean TXSR.

Co-developed-by: Harini Katakam <harini.katakam@amd.com>
Signed-off-by: Harini Katakam <harini.katakam@amd.com>
Co-developed-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Padmarao Begari <padmarao.begari@amd.com>
Message-ID: <20260227144530.505233-1-padmarao.begari@amd.com>
---

 drivers/net/zynq_gem.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index b05c752b17eb..41883a440528 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -693,6 +693,7 @@ static int zynq_gem_send(struct udevice *dev, void *ptr, int len)
 {
 	dma_addr_t addr;
 	u32 size;
+	int ret;
 	struct zynq_gem_priv *priv = dev_get_priv(dev);
 	struct zynq_gem_regs *regs = priv->iobase;
 	struct emac_bd *current_bd = &priv->tx_bd[1];
@@ -734,8 +735,13 @@ static int zynq_gem_send(struct udevice *dev, void *ptr, int len)
 	if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED)
 		printf("TX buffers exhausted in mid frame\n");
 
-	return wait_for_bit_le32(&regs->txsr, ZYNQ_GEM_TSR_DONE,
-				 true, 20000, true);
+	ret = wait_for_bit_le32(&regs->txsr, ZYNQ_GEM_TSR_DONE,
+				true, 20000, true);
+
+	/* Clear the transfer complete */
+	setbits_le32(&regs->txsr, ZYNQ_GEM_TSR_DONE);
+
+	return ret;
 }
 
 /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */
-- 
2.43.0

[PATCH 3/3] net: zynq_gem: Add support for dma-coherent flag

[Michal Simek]

When dma-coherent DT property is passed there is no need to do any cache
operations.

Signed-off-by: Michal Simek <michal.simek@amd.com>
---

 drivers/net/zynq_gem.c | 22 +++++++++++++++-------
 1 file changed, 15 insertions(+), 7 deletions(-)

diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 41883a440528..a50d5aee03fe 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -258,6 +258,7 @@ struct zynq_gem_priv {
 	struct clk pclk;
 	u32 max_speed;
 	bool dma_64bit;
+	bool cache_on;
 	u32 clk_en_info;
 	struct reset_ctl_bulk resets;
 };
@@ -725,7 +726,8 @@ static int zynq_gem_send(struct udevice *dev, void *ptr, int len)
 	addr = (ulong) ptr;
 	addr &= ~(ARCH_DMA_MINALIGN - 1);
 	size = roundup(len, ARCH_DMA_MINALIGN);
-	flush_dcache_range(addr, addr + size);
+	if (priv->cache_on)
+		flush_dcache_range(addr, addr + size);
 	barrier();
 
 	/* Start transmit */
@@ -777,7 +779,8 @@ static int zynq_gem_recv(struct udevice *dev, int flags, uchar **packetp)
 
 	*packetp = (uchar *)(uintptr_t)addr;
 
-	invalidate_dcache_range(addr, addr + roundup(PKTSIZE_ALIGN, ARCH_DMA_MINALIGN));
+	if (priv->cache_on)
+		invalidate_dcache_range(addr, addr + roundup(PKTSIZE_ALIGN, ARCH_DMA_MINALIGN));
 	barrier();
 
 	return frame_len;
@@ -810,8 +813,8 @@ static int zynq_gem_free_pkt(struct udevice *dev, uchar *packet, int length)
 #else
 	addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK;
 #endif
-	flush_dcache_range(addr, addr + roundup(PKTSIZE_ALIGN,
-						ARCH_DMA_MINALIGN));
+	if (priv->cache_on)
+		flush_dcache_range(addr, addr + roundup(PKTSIZE_ALIGN, ARCH_DMA_MINALIGN));
 	barrier();
 
 	if ((++priv->rxbd_current) >= RX_BUF)
@@ -934,7 +937,8 @@ static int zynq_gem_probe(struct udevice *dev)
 
 	memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN);
 	ulong addr = (ulong)priv->rxbuffers;
-	flush_dcache_range(addr, addr + roundup(RX_BUF * PKTSIZE_ALIGN, ARCH_DMA_MINALIGN));
+	if (priv->cache_on)
+		flush_dcache_range(addr, addr + roundup(RX_BUF * PKTSIZE_ALIGN, ARCH_DMA_MINALIGN));
 	barrier();
 
 	/* Align bd_space to MMU_SECTION_SHIFT */
@@ -944,8 +948,9 @@ static int zynq_gem_probe(struct udevice *dev)
 		goto err1;
 	}
 
-	mmu_set_region_dcache_behaviour((phys_addr_t)bd_space,
-					BD_SPACE, DCACHE_OFF);
+	if (priv->cache_on)
+		mmu_set_region_dcache_behaviour((phys_addr_t)bd_space,
+						BD_SPACE, DCACHE_OFF);
 
 	/* Initialize the bd spaces for tx and rx bd's */
 	priv->tx_bd = (struct emac_bd *)bd_space;
@@ -1058,6 +1063,9 @@ static int zynq_gem_of_to_plat(struct udevice *dev)
 	/* Hardcode for now */
 	priv->phyaddr = -1;
 
+	if (!dev_read_bool(dev, "dma-coherent"))
+		priv->cache_on = true;
+
 	if (!dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
 					&phandle_args)) {
 		fdt_addr_t addr;
-- 
2.43.0

Re: [PATCH 0/3] net: zynq_gem: driver enhancement

[Michal Simek]

On 3/2/26 08:43, Michal Simek wrote:
> Hi,
> 
> on cache coherent system some operations are not working properly
> hence these 3 patches.
> Boardcast one is just optimization to ignore packets which are not for us.
> TXSR is actual fix for coherent system.
> dma-coherent flag handling is nice to have but don't expect any performance
> improvement.
> 
> Thanks,
> Michal
> 
> 
> Michal Simek (2):
>    net: zynq_gem: Disable broadcast packets
>    net: zynq_gem: Add support for dma-coherent flag
> 
> Padmarao Begari (1):
>    net: zynq_gem: clear TXSR transfer complete
> 
>   drivers/net/zynq_gem.c | 34 +++++++++++++++++++++++++---------
>   1 file changed, 25 insertions(+), 9 deletions(-)
> 

Applied.
M