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Wed, 27 Sep 2023 08:56:11 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id A02B6100062; Wed, 27 Sep 2023 08:56:10 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 9AA99212FA2; Wed, 27 Sep 2023 08:56:10 +0200 (CEST) Received: from [10.201.20.38] (10.201.20.38) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Wed, 27 Sep 2023 08:56:10 +0200 Message-ID: Date: Wed, 27 Sep 2023 08:56:09 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH v3 3/7] rng: stm32: Implement configurable RNG clock error detection Content-Language: en-US To: Gatien Chevallier , CC: Patrick Delaunay , Sughosh Ganu , Heinrich Schuchardt , References: <20230919152759.327420-1-gatien.chevallier@foss.st.com> <20230919152759.327420-4-gatien.chevallier@foss.st.com> From: Patrice CHOTARD In-Reply-To: <20230919152759.327420-4-gatien.chevallier@foss.st.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.201.20.38] X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-09-27_03,2023-09-26_01,2023-05-22_02 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean On 9/19/23 17:27, Gatien Chevallier wrote: > RNG clock error detection is now enabled if the "clock-error-detect" > property is set in the device tree. > > Signed-off-by: Gatien Chevallier > Reviewed-by: Patrick Delaunay > --- > Changes in V2: > - Added Patrick's tag > > drivers/rng/stm32_rng.c | 22 +++++++++++++++++----- > 1 file changed, 17 insertions(+), 5 deletions(-) > > diff --git a/drivers/rng/stm32_rng.c b/drivers/rng/stm32_rng.c > index 89da78c6c8..ada5d92214 100644 > --- a/drivers/rng/stm32_rng.c > +++ b/drivers/rng/stm32_rng.c > @@ -40,6 +40,7 @@ struct stm32_rng_plat { > struct clk clk; > struct reset_ctl rst; > const struct stm32_rng_data *data; > + bool ced; > }; > > static int stm32_rng_read(struct udevice *dev, void *data, size_t len) > @@ -97,25 +98,34 @@ static int stm32_rng_init(struct stm32_rng_plat *pdata) > > cr = readl(pdata->base + RNG_CR); > > - /* Disable CED */ > - cr |= RNG_CR_CED; > if (pdata->data->has_cond_reset) { > cr |= RNG_CR_CONDRST; > + if (pdata->ced) > + cr &= ~RNG_CR_CED; > + else > + cr |= RNG_CR_CED; > writel(cr, pdata->base + RNG_CR); > cr &= ~RNG_CR_CONDRST; > + cr |= RNG_CR_RNGEN; > writel(cr, pdata->base + RNG_CR); > err = readl_poll_timeout(pdata->base + RNG_CR, cr, > (!(cr & RNG_CR_CONDRST)), 10000); > if (err) > return err; > + } else { > + if (pdata->ced) > + cr &= ~RNG_CR_CED; > + else > + cr |= RNG_CR_CED; > + > + cr |= RNG_CR_RNGEN; > + > + writel(cr, pdata->base + RNG_CR); > } > > /* clear error indicators */ > writel(0, pdata->base + RNG_SR); > > - cr |= RNG_CR_RNGEN; > - writel(cr, pdata->base + RNG_CR); > - > err = readl_poll_timeout(pdata->base + RNG_SR, sr, > sr & RNG_SR_DRDY, 10000); > return err; > @@ -165,6 +175,8 @@ static int stm32_rng_of_to_plat(struct udevice *dev) > if (err) > return err; > > + pdata->ced = dev_read_bool(dev, "clock-error-detect"); > + > return 0; > } > Reviewed-by: Patrice Chotard Thanks Patrice