RE: [PATCH v6 4/7] mtd: spi-nor-ids: Add 4K page support for Macronix MX25L25635E

[<Takahiro.Kuwano@infineon.com>]

Hi,

In Subject,
s/4K page/4K sector/

> MX25L25635E supports 4KB/32KB/64KB uniform erase sector/blocks.
> 
> Link: https://www.mxic.com.tw/Lists/Datasheet/Attachments/8592/MX25L25635E,%203V,%20256Mb,%20v1.3.pdf
> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
> ---
> v5-v6: not changed
> v3-v4: updated commit message
> v2: not changed
> ---
>  drivers/mtd/spi/spi-nor-ids.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
> index 4d07221ae65..018a8341553 100644
> --- a/drivers/mtd/spi/spi-nor-ids.c
> +++ b/drivers/mtd/spi/spi-nor-ids.c
> @@ -323,7 +323,7 @@ const struct flash_info spi_nor_ids[] = {
>         { INFO("mx25u51245g", 0xc2253a, 0, 64 * 1024, 1024, SECT_4K |
>                SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
>         { INFO("mx25l12855e", 0xc22618, 0, 64 * 1024, 256, 0) },
> -       { INFO("mx25l25635e", 0xc22019, 0, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> +       { INFO("mx25l25635e", 0xc22019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },

Like as some chips in this series, this chip doesn't support PP_1_1_4 (32h).
Maybe using SFDP can correct the chip capability.
If you tested this chip, it would be good to describe test conditions, such
as SFDP used (or not), read/program protocols, and so forth. 

This is a pre-existing issue in core that adds PP_1_1_4 capability along with
READ_1_1_4.

>         { INFO("mx25u25635f", 0xc22539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_4B_OPCODES) },
>         { INFO("mx25v8035f",  0xc22314, 0, 64 * 1024,  16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
>         { INFO("mx25r1635f",  0xc22815, 0, 64 * 1024,  32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> --
> 2.45.2

Thanks,
Takahiro