From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 16EB1C54798 for ; Tue, 27 Feb 2024 04:25:13 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 8A7EF87FB6; Tue, 27 Feb 2024 05:25:11 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="XputJF/7"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 58CCC87FC2; Tue, 27 Feb 2024 05:25:10 +0100 (CET) Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 55F0387FAC for ; Tue, 27 Feb 2024 05:25:08 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=n-francis@ti.com Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 41R4P2G6044205; Mon, 26 Feb 2024 22:25:02 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1709007902; bh=MGTadAE98Ku+tji2eTfzQHC20Bhw5/lgM/zln83CbyU=; h=Date:Subject:To:CC:References:From:In-Reply-To; b=XputJF/7+fAfSKJA4s46u4C+lm84E3MtYNWBaSURP7EGeJxlNSdkWglKayYsKzSgm oe7ZLY0q7oGopRSarPJtDPPisJb7EHVhIogPN9XgwLwTWy8KioC3c3i3GlCbWxp/ge ZOQfPz0n3exhlh8KxK885BCn2qjR4VInty3edF5E= Received: from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 41R4P25T005360 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 26 Feb 2024 22:25:02 -0600 Received: from DFLE110.ent.ti.com (10.64.6.31) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 26 Feb 2024 22:25:02 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 26 Feb 2024 22:25:02 -0600 Received: from [172.24.227.36] (a0497641-hp-z2-tower-g9-workstation-desktop-pc.dhcp.ti.com [172.24.227.36]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 41R4NfLS076249; Mon, 26 Feb 2024 22:24:57 -0600 Message-ID: Date: Tue, 27 Feb 2024 09:54:57 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 04/13] ram: k3-ddrss: enable the am62ax's DDR controller for am62px Content-Language: en-US To: Bryan Brattlof , Tom Rini , Jaehoon Chung , Lukasz Majewski , Sean Anderson , Vignesh Raghavendra CC: U-Boot Mailing List , Simon Glass , Sumit Garg , Nishanth Menon , Andrew Davis , Igor Opaniuk , Hari Nagalla , Ravi Gunasekaran , Vaishnav Achath , Jayesh Choudhary References: <20240205-am62px-wip-rebasing-v3-0-04cbb42eaa6f@ti.com> <20240205-am62px-wip-rebasing-v3-4-04cbb42eaa6f@ti.com> From: Neha Malcom Francis In-Reply-To: <20240205-am62px-wip-rebasing-v3-4-04cbb42eaa6f@ti.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean On 27/02/24 02:49, Bryan Brattlof wrote: > The am62px family of SoCs uses the same DDR controller as found on the > am62ax family. Enable this option when building for the am62px family > > Signed-off-by: Bryan Brattlof > --- > drivers/ram/Kconfig | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig > index 5b07e92030142..56391058567bb 100644 > --- a/drivers/ram/Kconfig > +++ b/drivers/ram/Kconfig > @@ -65,7 +65,7 @@ choice > default K3_J721E_DDRSS if SOC_K3_J721E || SOC_K3_J721S2 > default K3_AM64_DDRSS if SOC_K3_AM642 > default K3_AM64_DDRSS if SOC_K3_AM625 > - default K3_AM62A_DDRSS if SOC_K3_AM62A7 > + default K3_AM62A_DDRSS if SOC_K3_AM62A7 || SOC_K3_AM62P5 > > config K3_J721E_DDRSS > bool "Enable J721E DDRSS support" > Reviewed-by: Neha Malcom Francis -- Thanking You Neha Malcom Francis