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From: Sean Anderson <seanga2@gmail.com>
To: u-boot@lists.denx.de
Subject: [PATCH v7 16/22] riscv: Enable cpu clock if it is present
Date: Sat, 2 May 2020 14:15:35 -0400	[thread overview]
Message-ID: <d53e368b-387c-af02-c2d2-667e6e429216@gmail.com> (raw)
In-Reply-To: <20200502100628.24809-17-pragnesh.patel@sifive.com>

On 5/2/20 6:06 AM, Pragnesh Patel wrote:
> The cpu clock is probably already enabled if we are executing code (though
> we could be executing from a different core). This patch prevents the cpu
> clock or its parents from being disabled.
> 
> Signed-off-by: Sean Anderson <seanga2@gmail.com>

If you make substantial changes can you please make a note of it in the
commit? I did not sign off on *this* code.

> Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>  drivers/cpu/riscv_cpu.c | 33 +++++++++++++++++++++++++++++++++
>  1 file changed, 33 insertions(+)
> 
> diff --git a/drivers/cpu/riscv_cpu.c b/drivers/cpu/riscv_cpu.c
> index 28ad0aa30f..8ebe0341fd 100644
> --- a/drivers/cpu/riscv_cpu.c
> +++ b/drivers/cpu/riscv_cpu.c
> @@ -9,6 +9,7 @@
>  #include <errno.h>
>  #include <dm/device-internal.h>
>  #include <dm/lists.h>
> +#include <clk.h>
>  
>  DECLARE_GLOBAL_DATA_PTR;
>  
> @@ -100,6 +101,37 @@ static int riscv_cpu_bind(struct udevice *dev)
>  	return 0;
>  }
>  
> +static int riscv_cpu_probe(struct udevice *dev)
> +{
> +	int ret = 0;
> +	u32 clock = 0;
> +	struct clk clk;
> +
> +	/* Get a clock if it exists */
> +	ret = clk_get_by_index(dev, 0, &clk);
> +	if (ret)
> +		return 0;
> +
> +	ret = dev_read_u32(dev, "clock-frequency", &clock);

Ok, so as I understand it, your goal for your changes this patch is to
have a way to set the cpu frequency on startup. However, I think the
cpu-frequency property is not the correct way to go about this when we
have a clock from the device tree. In this case, one should use the
assigned-clock* properties to have the frequency set automatically when
clk_get_by_index is called. There is no need to add this functionality
here.

With the previous patch in the series you pulled this from [1], one
could easily do something like

cpus {
	assigned-clocks = <&foo FOO_CPU>;
	assigned-clock-frequency = <100000000>;
	cpu at 0 {
		/* ... */
		clocks = <&foo FOO_CPU>;
		/* ... */
	};
};

which would use existing code to assign the frequency.

[1] https://patchwork.ozlabs.org/project/uboot/patch/20200423023320.1380090-18-seanga2 at gmail.com/

> +	if (ret) {
> +		debug("clock-frequency not found in dt %d\n", ret);

This should not be an error. You also need to check for ENOSYS and
ENOTSUPP like below.

> +		return ret;
> +	} else {
> +		ret = clk_set_rate(&clk, clock);
> +		if (ret < 0) {
> +			debug("Could not set CPU clock\n");

Neither should this be.

> +			return ret;
> +		}
> +	}
> +
> +	ret = clk_enable(&clk);
> +	clk_free(&clk);
> +	if (ret == -ENOSYS || ret == -ENOTSUPP)

All clk_ calls can return ENOSYS and ENOTSUPP. These are returned when
the underlying clock does not support the operation. However, they are
not appropriate errors to return from this function.

> +		return 0;
> +	else
> +		return ret;
> +}
> +
>  static const struct cpu_ops riscv_cpu_ops = {
>  	.get_desc	= riscv_cpu_get_desc,
>  	.get_info	= riscv_cpu_get_info,
> @@ -116,6 +148,7 @@ U_BOOT_DRIVER(riscv_cpu) = {
>  	.id = UCLASS_CPU,
>  	.of_match = riscv_cpu_ids,
>  	.bind = riscv_cpu_bind,
> +	.probe = riscv_cpu_probe,
>  	.ops = &riscv_cpu_ops,
>  	.flags = DM_FLAG_PRE_RELOC,
>  };
> 

--Sean

  parent reply	other threads:[~2020-05-02 18:15 UTC|newest]

Thread overview: 118+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-02 10:06 [PATCH v7 00/22] RISC-V SiFive FU540 support SPL Pragnesh Patel
2020-05-02 10:06 ` [PATCH v7 01/22] misc: add driver for the SiFive otp controller Pragnesh Patel
2020-05-02 12:28   ` Bin Meng
2020-05-02 15:37   ` Jagan Teki
2020-05-02 15:42     ` Pragnesh Patel
2020-05-02 15:50       ` Jagan Teki
2020-05-02 16:18         ` Pragnesh Patel
2020-05-10  9:04           ` Jagan Teki
2020-05-11  5:39             ` Pragnesh Patel
2020-05-02 10:06 ` [PATCH v7 02/22] riscv: sifive: fu540: Use OTP DM driver for serial environment variable Pragnesh Patel
2020-05-02 12:28   ` Bin Meng
2020-05-02 10:06 ` [PATCH v7 03/22] riscv: Add _image_binary_end for SPL Pragnesh Patel
2020-05-02 12:28   ` Bin Meng
2020-05-02 10:06 ` [PATCH v7 04/22] lib: Makefile: build crc7.c when CONFIG_MMC_SPI Pragnesh Patel
2020-05-02 10:29   ` Heinrich Schuchardt
2020-05-02 11:47     ` Bin Meng
2020-05-02 12:58       ` Heinrich Schuchardt
2020-05-02 15:33         ` Jagan Teki
2020-05-04  5:45           ` Pragnesh Patel
2020-05-05 15:55             ` Pragnesh Patel
2020-05-08  5:59               ` Pragnesh Patel
2020-05-03  9:54         ` Pragnesh Patel
2020-05-02 12:28   ` Bin Meng
2020-05-02 10:06 ` [PATCH v7 05/22] riscv: sifive: dts: fu540: Add board -u-boot.dtsi files Pragnesh Patel
2020-05-02 10:06 ` [PATCH v7 06/22] sifive: fu540: add ddr driver Pragnesh Patel
2020-05-02 12:28   ` Bin Meng
2020-05-02 15:59   ` Jagan Teki
2020-05-02 16:32     ` Pragnesh Patel
2020-05-02 10:06 ` [PATCH v7 07/22] sifive: dts: fu540: Add DDR controller and phy register settings Pragnesh Patel
2020-05-02 12:28   ` Bin Meng
2020-05-02 14:41     ` Pragnesh Patel
2020-05-02 10:06 ` [PATCH v7 08/22] riscv: sifive: dts: fu540: add U-Boot dmc node Pragnesh Patel
2020-05-02 12:29   ` Bin Meng
2020-05-02 10:06 ` [PATCH v7 09/22] clk: sifive: fu540-prci: Add clock enable and disable ops Pragnesh Patel
2020-05-02 12:29   ` Bin Meng
2020-05-02 10:06 ` [PATCH v7 10/22] clk: sifive: fu540-prci: ddr and ethernet clock initialization in SPL Pragnesh Patel
2020-05-02 12:28   ` Bin Meng
2020-05-02 14:49     ` Pragnesh Patel
2020-05-09 11:29       ` Pragnesh Patel
2020-05-02 16:14   ` Jagan Teki
2020-05-02 16:35     ` Pragnesh Patel
2020-05-02 16:44       ` Jagan Teki
2020-05-03  8:57         ` Pragnesh Patel
2020-05-02 10:06 ` [PATCH v7 11/22] riscv: dts: sifive: Sync hifive-unleashed-a00 dts from linux Pragnesh Patel
2020-05-02 10:06 ` [PATCH v7 12/22] sifive: dts: fu540: Enable gpio in U-Boot SPL Pragnesh Patel
2020-05-02 10:06 ` [PATCH v7 13/22] riscv: cpu: fu540: Add support for cpu fu540 Pragnesh Patel
2020-05-02 12:32   ` Bin Meng
2020-05-02 14:38     ` Pragnesh Patel
2020-05-02 16:34   ` Jagan Teki
2020-05-03  9:16     ` Pragnesh Patel
2020-05-02 10:06 ` [PATCH v7 14/22] riscv: Add place-holder for driver compilation Pragnesh Patel
2020-05-02 12:43   ` Bin Meng
2020-05-02 16:27   ` Jagan Teki
2020-05-03  9:17     ` Pragnesh Patel
2020-05-10  9:12       ` Jagan Teki
2020-05-11  5:58         ` Pragnesh Patel
2020-05-11  6:53           ` Jagan Teki
2020-05-11  7:10             ` Pragnesh Patel
2020-05-02 10:06 ` [PATCH v7 15/22] riscv: sifive: dts: fu540: Add clock for cpus node Pragnesh Patel
2020-05-02 12:43   ` Bin Meng
2020-05-02 16:50   ` Jagan Teki
2020-05-03  8:55     ` Pragnesh Patel
2020-05-02 10:06 ` [PATCH v7 16/22] riscv: Enable cpu clock if it is present Pragnesh Patel
2020-05-02 12:55   ` Bin Meng
2020-05-02 18:15   ` Sean Anderson [this message]
2020-05-03  7:12     ` Pragnesh Patel
2020-05-03 17:17       ` Sean Anderson
2020-05-04  5:20         ` Pragnesh Patel
2020-05-02 10:06 ` [PATCH v7 17/22] riscv: sifive: fu540: add SPL configuration Pragnesh Patel
2020-05-02 12:55   ` Bin Meng
2020-05-02 10:06 ` [PATCH v7 18/22] configs: fu540: Add config options for U-Boot SPL Pragnesh Patel
2020-05-02 12:55   ` Bin Meng
2020-05-02 14:37     ` Pragnesh Patel
2020-05-02 17:04     ` Jagan Teki
2020-05-02 16:51   ` Jagan Teki
2020-05-04 15:48     ` Pragnesh Patel
2020-05-02 17:15   ` Jagan Teki
2020-05-03  7:20     ` Pragnesh Patel
2020-05-02 10:06 ` [PATCH v7 19/22] sifive: dts: fu540: Enable L2 Cache in U-Boot Pragnesh Patel
2020-05-02 16:18   ` Jagan Teki
2020-05-02 16:42     ` Pragnesh Patel
2020-05-02 17:13       ` Jagan Teki
2020-05-03  7:27         ` Pragnesh Patel
2020-05-10  9:31           ` Jagan Teki
2020-05-11  6:05             ` Pragnesh Patel
2020-05-11  6:54               ` Jagan Teki
2020-05-11  7:07                 ` Pragnesh Patel
2020-05-11  7:25                   ` Jagan Teki
2020-05-11  7:45                     ` Pragnesh Patel
2020-05-11  8:48                       ` Jagan Teki
2020-05-11  9:00                         ` Bin Meng
2020-05-11  9:05                           ` Jagan Teki
2020-05-11  9:34                             ` Pragnesh Patel
2020-05-11  9:47                               ` Bin Meng
2020-05-11  9:55                                 ` Pragnesh Patel
2020-05-11 10:10                                   ` Bin Meng
2020-05-11 10:35                                     ` Pragnesh Patel
2020-05-12  1:20                                       ` Bin Meng
2020-05-12  7:45                                   ` Jagan Teki
2020-05-02 10:06 ` [PATCH v7 20/22] riscv: sifive: fu540: enable all cache ways from U-Boot proper Pragnesh Patel
2020-05-02 12:55   ` Bin Meng
2020-05-02 14:34     ` Pragnesh Patel
2020-05-02 10:06 ` [PATCH v7 21/22] doc: sifive: fu540: Add description for OpenSBI generic platform Pragnesh Patel
2020-05-02 12:55   ` Bin Meng
2020-05-02 14:30     ` Pragnesh Patel
2020-05-02 15:16       ` Bin Meng
2020-05-02 15:22         ` Pragnesh Patel
2020-05-02 15:27           ` Bin Meng
2020-05-02 15:29             ` Pragnesh Patel
2020-05-03  4:36             ` Anup Patel
2020-05-02 10:06 ` [PATCH v7 22/22] doc: sifive: fu540: Add description for RISC-V FU540 U-Boot SPL Pragnesh Patel
2020-05-02 12:55   ` Bin Meng
2020-05-02 16:22   ` Jagan Teki
2020-05-02 16:53     ` Pragnesh Patel
2020-05-03  4:34   ` Anup Patel
2020-05-03  6:13     ` Pragnesh Patel
2020-05-02 17:18 ` [PATCH v7 00/22] RISC-V SiFive FU540 support SPL Jagan Teki
2020-05-03  7:19   ` Pragnesh Patel

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