From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.3 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BCA9EC4338F for ; Tue, 10 Aug 2021 04:51:19 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DC14A6101D for ; Tue, 10 Aug 2021 04:51:18 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org DC14A6101D Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=lists.denx.de Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id B0E8382B4E; Tue, 10 Aug 2021 06:51:16 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="ttKZ664S"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 01FCF82BCE; Tue, 10 Aug 2021 06:51:15 +0200 (CEST) Received: from mail-qk1-x72a.google.com (mail-qk1-x72a.google.com [IPv6:2607:f8b0:4864:20::72a]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id C8F98829F9 for ; Tue, 10 Aug 2021 06:51:10 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=seanga2@gmail.com Received: by mail-qk1-x72a.google.com with SMTP id a19so21077562qkg.2 for ; Mon, 09 Aug 2021 21:51:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=subject:to:references:from:message-id:date:user-agent:mime-version :in-reply-to:content-language:content-transfer-encoding; bh=AfZqwQBhXDwmN5OSDS5kPdc4TodPwQ/++LB+aT6wrkQ=; b=ttKZ664S/kJfyQ78VMTsukXMc6j6vDsFj+P9i9AdUZkg9nMEORzjgPHf/uIM7H/Xi8 pF/lcWTx1mHP5qz3XSH6Dw84e80RZrsHz+7r02yKnHP/GQTFx9q1H8pqi+rqcHbRYMD9 i/HUibMuCHld2IaZoXp4NV2j5VO6mdhIHhoHm4CPpbtVrBIOeSjPpdSjgz/lkvJs3fru EkII7hgH1AcOZHXZqJ50TC4iCqUszUwePfruIEz0shjhYCKuBQe8Rg5M5TE95ijtrcvF lGkEbDKj9TZu3U5w3kesx1RWxjXLnmibUqmDyX8bF6/IHck0SA3UzZsD7D/4Af2PdiqR jKGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=AfZqwQBhXDwmN5OSDS5kPdc4TodPwQ/++LB+aT6wrkQ=; b=DZVcDEAV4SgBhSW637UTxejpqpBPDMVGFJcu5akNzBbxzI5cCO5WKWGtjaSL1LAYJR mpnt8RIWwW8Mux6udGFD9E7S2GrlvbycQHuEPMQ975DzEEfajTlOaxnl3U4Y0Agp24Du 8MdekBN91Zi1jNz+R8oIJfK6rh+tWLcPNF+PCeFiL8970PQFd/r5CHnm0VZ5n6kXK7h2 EbKjEHA9LMj9NiWQgFctAXAepj/tum+nvLaPUcxWn5D/K6VDh9L6yKEgl+MkFiKvuSWy cjm/hrRRRgq0gqhMVzRnFzZBk6OtsooUYrcvCPt83iVzNGgwoUdc6DGFymXRC4ZJDKzi b0RA== X-Gm-Message-State: AOAM533A+I6v4dz2xxm04z7VlViwI/DPDySMKNt85wLOXx2CEwifHrKv IMWYjyUjXRC/BciZ9fjxC+lBnMBVZ0E= X-Google-Smtp-Source: ABdhPJxw68iT5bhvD/HWXTqEbKu1sl5GW6qEXQzbyCk8gigrNjIxkwf/OyK8yWtURNJqRIugV9cm6w== X-Received: by 2002:a05:620a:cc1:: with SMTP id b1mr9613750qkj.47.1628571069497; Mon, 09 Aug 2021 21:51:09 -0700 (PDT) Received: from [192.168.1.201] (pool-74-96-87-9.washdc.fios.verizon.net. [74.96.87.9]) by smtp.googlemail.com with ESMTPSA id z9sm8046508qtn.54.2021.08.09.21.51.08 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 09 Aug 2021 21:51:09 -0700 (PDT) Subject: Re: [PATCH v2 2/6] board: sifive: use ccache driver instead of helper function To: Zong Li , rick@andestech.com, ycliang@andestech.com, bmeng.cn@gmail.com, green.wan@sifive.com, paul.walmsley@sifive.com, sjg@chromium.org, u-boot@lists.denx.de References: <20210803044444.14032-1-zong.li@sifive.com> <20210803044444.14032-3-zong.li@sifive.com> From: Sean Anderson Message-ID: Date: Tue, 10 Aug 2021 00:51:08 -0400 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.12.0 MIME-Version: 1.0 In-Reply-To: <20210803044444.14032-3-zong.li@sifive.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean On 8/3/21 12:44 AM, Zong Li wrote: > Invokes the generic cache_enable interface to execute the relative > implementation in SiFive ccache driver. > > Signed-off-by: Zong Li > --- > arch/riscv/cpu/fu540/Kconfig | 1 + > arch/riscv/cpu/fu540/cache.c | 54 ++++++----------------- > arch/riscv/cpu/fu740/Kconfig | 1 + > arch/riscv/cpu/fu740/cache.c | 52 ++++++---------------- > arch/riscv/include/asm/arch-fu540/cache.h | 2 +- > arch/riscv/include/asm/arch-fu740/cache.h | 2 +- > board/sifive/unleashed/unleashed.c | 10 +---- > board/sifive/unmatched/unmatched.c | 9 +--- > 8 files changed, 33 insertions(+), 98 deletions(-) > > diff --git a/arch/riscv/cpu/fu540/Kconfig b/arch/riscv/cpu/fu540/Kconfig > index 05463b2625..8608741779 100644 > --- a/arch/riscv/cpu/fu540/Kconfig > +++ b/arch/riscv/cpu/fu540/Kconfig > @@ -19,6 +19,7 @@ config SIFIVE_FU540 > imply SMP > imply CLK_SIFIVE > imply CLK_SIFIVE_PRCI > + imply SIFIVE_CCACHE > imply SIFIVE_SERIAL > imply MACB > imply MII > diff --git a/arch/riscv/cpu/fu540/cache.c b/arch/riscv/cpu/fu540/cache.c > index 0fc4ef6c00..bc31f664b8 100644 > --- a/arch/riscv/cpu/fu540/cache.c > +++ b/arch/riscv/cpu/fu540/cache.c > @@ -1,55 +1,29 @@ > // SPDX-License-Identifier: GPL-2.0+ > /* > - * Copyright (C) 2020 SiFive, Inc > + * Copyright (C) 2020 - 2021 SiFive, Inc > * > * Authors: > * Pragnesh Patel > */ > > #include > -#include > -#include > -#include > +#include > +#include > > -/* Register offsets */ > -#define L2_CACHE_CONFIG 0x000 > -#define L2_CACHE_ENABLE 0x008 > - > -#define MASK_NUM_WAYS GENMASK(15, 8) > -#define NUM_WAYS_SHIFT 8 > - > -DECLARE_GLOBAL_DATA_PTR; > - > -int cache_enable_ways(void) > +int sifive_ccache_enable_ways(void) > { > - const void *blob = gd->fdt_blob; > - int node; > - fdt_addr_t base; > - u32 config; > - u32 ways; > - > - volatile u32 *enable; > - > - node = fdt_node_offset_by_compatible(blob, -1, > - "sifive,fu540-c000-ccache"); > - > - if (node < 0) > - return node; > - > - base = fdtdec_get_addr_size_auto_parent(blob, 0, node, "reg", 0, > - NULL, false); > - if (base == FDT_ADDR_T_NONE) > - return FDT_ADDR_T_NONE; > + struct udevice *dev; > + int ret; > > - config = readl((volatile u32 *)base + L2_CACHE_CONFIG); > - ways = (config & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT; > + ret = uclass_get_device_by_driver(UCLASS_CACHE, > + DM_DRIVER_GET(sifive_ccache), > + &dev); > + if (ret) > + return log_msg_ret("Cannot enable cache ways", ret); > > - enable = (volatile u32 *)(base + L2_CACHE_ENABLE); > + ret = cache_enable(dev); > + if (ret) > + return log_msg_ret("ccache enable failed", ret); > > - /* memory barrier */ > - mb(); > - (*enable) = ways - 1; > - /* memory barrier */ > - mb(); > return 0; > } > diff --git a/arch/riscv/cpu/fu740/Kconfig b/arch/riscv/cpu/fu740/Kconfig > index 408195f149..b4cada0ea9 100644 > --- a/arch/riscv/cpu/fu740/Kconfig > +++ b/arch/riscv/cpu/fu740/Kconfig > @@ -19,6 +19,7 @@ config SIFIVE_FU740 > imply SMP > imply CLK_SIFIVE > imply CLK_SIFIVE_PRCI > + imply SIFIVE_CCACHE > imply SIFIVE_SERIAL > imply MACB > imply MII > diff --git a/arch/riscv/cpu/fu740/cache.c b/arch/riscv/cpu/fu740/cache.c > index 680955c9e3..e2782d76c0 100644 > --- a/arch/riscv/cpu/fu740/cache.c > +++ b/arch/riscv/cpu/fu740/cache.c > @@ -7,49 +7,23 @@ > */ > > #include > -#include > -#include > -#include > +#include > +#include > > -/* Register offsets */ > -#define L2_CACHE_CONFIG 0x000 > -#define L2_CACHE_ENABLE 0x008 > - > -#define MASK_NUM_WAYS GENMASK(15, 8) > -#define NUM_WAYS_SHIFT 8 > - > -DECLARE_GLOBAL_DATA_PTR; > - > -int cache_enable_ways(void) > +int sifive_ccache_enable_ways(void) > { > - const void *blob = gd->fdt_blob; > - int node; > - fdt_addr_t base; > - u32 config; > - u32 ways; > - > - volatile u32 *enable; > - > - node = fdt_node_offset_by_compatible(blob, -1, > - "sifive,fu740-c000-ccache"); > - > - if (node < 0) > - return node; > - > - base = fdtdec_get_addr_size_auto_parent(blob, 0, node, "reg", 0, > - NULL, false); > - if (base == FDT_ADDR_T_NONE) > - return FDT_ADDR_T_NONE; > + struct udevice *dev; > + int ret; > > - config = readl((volatile u32 *)base + L2_CACHE_CONFIG); > - ways = (config & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT; > + ret = uclass_get_device_by_driver(UCLASS_CACHE, > + DM_DRIVER_GET(sifive_ccache), > + &dev); > + if (ret) > + return log_msg_ret("Cannot enable cache ways", ret); > > - enable = (volatile u32 *)(base + L2_CACHE_ENABLE); > + ret = cache_enable(dev); > + if (ret) > + return log_msg_ret("ccache enable failed", ret); > > - /* memory barrier */ > - mb(); > - (*enable) = ways - 1; > - /* memory barrier */ > - mb(); > return 0; > } > diff --git a/arch/riscv/include/asm/arch-fu540/cache.h b/arch/riscv/include/asm/arch-fu540/cache.h > index 135a17c679..c252eb64d1 100644 > --- a/arch/riscv/include/asm/arch-fu540/cache.h > +++ b/arch/riscv/include/asm/arch-fu540/cache.h > @@ -9,6 +9,6 @@ > #ifndef _CACHE_SIFIVE_H > #define _CACHE_SIFIVE_H > > -int cache_enable_ways(void); > +int sifive_ccache_enable_ways(void); > > #endif /* _CACHE_SIFIVE_H */ > diff --git a/arch/riscv/include/asm/arch-fu740/cache.h b/arch/riscv/include/asm/arch-fu740/cache.h > index 7d4fe9942b..8c456e3658 100644 > --- a/arch/riscv/include/asm/arch-fu740/cache.h > +++ b/arch/riscv/include/asm/arch-fu740/cache.h > @@ -9,6 +9,6 @@ > #ifndef _CACHE_SIFIVE_H > #define _CACHE_SIFIVE_H > > -int cache_enable_ways(void); > +int sifive_ccache_enable_ways(void); > > #endif /* _CACHE_SIFIVE_H */ > diff --git a/board/sifive/unleashed/unleashed.c b/board/sifive/unleashed/unleashed.c > index 43027f0b54..12e61ec85f 100644 > --- a/board/sifive/unleashed/unleashed.c > +++ b/board/sifive/unleashed/unleashed.c > @@ -126,14 +126,6 @@ void *board_fdt_blob_setup(void) > > int board_init(void) > { > - int ret; > - > /* enable all cache ways */ > - ret = cache_enable_ways(); > - if (ret) { > - debug("%s: could not enable cache ways\n", __func__); > - return ret; > - } > - > - return 0; > + return sifive_ccache_enable_ways(); > } > diff --git a/board/sifive/unmatched/unmatched.c b/board/sifive/unmatched/unmatched.c > index 2f5629b578..d27c4d3e88 100644 > --- a/board/sifive/unmatched/unmatched.c > +++ b/board/sifive/unmatched/unmatched.c > @@ -23,13 +23,6 @@ void *board_fdt_blob_setup(void) > > int board_init(void) > { > - int ret; > - > /* enable all cache ways */ > - ret = cache_enable_ways(); > - if (ret) { > - debug("%s: could not enable cache ways\n", __func__); > - return ret; > - } > - return 0; > + return sifive_ccache_enable_ways(); > } > Can you combine patches 2-4 in some way? It seems like you add some code only to immediately refactor it. --Sean