From mboxrd@z Thu Jan  1 00:00:00 1970
From: Marc Zyngier <maz@kernel.org>
Date: Fri, 11 Dec 2020 10:48:43 +0000
Subject: [PATC 1/2H] board: fsl: ls2088ardb: Program GIC LPI configuration
 table
In-Reply-To: <20201207071436.22320-1-priyanka.jain@nxp.com>
References: <20201207071436.22320-1-priyanka.jain@nxp.com>
Message-ID: <d6a55a5a1eb59d47c8ca5fab11f26d90@kernel.org>
List-Id: <u-boot.lists.denx.de>
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
To: u-boot@lists.denx.de

On 2020-12-07 07:14, Priyanka Jain wrote:
> From: Nikhil Gupta <nikhil.gupta@nxp.com>
> 
> Add programming of GIC LPI configuration table:
> 1. Program Redistributor PROCBASER configuration table

The register name is GICR_PROPBASER.

>    which is common for all redistributors.
> 2. Program Redistributor pending table (PENDBASER), for
>    all the available redistributors.
> 3. Reserve DDR memory region used for GIC LPI configuration table.

I'm not convinced that's a good idea, but hey, why not.

> 
> Signed-off-by: Nikhil Gupta <nikhil.gupta@nxp.com>
> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
> ---
>  board/freescale/ls2080ardb/ls2080ardb.c | 27 ++++++++++++++++++++++++-
>  1 file changed, 26 insertions(+), 1 deletion(-)
> 
> diff --git a/board/freescale/ls2080ardb/ls2080ardb.c
> b/board/freescale/ls2080ardb/ls2080ardb.c
> index c7e9c1dacf..1c54bac529 100644
> --- a/board/freescale/ls2080ardb/ls2080ardb.c
> +++ b/board/freescale/ls2080ardb/ls2080ardb.c
> @@ -1,7 +1,7 @@
>  // SPDX-License-Identifier: GPL-2.0+
>  /*
>   * Copyright 2015 Freescale Semiconductor
> - * Copyright 2017 NXP
> + * Copyright 2017-2020 NXP
>   */
>  #include <common.h>
>  #include <env.h>
> @@ -24,7 +24,10 @@
>  #include <asm/arch/ppa.h>
>  #include <fsl_sec.h>
>  #include <asm/arch-fsl-layerscape/fsl_icid.h>
> +#include <asm/gic-v3.h>
> +#include <cpu_func.h>
> 
> +#define GIC_LPI_SIZE                             0x200000

Shouldn't you probe this from the HW instead of hardcoding it?

>  #ifdef CONFIG_FSL_QIXIS
>  #include "../common/qixis.h"
>  #include "ls2080ardb_qixis.h"
> @@ -352,6 +355,21 @@ void board_quiesce_devices(void)
>  }
>  #endif
> 
> +#ifdef CONFIG_GIC_V3_ITS
> +void fdt_fixup_gic_lpi_memory(void *blob, u64 gic_lpi_base)
> +{
> +	u32 phandle;
> +	int err;
> +	struct fdt_memory gic_lpi;
> +
> +	gic_lpi.start = gic_lpi_base;
> +	gic_lpi.end = gic_lpi_base + GIC_LPI_SIZE - 1;
> +	err = fdtdec_add_reserved_memory(blob, "gic-lpi", &gic_lpi, 
> &phandle);
> +	if (err < 0)
> +		debug("failed to add reserved memory: %d\n", err);
> +}
> +#endif
> +
>  #ifdef CONFIG_OF_BOARD_SETUP
>  void fsl_fdt_fixup_flash(void *fdt)
>  {
> @@ -426,6 +444,7 @@ int ft_board_setup(void *blob, struct bd_info *bd)
>  	u64 mc_memory_base = 0;
>  	u64 mc_memory_size = 0;
>  	u16 total_memory_banks;
> +	u64 gic_lpi_base;
> 
>  	ft_cpu_setup(blob, bd);
> 
> @@ -445,6 +464,12 @@ int ft_board_setup(void *blob, struct bd_info *bd)
>  	base[1] = gd->bd->bi_dram[1].start;
>  	size[1] = gd->bd->bi_dram[1].size;
> 
> +#ifdef CONFIG_GIC_V3_ITS
> +	gic_lpi_base = gd->arch.resv_ram - GIC_LPI_SIZE;
> +	gic_lpi_tables_init(gic_lpi_base, cpu_numcores());
> +	fdt_fixup_gic_lpi_memory(blob, gic_lpi_base);
> +#endif
> +
>  #ifdef CONFIG_RESV_RAM
>  	/* reduce size if reserved memory is within this bank */
>  	if (gd->arch.resv_ram >= base[0] &&

         M.
-- 
Jazz is not dead. It just smells funny...