* [PATCH v2 2/7] arm: dts: rockchip: rk3288: partial sync grf and pmu nodes
2023-03-15 18:31 [PATCH v2 1/7] arm: dts: rockchip: rk3288: move io-domains nodes Johan Jonker
@ 2023-03-15 18:33 ` Johan Jonker
2023-03-21 3:14 ` Kever Yang
2023-03-15 18:33 ` [PATCH v2 3/7] video: rockchip: rk_vop: add rk3288-dp compare string Johan Jonker
` (5 subsequent siblings)
6 siblings, 1 reply; 14+ messages in thread
From: Johan Jonker @ 2023-03-15 18:33 UTC (permalink / raw)
To: kever.yang
Cc: sjg, philipp.tomsich, w.egorov, hl, jernej.skrabec, lukma,
seanga2, agust, u-boot
In order to better compare the Linux rk3288.dtsi
version 6.3 -rc2 with the U-Boot version partial
sync the grf and pmu nodes.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org> # chromebook-jerry
---
arch/arm/dts/rk3288.dtsi | 269 +++++++++++++++++++++++++--------------
1 file changed, 173 insertions(+), 96 deletions(-)
diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi
index 9cfb86f9..f06d1f5b 100644
--- a/arch/arm/dts/rk3288.dtsi
+++ b/arch/arm/dts/rk3288.dtsi
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: GPL-2.0+
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
@@ -7,13 +7,16 @@
#include <dt-bindings/clock/rk3288-cru.h>
#include <dt-bindings/power/rk3288-power.h>
#include <dt-bindings/thermal/thermal.h>
-#include <dt-bindings/video/rk3288.h>
-#include "skeleton.dtsi"
+#include <dt-bindings/soc/rockchip,boot-mode.h>
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
compatible = "rockchip,rk3288";
interrupt-parent = <&gic>;
+
aliases {
ethernet0 = &gmac;
i2c0 = &i2c0;
@@ -732,8 +735,128 @@
};
pmu: power-management@ff730000 {
- compatible = "rockchip,rk3288-pmu", "syscon";
+ compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
reg = <0xff730000 0x100>;
+
+ power: power-controller {
+ compatible = "rockchip,rk3288-power-controller";
+ #power-domain-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ assigned-clocks = <&cru SCLK_EDP_24M>;
+ assigned-clock-parents = <&xin24m>;
+
+ /*
+ * Note: Although SCLK_* are the working clocks
+ * of device without including on the NOC, needed for
+ * synchronous reset.
+ *
+ * The clocks on the which NOC:
+ * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
+ * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
+ * ACLK_RGA is on ACLK_RGA_NIU.
+ * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
+ *
+ * Which clock are device clocks:
+ * clocks devices
+ * *_IEP IEP:Image Enhancement Processor
+ * *_ISP ISP:Image Signal Processing
+ * *_VIP VIP:Video Input Processor
+ * *_VOP* VOP:Visual Output Processor
+ * *_RGA RGA
+ * *_EDP* EDP
+ * *_LVDS_* LVDS
+ * *_HDMI HDMI
+ * *_MIPI_* MIPI
+ */
+ power-domain@RK3288_PD_VIO {
+ reg = <RK3288_PD_VIO>;
+ clocks = <&cru ACLK_IEP>,
+ <&cru ACLK_ISP>,
+ <&cru ACLK_RGA>,
+ <&cru ACLK_VIP>,
+ <&cru ACLK_VOP0>,
+ <&cru ACLK_VOP1>,
+ <&cru DCLK_VOP0>,
+ <&cru DCLK_VOP1>,
+ <&cru HCLK_IEP>,
+ <&cru HCLK_ISP>,
+ <&cru HCLK_RGA>,
+ <&cru HCLK_VIP>,
+ <&cru HCLK_VOP0>,
+ <&cru HCLK_VOP1>,
+ <&cru PCLK_EDP_CTRL>,
+ <&cru PCLK_HDMI_CTRL>,
+ <&cru PCLK_LVDS_PHY>,
+ <&cru PCLK_MIPI_CSI>,
+ <&cru PCLK_MIPI_DSI0>,
+ <&cru PCLK_MIPI_DSI1>,
+ <&cru SCLK_EDP_24M>,
+ <&cru SCLK_EDP>,
+ <&cru SCLK_ISP_JPE>,
+ <&cru SCLK_ISP>,
+ <&cru SCLK_RGA>;
+ pm_qos = <&qos_vio0_iep>,
+ <&qos_vio1_vop>,
+ <&qos_vio1_isp_w0>,
+ <&qos_vio1_isp_w1>,
+ <&qos_vio0_vop>,
+ <&qos_vio0_vip>,
+ <&qos_vio2_rga_r>,
+ <&qos_vio2_rga_w>,
+ <&qos_vio1_isp_r>;
+ #power-domain-cells = <0>;
+ };
+
+ /*
+ * Note: The following 3 are HEVC(H.265) clocks,
+ * and on the ACLK_HEVC_NIU (NOC).
+ */
+ power-domain@RK3288_PD_HEVC {
+ reg = <RK3288_PD_HEVC>;
+ clocks = <&cru ACLK_HEVC>,
+ <&cru SCLK_HEVC_CABAC>,
+ <&cru SCLK_HEVC_CORE>;
+ pm_qos = <&qos_hevc_r>,
+ <&qos_hevc_w>;
+ #power-domain-cells = <0>;
+ };
+
+ /*
+ * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
+ * (video endecoder & decoder) clocks that on the
+ * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
+ */
+ power-domain@RK3288_PD_VIDEO {
+ reg = <RK3288_PD_VIDEO>;
+ clocks = <&cru ACLK_VCODEC>,
+ <&cru HCLK_VCODEC>;
+ pm_qos = <&qos_video>;
+ #power-domain-cells = <0>;
+ };
+
+ /*
+ * Note: ACLK_GPU is the GPU clock,
+ * and on the ACLK_GPU_NIU (NOC).
+ */
+ power-domain@RK3288_PD_GPU {
+ reg = <RK3288_PD_GPU>;
+ clocks = <&cru ACLK_GPU>;
+ pm_qos = <&qos_gpu_r>,
+ <&qos_gpu_w>;
+ #power-domain-cells = <0>;
+ };
+ };
+
+ reboot-mode {
+ compatible = "syscon-reboot-mode";
+ offset = <0x94>;
+ mode-normal = <BOOT_NORMAL>;
+ mode-recovery = <BOOT_RECOVERY>;
+ mode-bootloader = <BOOT_FASTBOOT>;
+ mode-loader = <BOOT_BL_DOWNLOAD>;
+ };
};
sgrf: syscon@ff740000 {
@@ -760,13 +883,58 @@
};
grf: syscon@ff770000 {
- compatible = "rockchip,rk3288-grf", "syscon";
+ compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
reg = <0xff770000 0x1000>;
+ edp_phy: edp-phy {
+ compatible = "rockchip,rk3288-dp-phy";
+ clocks = <&cru SCLK_EDP_24M>;
+ clock-names = "24m";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
io_domains: io-domains {
compatible = "rockchip,rk3288-io-voltage-domain";
status = "disabled";
};
+
+ usbphy: usbphy {
+ compatible = "rockchip,rk3288-usb-phy";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ usbphy0: usb-phy@320 {
+ #phy-cells = <0>;
+ reg = <0x320>;
+ clocks = <&cru SCLK_OTGPHY0>;
+ clock-names = "phyclk";
+ #clock-cells = <0>;
+ resets = <&cru SRST_USBOTG_PHY>;
+ reset-names = "phy-reset";
+ };
+
+ usbphy1: usb-phy@334 {
+ #phy-cells = <0>;
+ reg = <0x334>;
+ clocks = <&cru SCLK_OTGPHY1>;
+ clock-names = "phyclk";
+ #clock-cells = <0>;
+ resets = <&cru SRST_USBHOST0_PHY>;
+ reset-names = "phy-reset";
+ };
+
+ usbphy2: usb-phy@348 {
+ #phy-cells = <0>;
+ reg = <0x348>;
+ clocks = <&cru SCLK_OTGPHY2>;
+ clock-names = "phyclk";
+ #clock-cells = <0>;
+ resets = <&cru SRST_USBHOST1_PHY>;
+ reset-names = "phy-reset";
+ };
+ };
};
wdt: watchdog@ff800000 {
@@ -1246,39 +1414,6 @@
interrupts = <GIC_PPI 9 0xf04>;
};
- cpuidle: cpuidle {
- compatible = "rockchip,rk3288-cpuidle";
- };
-
- usbphy: phy {
- compatible = "rockchip,rk3288-usb-phy";
- rockchip,grf = <&grf>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
-
- usbphy0: usb-phy0 {
- #phy-cells = <0>;
- reg = <0x320>;
- clocks = <&cru SCLK_OTGPHY0>;
- clock-names = "phyclk";
- };
-
- usbphy1: usb-phy1 {
- #phy-cells = <0>;
- reg = <0x334>;
- clocks = <&cru SCLK_OTGPHY1>;
- clock-names = "phyclk";
- };
-
- usbphy2: usb-phy2 {
- #phy-cells = <0>;
- reg = <0x348>;
- clocks = <&cru SCLK_OTGPHY2>;
- clock-names = "phyclk";
- };
- };
-
pinctrl: pinctrl {
compatible = "rockchip,rk3288-pinctrl";
rockchip,grf = <&grf>;
@@ -1865,62 +2000,4 @@
};
};
};
-
- power: power-controller {
- compatible = "rockchip,rk3288-power-controller";
- #power-domain-cells = <1>;
- rockchip,pmu = <&pmu>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- pd_gpu {
- reg = <RK3288_PD_GPU>;
- clocks = <&cru ACLK_GPU>;
- };
-
- pd_hevc {
- reg = <RK3288_PD_HEVC>;
- clocks = <&cru ACLK_HEVC>,
- <&cru SCLK_HEVC_CABAC>,
- <&cru SCLK_HEVC_CORE>,
- <&cru HCLK_HEVC>;
- };
-
- pd_vio {
- reg = <RK3288_PD_VIO>;
- clocks = <&cru ACLK_IEP>,
- <&cru ACLK_ISP>,
- <&cru ACLK_RGA>,
- <&cru ACLK_VIP>,
- <&cru ACLK_VOP0>,
- <&cru ACLK_VOP1>,
- <&cru DCLK_VOP0>,
- <&cru DCLK_VOP1>,
- <&cru HCLK_IEP>,
- <&cru HCLK_ISP>,
- <&cru HCLK_RGA>,
- <&cru HCLK_VIP>,
- <&cru HCLK_VOP0>,
- <&cru HCLK_VOP1>,
- <&cru PCLK_EDP_CTRL>,
- <&cru PCLK_HDMI_CTRL>,
- <&cru PCLK_LVDS_PHY>,
- <&cru PCLK_MIPI_CSI>,
- <&cru PCLK_MIPI_DSI0>,
- <&cru PCLK_MIPI_DSI1>,
- <&cru SCLK_EDP_24M>,
- <&cru SCLK_EDP>,
- <&cru SCLK_HDMI_CEC>,
- <&cru SCLK_HDMI_HDCP>,
- <&cru SCLK_ISP_JPE>,
- <&cru SCLK_ISP>,
- <&cru SCLK_RGA>;
- };
-
- pd_video {
- reg = <RK3288_PD_VIDEO>;
- clocks = <&cru ACLK_VCODEC>,
- <&cru HCLK_VCODEC>;
- };
- };
};
--
2.20.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v2 2/7] arm: dts: rockchip: rk3288: partial sync grf and pmu nodes
2023-03-15 18:33 ` [PATCH v2 2/7] arm: dts: rockchip: rk3288: partial sync grf and pmu nodes Johan Jonker
@ 2023-03-21 3:14 ` Kever Yang
0 siblings, 0 replies; 14+ messages in thread
From: Kever Yang @ 2023-03-21 3:14 UTC (permalink / raw)
To: Johan Jonker
Cc: sjg, philipp.tomsich, w.egorov, hl, jernej.skrabec, lukma,
seanga2, agust, u-boot
On 2023/3/16 02:33, Johan Jonker wrote:
> In order to better compare the Linux rk3288.dtsi
> version 6.3 -rc2 with the U-Boot version partial
> sync the grf and pmu nodes.
>
> Signed-off-by: Johan Jonker <jbx6244@gmail.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> Tested-by: Simon Glass <sjg@chromium.org> # chromebook-jerry
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> arch/arm/dts/rk3288.dtsi | 269 +++++++++++++++++++++++++--------------
> 1 file changed, 173 insertions(+), 96 deletions(-)
>
> diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi
> index 9cfb86f9..f06d1f5b 100644
> --- a/arch/arm/dts/rk3288.dtsi
> +++ b/arch/arm/dts/rk3288.dtsi
> @@ -1,4 +1,4 @@
> -// SPDX-License-Identifier: GPL-2.0+
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>
> #include <dt-bindings/gpio/gpio.h>
> #include <dt-bindings/interrupt-controller/irq.h>
> @@ -7,13 +7,16 @@
> #include <dt-bindings/clock/rk3288-cru.h>
> #include <dt-bindings/power/rk3288-power.h>
> #include <dt-bindings/thermal/thermal.h>
> -#include <dt-bindings/video/rk3288.h>
> -#include "skeleton.dtsi"
> +#include <dt-bindings/soc/rockchip,boot-mode.h>
>
> / {
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> compatible = "rockchip,rk3288";
>
> interrupt-parent = <&gic>;
> +
> aliases {
> ethernet0 = &gmac;
> i2c0 = &i2c0;
> @@ -732,8 +735,128 @@
> };
>
> pmu: power-management@ff730000 {
> - compatible = "rockchip,rk3288-pmu", "syscon";
> + compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
> reg = <0xff730000 0x100>;
> +
> + power: power-controller {
> + compatible = "rockchip,rk3288-power-controller";
> + #power-domain-cells = <1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + assigned-clocks = <&cru SCLK_EDP_24M>;
> + assigned-clock-parents = <&xin24m>;
> +
> + /*
> + * Note: Although SCLK_* are the working clocks
> + * of device without including on the NOC, needed for
> + * synchronous reset.
> + *
> + * The clocks on the which NOC:
> + * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
> + * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
> + * ACLK_RGA is on ACLK_RGA_NIU.
> + * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
> + *
> + * Which clock are device clocks:
> + * clocks devices
> + * *_IEP IEP:Image Enhancement Processor
> + * *_ISP ISP:Image Signal Processing
> + * *_VIP VIP:Video Input Processor
> + * *_VOP* VOP:Visual Output Processor
> + * *_RGA RGA
> + * *_EDP* EDP
> + * *_LVDS_* LVDS
> + * *_HDMI HDMI
> + * *_MIPI_* MIPI
> + */
> + power-domain@RK3288_PD_VIO {
> + reg = <RK3288_PD_VIO>;
> + clocks = <&cru ACLK_IEP>,
> + <&cru ACLK_ISP>,
> + <&cru ACLK_RGA>,
> + <&cru ACLK_VIP>,
> + <&cru ACLK_VOP0>,
> + <&cru ACLK_VOP1>,
> + <&cru DCLK_VOP0>,
> + <&cru DCLK_VOP1>,
> + <&cru HCLK_IEP>,
> + <&cru HCLK_ISP>,
> + <&cru HCLK_RGA>,
> + <&cru HCLK_VIP>,
> + <&cru HCLK_VOP0>,
> + <&cru HCLK_VOP1>,
> + <&cru PCLK_EDP_CTRL>,
> + <&cru PCLK_HDMI_CTRL>,
> + <&cru PCLK_LVDS_PHY>,
> + <&cru PCLK_MIPI_CSI>,
> + <&cru PCLK_MIPI_DSI0>,
> + <&cru PCLK_MIPI_DSI1>,
> + <&cru SCLK_EDP_24M>,
> + <&cru SCLK_EDP>,
> + <&cru SCLK_ISP_JPE>,
> + <&cru SCLK_ISP>,
> + <&cru SCLK_RGA>;
> + pm_qos = <&qos_vio0_iep>,
> + <&qos_vio1_vop>,
> + <&qos_vio1_isp_w0>,
> + <&qos_vio1_isp_w1>,
> + <&qos_vio0_vop>,
> + <&qos_vio0_vip>,
> + <&qos_vio2_rga_r>,
> + <&qos_vio2_rga_w>,
> + <&qos_vio1_isp_r>;
> + #power-domain-cells = <0>;
> + };
> +
> + /*
> + * Note: The following 3 are HEVC(H.265) clocks,
> + * and on the ACLK_HEVC_NIU (NOC).
> + */
> + power-domain@RK3288_PD_HEVC {
> + reg = <RK3288_PD_HEVC>;
> + clocks = <&cru ACLK_HEVC>,
> + <&cru SCLK_HEVC_CABAC>,
> + <&cru SCLK_HEVC_CORE>;
> + pm_qos = <&qos_hevc_r>,
> + <&qos_hevc_w>;
> + #power-domain-cells = <0>;
> + };
> +
> + /*
> + * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
> + * (video endecoder & decoder) clocks that on the
> + * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
> + */
> + power-domain@RK3288_PD_VIDEO {
> + reg = <RK3288_PD_VIDEO>;
> + clocks = <&cru ACLK_VCODEC>,
> + <&cru HCLK_VCODEC>;
> + pm_qos = <&qos_video>;
> + #power-domain-cells = <0>;
> + };
> +
> + /*
> + * Note: ACLK_GPU is the GPU clock,
> + * and on the ACLK_GPU_NIU (NOC).
> + */
> + power-domain@RK3288_PD_GPU {
> + reg = <RK3288_PD_GPU>;
> + clocks = <&cru ACLK_GPU>;
> + pm_qos = <&qos_gpu_r>,
> + <&qos_gpu_w>;
> + #power-domain-cells = <0>;
> + };
> + };
> +
> + reboot-mode {
> + compatible = "syscon-reboot-mode";
> + offset = <0x94>;
> + mode-normal = <BOOT_NORMAL>;
> + mode-recovery = <BOOT_RECOVERY>;
> + mode-bootloader = <BOOT_FASTBOOT>;
> + mode-loader = <BOOT_BL_DOWNLOAD>;
> + };
> };
>
> sgrf: syscon@ff740000 {
> @@ -760,13 +883,58 @@
> };
>
> grf: syscon@ff770000 {
> - compatible = "rockchip,rk3288-grf", "syscon";
> + compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
> reg = <0xff770000 0x1000>;
>
> + edp_phy: edp-phy {
> + compatible = "rockchip,rk3288-dp-phy";
> + clocks = <&cru SCLK_EDP_24M>;
> + clock-names = "24m";
> + #phy-cells = <0>;
> + status = "disabled";
> + };
> +
> io_domains: io-domains {
> compatible = "rockchip,rk3288-io-voltage-domain";
> status = "disabled";
> };
> +
> + usbphy: usbphy {
> + compatible = "rockchip,rk3288-usb-phy";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> +
> + usbphy0: usb-phy@320 {
> + #phy-cells = <0>;
> + reg = <0x320>;
> + clocks = <&cru SCLK_OTGPHY0>;
> + clock-names = "phyclk";
> + #clock-cells = <0>;
> + resets = <&cru SRST_USBOTG_PHY>;
> + reset-names = "phy-reset";
> + };
> +
> + usbphy1: usb-phy@334 {
> + #phy-cells = <0>;
> + reg = <0x334>;
> + clocks = <&cru SCLK_OTGPHY1>;
> + clock-names = "phyclk";
> + #clock-cells = <0>;
> + resets = <&cru SRST_USBHOST0_PHY>;
> + reset-names = "phy-reset";
> + };
> +
> + usbphy2: usb-phy@348 {
> + #phy-cells = <0>;
> + reg = <0x348>;
> + clocks = <&cru SCLK_OTGPHY2>;
> + clock-names = "phyclk";
> + #clock-cells = <0>;
> + resets = <&cru SRST_USBHOST1_PHY>;
> + reset-names = "phy-reset";
> + };
> + };
> };
>
> wdt: watchdog@ff800000 {
> @@ -1246,39 +1414,6 @@
> interrupts = <GIC_PPI 9 0xf04>;
> };
>
> - cpuidle: cpuidle {
> - compatible = "rockchip,rk3288-cpuidle";
> - };
> -
> - usbphy: phy {
> - compatible = "rockchip,rk3288-usb-phy";
> - rockchip,grf = <&grf>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> - status = "disabled";
> -
> - usbphy0: usb-phy0 {
> - #phy-cells = <0>;
> - reg = <0x320>;
> - clocks = <&cru SCLK_OTGPHY0>;
> - clock-names = "phyclk";
> - };
> -
> - usbphy1: usb-phy1 {
> - #phy-cells = <0>;
> - reg = <0x334>;
> - clocks = <&cru SCLK_OTGPHY1>;
> - clock-names = "phyclk";
> - };
> -
> - usbphy2: usb-phy2 {
> - #phy-cells = <0>;
> - reg = <0x348>;
> - clocks = <&cru SCLK_OTGPHY2>;
> - clock-names = "phyclk";
> - };
> - };
> -
> pinctrl: pinctrl {
> compatible = "rockchip,rk3288-pinctrl";
> rockchip,grf = <&grf>;
> @@ -1865,62 +2000,4 @@
> };
> };
> };
> -
> - power: power-controller {
> - compatible = "rockchip,rk3288-power-controller";
> - #power-domain-cells = <1>;
> - rockchip,pmu = <&pmu>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - pd_gpu {
> - reg = <RK3288_PD_GPU>;
> - clocks = <&cru ACLK_GPU>;
> - };
> -
> - pd_hevc {
> - reg = <RK3288_PD_HEVC>;
> - clocks = <&cru ACLK_HEVC>,
> - <&cru SCLK_HEVC_CABAC>,
> - <&cru SCLK_HEVC_CORE>,
> - <&cru HCLK_HEVC>;
> - };
> -
> - pd_vio {
> - reg = <RK3288_PD_VIO>;
> - clocks = <&cru ACLK_IEP>,
> - <&cru ACLK_ISP>,
> - <&cru ACLK_RGA>,
> - <&cru ACLK_VIP>,
> - <&cru ACLK_VOP0>,
> - <&cru ACLK_VOP1>,
> - <&cru DCLK_VOP0>,
> - <&cru DCLK_VOP1>,
> - <&cru HCLK_IEP>,
> - <&cru HCLK_ISP>,
> - <&cru HCLK_RGA>,
> - <&cru HCLK_VIP>,
> - <&cru HCLK_VOP0>,
> - <&cru HCLK_VOP1>,
> - <&cru PCLK_EDP_CTRL>,
> - <&cru PCLK_HDMI_CTRL>,
> - <&cru PCLK_LVDS_PHY>,
> - <&cru PCLK_MIPI_CSI>,
> - <&cru PCLK_MIPI_DSI0>,
> - <&cru PCLK_MIPI_DSI1>,
> - <&cru SCLK_EDP_24M>,
> - <&cru SCLK_EDP>,
> - <&cru SCLK_HDMI_CEC>,
> - <&cru SCLK_HDMI_HDCP>,
> - <&cru SCLK_ISP_JPE>,
> - <&cru SCLK_ISP>,
> - <&cru SCLK_RGA>;
> - };
> -
> - pd_video {
> - reg = <RK3288_PD_VIDEO>;
> - clocks = <&cru ACLK_VCODEC>,
> - <&cru HCLK_VCODEC>;
> - };
> - };
> };
> --
> 2.20.1
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v2 3/7] video: rockchip: rk_vop: add rk3288-dp compare string
2023-03-15 18:31 [PATCH v2 1/7] arm: dts: rockchip: rk3288: move io-domains nodes Johan Jonker
2023-03-15 18:33 ` [PATCH v2 2/7] arm: dts: rockchip: rk3288: partial sync grf and pmu nodes Johan Jonker
@ 2023-03-15 18:33 ` Johan Jonker
2023-03-21 3:15 ` Kever Yang
2023-03-15 18:33 ` [PATCH v2 4/7] arm: dts: rockchip: rk3288: partial sync edp node Johan Jonker
` (4 subsequent siblings)
6 siblings, 1 reply; 14+ messages in thread
From: Johan Jonker @ 2023-03-15 18:33 UTC (permalink / raw)
To: kever.yang
Cc: sjg, philipp.tomsich, w.egorov, hl, jernej.skrabec, lukma,
seanga2, agust, u-boot
In the current rk3288.dtsi file the compatible string for
the DisplayPort(DP) node ends with "edp". The string in the
binding ends with "dp" which conflicts with "cdn-dp" as a
search term. Add "rk3288-dp" as compare string to select
vop_id.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org> # chromebook-jerry
---
drivers/video/rockchip/rk_vop.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c
index bc98ab68..e21ac7e3 100644
--- a/drivers/video/rockchip/rk_vop.c
+++ b/drivers/video/rockchip/rk_vop.c
@@ -307,7 +307,8 @@ static int rk_display_init(struct udevice *dev, ulong fbbase, ofnode ep_node)
__func__, dev_read_name(dev));
return -EINVAL;
}
- if (strstr(compat, "edp")) {
+ if (strstr(compat, "edp") ||
+ strstr(compat, "rk3288-dp")) {
vop_id = VOP_MODE_EDP;
} else if (strstr(compat, "mipi")) {
vop_id = VOP_MODE_MIPI;
--
2.20.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v2 3/7] video: rockchip: rk_vop: add rk3288-dp compare string
2023-03-15 18:33 ` [PATCH v2 3/7] video: rockchip: rk_vop: add rk3288-dp compare string Johan Jonker
@ 2023-03-21 3:15 ` Kever Yang
0 siblings, 0 replies; 14+ messages in thread
From: Kever Yang @ 2023-03-21 3:15 UTC (permalink / raw)
To: Johan Jonker
Cc: sjg, philipp.tomsich, w.egorov, hl, jernej.skrabec, lukma,
seanga2, agust, u-boot
On 2023/3/16 02:33, Johan Jonker wrote:
> In the current rk3288.dtsi file the compatible string for
> the DisplayPort(DP) node ends with "edp". The string in the
> binding ends with "dp" which conflicts with "cdn-dp" as a
> search term. Add "rk3288-dp" as compare string to select
> vop_id.
>
> Signed-off-by: Johan Jonker <jbx6244@gmail.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> Tested-by: Simon Glass <sjg@chromium.org> # chromebook-jerry
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> drivers/video/rockchip/rk_vop.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c
> index bc98ab68..e21ac7e3 100644
> --- a/drivers/video/rockchip/rk_vop.c
> +++ b/drivers/video/rockchip/rk_vop.c
> @@ -307,7 +307,8 @@ static int rk_display_init(struct udevice *dev, ulong fbbase, ofnode ep_node)
> __func__, dev_read_name(dev));
> return -EINVAL;
> }
> - if (strstr(compat, "edp")) {
> + if (strstr(compat, "edp") ||
> + strstr(compat, "rk3288-dp")) {
> vop_id = VOP_MODE_EDP;
> } else if (strstr(compat, "mipi")) {
> vop_id = VOP_MODE_MIPI;
> --
> 2.20.1
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v2 4/7] arm: dts: rockchip: rk3288: partial sync edp node
2023-03-15 18:31 [PATCH v2 1/7] arm: dts: rockchip: rk3288: move io-domains nodes Johan Jonker
2023-03-15 18:33 ` [PATCH v2 2/7] arm: dts: rockchip: rk3288: partial sync grf and pmu nodes Johan Jonker
2023-03-15 18:33 ` [PATCH v2 3/7] video: rockchip: rk_vop: add rk3288-dp compare string Johan Jonker
@ 2023-03-15 18:33 ` Johan Jonker
2023-03-21 3:15 ` Kever Yang
2023-03-15 18:34 ` [PATCH v2 5/7] arm: dts: rockchip: rk3288: partial sync vop/lvds/mipi/hdmi nodes Johan Jonker
` (3 subsequent siblings)
6 siblings, 1 reply; 14+ messages in thread
From: Johan Jonker @ 2023-03-15 18:33 UTC (permalink / raw)
To: kever.yang
Cc: sjg, philipp.tomsich, w.egorov, hl, jernej.skrabec, lukma,
seanga2, agust, u-boot
The rk3288 edp node has a phy node in Linux with a clock
property while current U-Boot driver expects this clock
on position index 1. Move U-Boot-specific DT clock properties
to rk3288-u-boot.dtsi and partially sync the edp node.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org> # chromebook-jerry
---
arch/arm/dts/rk3288-u-boot.dtsi | 5 +++++
arch/arm/dts/rk3288.dtsi | 17 +++++++++++------
2 files changed, 16 insertions(+), 6 deletions(-)
diff --git a/arch/arm/dts/rk3288-u-boot.dtsi b/arch/arm/dts/rk3288-u-boot.dtsi
index e411445e..ca229150 100644
--- a/arch/arm/dts/rk3288-u-boot.dtsi
+++ b/arch/arm/dts/rk3288-u-boot.dtsi
@@ -91,6 +91,11 @@
u-boot,dm-pre-reloc;
};
+&edp {
+ clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>;
+ clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
+};
+
&gpio7 {
u-boot,dm-pre-reloc;
};
diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi
index f06d1f5b..9f924466 100644
--- a/arch/arm/dts/rk3288.dtsi
+++ b/arch/arm/dts/rk3288.dtsi
@@ -1177,19 +1177,24 @@
};
edp: dp@ff970000 {
- compatible = "rockchip,rk3288-edp";
+ compatible = "rockchip,rk3288-dp";
reg = <0xff970000 0x4000>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>;
- clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
+ clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
+ clock-names = "dp", "pclk";
+ phys = <&edp_phy>;
+ phy-names = "dp";
+ power-domains = <&power RK3288_PD_VIO>;
resets = <&cru SRST_EDP>;
- reset-names = "edp";
+ reset-names = "dp";
rockchip,grf = <&grf>;
- power-domains = <&power RK3288_PD_VIO>;
status = "disabled";
ports {
- edp_in: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ edp_in: port@0 {
+ reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
edp_in_vopb: endpoint@0 {
--
2.20.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v2 4/7] arm: dts: rockchip: rk3288: partial sync edp node
2023-03-15 18:33 ` [PATCH v2 4/7] arm: dts: rockchip: rk3288: partial sync edp node Johan Jonker
@ 2023-03-21 3:15 ` Kever Yang
0 siblings, 0 replies; 14+ messages in thread
From: Kever Yang @ 2023-03-21 3:15 UTC (permalink / raw)
To: Johan Jonker
Cc: sjg, philipp.tomsich, w.egorov, hl, jernej.skrabec, lukma,
seanga2, agust, u-boot
On 2023/3/16 02:33, Johan Jonker wrote:
> The rk3288 edp node has a phy node in Linux with a clock
> property while current U-Boot driver expects this clock
> on position index 1. Move U-Boot-specific DT clock properties
> to rk3288-u-boot.dtsi and partially sync the edp node.
>
> Signed-off-by: Johan Jonker <jbx6244@gmail.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> Tested-by: Simon Glass <sjg@chromium.org> # chromebook-jerry
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> arch/arm/dts/rk3288-u-boot.dtsi | 5 +++++
> arch/arm/dts/rk3288.dtsi | 17 +++++++++++------
> 2 files changed, 16 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm/dts/rk3288-u-boot.dtsi b/arch/arm/dts/rk3288-u-boot.dtsi
> index e411445e..ca229150 100644
> --- a/arch/arm/dts/rk3288-u-boot.dtsi
> +++ b/arch/arm/dts/rk3288-u-boot.dtsi
> @@ -91,6 +91,11 @@
> u-boot,dm-pre-reloc;
> };
>
> +&edp {
> + clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>;
> + clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
> +};
> +
> &gpio7 {
> u-boot,dm-pre-reloc;
> };
> diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi
> index f06d1f5b..9f924466 100644
> --- a/arch/arm/dts/rk3288.dtsi
> +++ b/arch/arm/dts/rk3288.dtsi
> @@ -1177,19 +1177,24 @@
> };
>
> edp: dp@ff970000 {
> - compatible = "rockchip,rk3288-edp";
> + compatible = "rockchip,rk3288-dp";
> reg = <0xff970000 0x4000>;
> interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>;
> - clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
> + clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
> + clock-names = "dp", "pclk";
> + phys = <&edp_phy>;
> + phy-names = "dp";
> + power-domains = <&power RK3288_PD_VIO>;
> resets = <&cru SRST_EDP>;
> - reset-names = "edp";
> + reset-names = "dp";
> rockchip,grf = <&grf>;
> - power-domains = <&power RK3288_PD_VIO>;
> status = "disabled";
>
> ports {
> - edp_in: port {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + edp_in: port@0 {
> + reg = <0>;
> #address-cells = <1>;
> #size-cells = <0>;
> edp_in_vopb: endpoint@0 {
> --
> 2.20.1
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v2 5/7] arm: dts: rockchip: rk3288: partial sync vop/lvds/mipi/hdmi nodes
2023-03-15 18:31 [PATCH v2 1/7] arm: dts: rockchip: rk3288: move io-domains nodes Johan Jonker
` (2 preceding siblings ...)
2023-03-15 18:33 ` [PATCH v2 4/7] arm: dts: rockchip: rk3288: partial sync edp node Johan Jonker
@ 2023-03-15 18:34 ` Johan Jonker
2023-03-21 3:15 ` Kever Yang
2023-03-15 18:34 ` [PATCH v2 6/7] clk: rockchip: clk_rk3288: add PCLK_RKPWM Johan Jonker
` (2 subsequent siblings)
6 siblings, 1 reply; 14+ messages in thread
From: Johan Jonker @ 2023-03-15 18:34 UTC (permalink / raw)
To: kever.yang
Cc: sjg, philipp.tomsich, w.egorov, hl, jernej.skrabec, lukma,
seanga2, agust, u-boot
In order to better compare the Linux rk3288.dtsi
version 6.3 -rc2 with the U-Boot version partial
sync the vop/lvds/mipi/hdmi nodes.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org> # chromebook-jerry
---
arch/arm/dts/rk3288.dtsi | 48 ++++++++++++++++++++--------------------
1 file changed, 24 insertions(+), 24 deletions(-)
diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi
index 9f924466..f24e9ba5 100644
--- a/arch/arm/dts/rk3288.dtsi
+++ b/arch/arm/dts/rk3288.dtsi
@@ -1021,7 +1021,7 @@
vopb: vop@ff930000 {
compatible = "rockchip,rk3288-vop";
- reg = <0xff930000 0x19c>;
+ reg = <0xff930000 0x19c>, <0xff931000 0x1000>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
@@ -1035,24 +1035,24 @@
#address-cells = <1>;
#size-cells = <0>;
- vopb_out_edp: endpoint@0 {
+ vopb_out_hdmi: endpoint@0 {
reg = <0>;
- remote-endpoint = <&edp_in_vopb>;
+ remote-endpoint = <&hdmi_in_vopb>;
};
- vopb_out_hdmi: endpoint@1 {
+ vopb_out_edp: endpoint@1 {
reg = <1>;
- remote-endpoint = <&hdmi_in_vopb>;
+ remote-endpoint = <&edp_in_vopb>;
};
- vopb_out_lvds: endpoint@2 {
+ vopb_out_mipi: endpoint@2 {
reg = <2>;
- remote-endpoint = <&lvds_in_vopb>;
+ remote-endpoint = <&mipi_in_vopb>;
};
- vopb_out_mipi: endpoint@3 {
+ vopb_out_lvds: endpoint@3 {
reg = <3>;
- remote-endpoint = <&mipi_in_vopb>;
+ remote-endpoint = <&lvds_in_vopb>;
};
};
};
@@ -1070,7 +1070,7 @@
vopl: vop@ff940000 {
compatible = "rockchip,rk3288-vop";
- reg = <0xff940000 0x19c>;
+ reg = <0xff940000 0x19c>, <0xff941000 0x1000>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
@@ -1084,24 +1084,24 @@
#address-cells = <1>;
#size-cells = <0>;
- vopl_out_edp: endpoint@0 {
+ vopl_out_hdmi: endpoint@0 {
reg = <0>;
- remote-endpoint = <&edp_in_vopl>;
+ remote-endpoint = <&hdmi_in_vopl>;
};
- vopl_out_hdmi: endpoint@1 {
+ vopl_out_edp: endpoint@1 {
reg = <1>;
- remote-endpoint = <&hdmi_in_vopl>;
+ remote-endpoint = <&edp_in_vopl>;
};
- vopl_out_lvds: endpoint@2 {
+ vopl_out_mipi: endpoint@2 {
reg = <2>;
- remote-endpoint = <&lvds_in_vopl>;
+ remote-endpoint = <&mipi_in_vopl>;
};
- vopl_out_mipi: endpoint@3 {
+ vopl_out_lvds: endpoint@3 {
reg = <3>;
- remote-endpoint = <&mipi_in_vopl>;
+ remote-endpoint = <&lvds_in_vopl>;
};
};
};
@@ -1118,11 +1118,11 @@
};
mipi_dsi: mipi@ff960000 {
- compatible = "rockchip,rk3288_mipi_dsi";
+ compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
reg = <0xff960000 0x4000>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_MIPI_DSI0>;
- clock-names = "pclk_mipi";
+ clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
+ clock-names = "ref", "pclk";
power-domains = <&power RK3288_PD_VIO>;
rockchip,grf = <&grf>;
status = "disabled";
@@ -1148,7 +1148,7 @@
reg = <0xff96c000 0x4000>;
clocks = <&cru PCLK_LVDS_PHY>;
clock-names = "pclk_lvds";
- pinctrl-names = "default";
+ pinctrl-names = "lcdc";
pinctrl-0 = <&lcdc_ctl>;
power-domains = <&power RK3288_PD_VIO>;
rockchip,grf = <&grf>;
@@ -1216,8 +1216,8 @@
#sound-dai-cells = <0>;
rockchip,grf = <&grf>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
- clock-names = "iahb", "isfr";
+ clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>;
+ clock-names = "iahb", "isfr", "cec";
power-domains = <&power RK3288_PD_VIO>;
status = "disabled";
--
2.20.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v2 5/7] arm: dts: rockchip: rk3288: partial sync vop/lvds/mipi/hdmi nodes
2023-03-15 18:34 ` [PATCH v2 5/7] arm: dts: rockchip: rk3288: partial sync vop/lvds/mipi/hdmi nodes Johan Jonker
@ 2023-03-21 3:15 ` Kever Yang
0 siblings, 0 replies; 14+ messages in thread
From: Kever Yang @ 2023-03-21 3:15 UTC (permalink / raw)
To: Johan Jonker
Cc: sjg, philipp.tomsich, w.egorov, hl, jernej.skrabec, lukma,
seanga2, agust, u-boot
On 2023/3/16 02:34, Johan Jonker wrote:
> In order to better compare the Linux rk3288.dtsi
> version 6.3 -rc2 with the U-Boot version partial
> sync the vop/lvds/mipi/hdmi nodes.
>
> Signed-off-by: Johan Jonker <jbx6244@gmail.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> Tested-by: Simon Glass <sjg@chromium.org> # chromebook-jerry
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> arch/arm/dts/rk3288.dtsi | 48 ++++++++++++++++++++--------------------
> 1 file changed, 24 insertions(+), 24 deletions(-)
>
> diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi
> index 9f924466..f24e9ba5 100644
> --- a/arch/arm/dts/rk3288.dtsi
> +++ b/arch/arm/dts/rk3288.dtsi
> @@ -1021,7 +1021,7 @@
>
> vopb: vop@ff930000 {
> compatible = "rockchip,rk3288-vop";
> - reg = <0xff930000 0x19c>;
> + reg = <0xff930000 0x19c>, <0xff931000 0x1000>;
> interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
> clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
> @@ -1035,24 +1035,24 @@
> #address-cells = <1>;
> #size-cells = <0>;
>
> - vopb_out_edp: endpoint@0 {
> + vopb_out_hdmi: endpoint@0 {
> reg = <0>;
> - remote-endpoint = <&edp_in_vopb>;
> + remote-endpoint = <&hdmi_in_vopb>;
> };
>
> - vopb_out_hdmi: endpoint@1 {
> + vopb_out_edp: endpoint@1 {
> reg = <1>;
> - remote-endpoint = <&hdmi_in_vopb>;
> + remote-endpoint = <&edp_in_vopb>;
> };
>
> - vopb_out_lvds: endpoint@2 {
> + vopb_out_mipi: endpoint@2 {
> reg = <2>;
> - remote-endpoint = <&lvds_in_vopb>;
> + remote-endpoint = <&mipi_in_vopb>;
> };
>
> - vopb_out_mipi: endpoint@3 {
> + vopb_out_lvds: endpoint@3 {
> reg = <3>;
> - remote-endpoint = <&mipi_in_vopb>;
> + remote-endpoint = <&lvds_in_vopb>;
> };
> };
> };
> @@ -1070,7 +1070,7 @@
>
> vopl: vop@ff940000 {
> compatible = "rockchip,rk3288-vop";
> - reg = <0xff940000 0x19c>;
> + reg = <0xff940000 0x19c>, <0xff941000 0x1000>;
> interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
> clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
> @@ -1084,24 +1084,24 @@
> #address-cells = <1>;
> #size-cells = <0>;
>
> - vopl_out_edp: endpoint@0 {
> + vopl_out_hdmi: endpoint@0 {
> reg = <0>;
> - remote-endpoint = <&edp_in_vopl>;
> + remote-endpoint = <&hdmi_in_vopl>;
> };
>
> - vopl_out_hdmi: endpoint@1 {
> + vopl_out_edp: endpoint@1 {
> reg = <1>;
> - remote-endpoint = <&hdmi_in_vopl>;
> + remote-endpoint = <&edp_in_vopl>;
> };
>
> - vopl_out_lvds: endpoint@2 {
> + vopl_out_mipi: endpoint@2 {
> reg = <2>;
> - remote-endpoint = <&lvds_in_vopl>;
> + remote-endpoint = <&mipi_in_vopl>;
> };
>
> - vopl_out_mipi: endpoint@3 {
> + vopl_out_lvds: endpoint@3 {
> reg = <3>;
> - remote-endpoint = <&mipi_in_vopl>;
> + remote-endpoint = <&lvds_in_vopl>;
> };
> };
> };
> @@ -1118,11 +1118,11 @@
> };
>
> mipi_dsi: mipi@ff960000 {
> - compatible = "rockchip,rk3288_mipi_dsi";
> + compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
> reg = <0xff960000 0x4000>;
> interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&cru PCLK_MIPI_DSI0>;
> - clock-names = "pclk_mipi";
> + clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
> + clock-names = "ref", "pclk";
> power-domains = <&power RK3288_PD_VIO>;
> rockchip,grf = <&grf>;
> status = "disabled";
> @@ -1148,7 +1148,7 @@
> reg = <0xff96c000 0x4000>;
> clocks = <&cru PCLK_LVDS_PHY>;
> clock-names = "pclk_lvds";
> - pinctrl-names = "default";
> + pinctrl-names = "lcdc";
> pinctrl-0 = <&lcdc_ctl>;
> power-domains = <&power RK3288_PD_VIO>;
> rockchip,grf = <&grf>;
> @@ -1216,8 +1216,8 @@
> #sound-dai-cells = <0>;
> rockchip,grf = <&grf>;
> interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
> - clock-names = "iahb", "isfr";
> + clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>;
> + clock-names = "iahb", "isfr", "cec";
> power-domains = <&power RK3288_PD_VIO>;
> status = "disabled";
>
> --
> 2.20.1
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v2 6/7] clk: rockchip: clk_rk3288: add PCLK_RKPWM
2023-03-15 18:31 [PATCH v2 1/7] arm: dts: rockchip: rk3288: move io-domains nodes Johan Jonker
` (3 preceding siblings ...)
2023-03-15 18:34 ` [PATCH v2 5/7] arm: dts: rockchip: rk3288: partial sync vop/lvds/mipi/hdmi nodes Johan Jonker
@ 2023-03-15 18:34 ` Johan Jonker
2023-03-21 3:15 ` Kever Yang
2023-03-15 18:34 ` [PATCH v2 7/7] arm: dts: rockchip: rk3288: partial sync pwm nodes Johan Jonker
2023-03-21 3:14 ` [PATCH v2 1/7] arm: dts: rockchip: rk3288: move io-domains nodes Kever Yang
6 siblings, 1 reply; 14+ messages in thread
From: Johan Jonker @ 2023-03-15 18:34 UTC (permalink / raw)
To: kever.yang
Cc: sjg, philipp.tomsich, w.egorov, hl, jernej.skrabec, lukma,
seanga2, agust, u-boot
The rk3288 pwm nodes synced from Linux make use of PCLK_RKPWM
instead of PCLK_PWM. They have the same pclk_cpu parent,
so add PCLK_RKPWM to rk3288_clk_get_rate().
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org> # chromebook-jerry
---
drivers/clk/rockchip/clk_rk3288.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c
index 3b29992c..ef744c06 100644
--- a/drivers/clk/rockchip/clk_rk3288.c
+++ b/drivers/clk/rockchip/clk_rk3288.c
@@ -778,6 +778,7 @@ static ulong rk3288_clk_get_rate(struct clk *clk)
case PCLK_I2C5:
return gclk_rate;
case PCLK_PWM:
+ case PCLK_RKPWM:
return PD_BUS_PCLK_HZ;
case SCLK_SARADC:
new_rate = rockchip_saradc_get_clk(priv->cru);
--
2.20.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v2 6/7] clk: rockchip: clk_rk3288: add PCLK_RKPWM
2023-03-15 18:34 ` [PATCH v2 6/7] clk: rockchip: clk_rk3288: add PCLK_RKPWM Johan Jonker
@ 2023-03-21 3:15 ` Kever Yang
0 siblings, 0 replies; 14+ messages in thread
From: Kever Yang @ 2023-03-21 3:15 UTC (permalink / raw)
To: Johan Jonker
Cc: sjg, philipp.tomsich, w.egorov, hl, jernej.skrabec, lukma,
seanga2, agust, u-boot
On 2023/3/16 02:34, Johan Jonker wrote:
> The rk3288 pwm nodes synced from Linux make use of PCLK_RKPWM
> instead of PCLK_PWM. They have the same pclk_cpu parent,
> so add PCLK_RKPWM to rk3288_clk_get_rate().
>
> Signed-off-by: Johan Jonker <jbx6244@gmail.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> Tested-by: Simon Glass <sjg@chromium.org> # chromebook-jerry
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> drivers/clk/rockchip/clk_rk3288.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c
> index 3b29992c..ef744c06 100644
> --- a/drivers/clk/rockchip/clk_rk3288.c
> +++ b/drivers/clk/rockchip/clk_rk3288.c
> @@ -778,6 +778,7 @@ static ulong rk3288_clk_get_rate(struct clk *clk)
> case PCLK_I2C5:
> return gclk_rate;
> case PCLK_PWM:
> + case PCLK_RKPWM:
> return PD_BUS_PCLK_HZ;
> case SCLK_SARADC:
> new_rate = rockchip_saradc_get_clk(priv->cru);
> --
> 2.20.1
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v2 7/7] arm: dts: rockchip: rk3288: partial sync pwm nodes
2023-03-15 18:31 [PATCH v2 1/7] arm: dts: rockchip: rk3288: move io-domains nodes Johan Jonker
` (4 preceding siblings ...)
2023-03-15 18:34 ` [PATCH v2 6/7] clk: rockchip: clk_rk3288: add PCLK_RKPWM Johan Jonker
@ 2023-03-15 18:34 ` Johan Jonker
2023-03-21 3:15 ` Kever Yang
2023-03-21 3:14 ` [PATCH v2 1/7] arm: dts: rockchip: rk3288: move io-domains nodes Kever Yang
6 siblings, 1 reply; 14+ messages in thread
From: Johan Jonker @ 2023-03-15 18:34 UTC (permalink / raw)
To: kever.yang
Cc: sjg, philipp.tomsich, w.egorov, hl, jernej.skrabec, lukma,
seanga2, agust, u-boot
In order to better compare the Linux rk3288.dtsi
version 6.3 -rc2 with the U-Boot version partial
sync the pwm nodes.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
arch/arm/dts/rk3288.dtsi | 18 +++++-------------
1 file changed, 5 insertions(+), 13 deletions(-)
diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi
index f24e9ba5..dd1d9897 100644
--- a/arch/arm/dts/rk3288.dtsi
+++ b/arch/arm/dts/rk3288.dtsi
@@ -675,9 +675,7 @@
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pwm0_pin>;
- clocks = <&cru PCLK_PWM>;
- clock-names = "pwm";
- rockchip,grf = <&grf>;
+ clocks = <&cru PCLK_RKPWM>;
status = "disabled";
};
@@ -687,9 +685,7 @@
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pwm1_pin>;
- clocks = <&cru PCLK_PWM>;
- clock-names = "pwm";
- rockchip,grf = <&grf>;
+ clocks = <&cru PCLK_RKPWM>;
status = "disabled";
};
@@ -699,21 +695,17 @@
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pwm2_pin>;
- clocks = <&cru PCLK_PWM>;
- clock-names = "pwm";
- rockchip,grf = <&grf>;
+ clocks = <&cru PCLK_RKPWM>;
status = "disabled";
};
pwm3: pwm@ff680030 {
compatible = "rockchip,rk3288-pwm";
reg = <0xff680030 0x10>;
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pwm3_pin>;
- clocks = <&cru PCLK_PWM>;
- clock-names = "pwm";
- rockchip,grf = <&grf>;
+ clocks = <&cru PCLK_RKPWM>;
status = "disabled";
};
--
2.20.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v2 7/7] arm: dts: rockchip: rk3288: partial sync pwm nodes
2023-03-15 18:34 ` [PATCH v2 7/7] arm: dts: rockchip: rk3288: partial sync pwm nodes Johan Jonker
@ 2023-03-21 3:15 ` Kever Yang
0 siblings, 0 replies; 14+ messages in thread
From: Kever Yang @ 2023-03-21 3:15 UTC (permalink / raw)
To: Johan Jonker
Cc: sjg, philipp.tomsich, w.egorov, hl, jernej.skrabec, lukma,
seanga2, agust, u-boot
On 2023/3/16 02:34, Johan Jonker wrote:
> In order to better compare the Linux rk3288.dtsi
> version 6.3 -rc2 with the U-Boot version partial
> sync the pwm nodes.
>
> Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> arch/arm/dts/rk3288.dtsi | 18 +++++-------------
> 1 file changed, 5 insertions(+), 13 deletions(-)
>
> diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi
> index f24e9ba5..dd1d9897 100644
> --- a/arch/arm/dts/rk3288.dtsi
> +++ b/arch/arm/dts/rk3288.dtsi
> @@ -675,9 +675,7 @@
> #pwm-cells = <3>;
> pinctrl-names = "default";
> pinctrl-0 = <&pwm0_pin>;
> - clocks = <&cru PCLK_PWM>;
> - clock-names = "pwm";
> - rockchip,grf = <&grf>;
> + clocks = <&cru PCLK_RKPWM>;
> status = "disabled";
> };
>
> @@ -687,9 +685,7 @@
> #pwm-cells = <3>;
> pinctrl-names = "default";
> pinctrl-0 = <&pwm1_pin>;
> - clocks = <&cru PCLK_PWM>;
> - clock-names = "pwm";
> - rockchip,grf = <&grf>;
> + clocks = <&cru PCLK_RKPWM>;
> status = "disabled";
> };
>
> @@ -699,21 +695,17 @@
> #pwm-cells = <3>;
> pinctrl-names = "default";
> pinctrl-0 = <&pwm2_pin>;
> - clocks = <&cru PCLK_PWM>;
> - clock-names = "pwm";
> - rockchip,grf = <&grf>;
> + clocks = <&cru PCLK_RKPWM>;
> status = "disabled";
> };
>
> pwm3: pwm@ff680030 {
> compatible = "rockchip,rk3288-pwm";
> reg = <0xff680030 0x10>;
> - #pwm-cells = <2>;
> + #pwm-cells = <3>;
> pinctrl-names = "default";
> pinctrl-0 = <&pwm3_pin>;
> - clocks = <&cru PCLK_PWM>;
> - clock-names = "pwm";
> - rockchip,grf = <&grf>;
> + clocks = <&cru PCLK_RKPWM>;
> status = "disabled";
> };
>
> --
> 2.20.1
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v2 1/7] arm: dts: rockchip: rk3288: move io-domains nodes
2023-03-15 18:31 [PATCH v2 1/7] arm: dts: rockchip: rk3288: move io-domains nodes Johan Jonker
` (5 preceding siblings ...)
2023-03-15 18:34 ` [PATCH v2 7/7] arm: dts: rockchip: rk3288: partial sync pwm nodes Johan Jonker
@ 2023-03-21 3:14 ` Kever Yang
6 siblings, 0 replies; 14+ messages in thread
From: Kever Yang @ 2023-03-21 3:14 UTC (permalink / raw)
To: Johan Jonker
Cc: sjg, philipp.tomsich, w.egorov, hl, jernej.skrabec, lukma,
seanga2, agust, u-boot
On 2023/3/16 02:31, Johan Jonker wrote:
> In order to better compare the Linux rk3288.dtsi version
> with the U-Boot version move the io-domains nodes.
>
> Signed-off-by: Johan Jonker <jbx6244@gmail.com>
> Reviewed-by: John Keeping <john@metanate.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> Tested-by: Simon Glass <sjg@chromium.org> # chromebook-jerry
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> arch/arm/dts/rk3288-miqi.dtsi | 27 +++++++++++--------------
> arch/arm/dts/rk3288-phycore-som.dtsi | 30 +++++++++++++---------------
> arch/arm/dts/rk3288-popmetal.dtsi | 30 +++++++++++++---------------
> arch/arm/dts/rk3288-veyron.dtsi | 28 ++++++++++++--------------
> arch/arm/dts/rk3288.dtsi | 5 +++++
> 5 files changed, 58 insertions(+), 62 deletions(-)
>
> diff --git a/arch/arm/dts/rk3288-miqi.dtsi b/arch/arm/dts/rk3288-miqi.dtsi
> index cb80cbf2..00c8613d 100644
> --- a/arch/arm/dts/rk3288-miqi.dtsi
> +++ b/arch/arm/dts/rk3288-miqi.dtsi
> @@ -18,21 +18,6 @@
> clock-output-names = "ext_gmac";
> };
>
> - io_domains: io-domains {
> - compatible = "rockchip,rk3288-io-voltage-domain";
> - rockchip,grf = <&grf>;
> -
> - audio-supply = <&vcca_33>;
> - flash0-supply = <&vcc_flash>;
> - flash1-supply = <&vcc_lan>;
> - gpio30-supply = <&vcc_io>;
> - gpio1830-supply = <&vcc_io>;
> - lcdc-supply = <&vcc_io>;
> - sdcard-supply = <&vccio_sd>;
> - wifi-supply = <&vcc_18>;
> - };
> -
> -
> leds {
> compatible = "gpio-leds";
>
> @@ -277,6 +262,18 @@
> status = "okay";
> };
>
> +&io_domains {
> + audio-supply = <&vcca_33>;
> + flash0-supply = <&vcc_flash>;
> + flash1-supply = <&vcc_lan>;
> + gpio30-supply = <&vcc_io>;
> + gpio1830-supply = <&vcc_io>;
> + lcdc-supply = <&vcc_io>;
> + sdcard-supply = <&vccio_sd>;
> + wifi-supply = <&vcc_18>;
> + status = "okay";
> +};
> +
> &pinctrl {
> pcfg_output_high: pcfg-output-high {
> output-high;
> diff --git a/arch/arm/dts/rk3288-phycore-som.dtsi b/arch/arm/dts/rk3288-phycore-som.dtsi
> index 821525f7..70c00308 100644
> --- a/arch/arm/dts/rk3288-phycore-som.dtsi
> +++ b/arch/arm/dts/rk3288-phycore-som.dtsi
> @@ -71,22 +71,6 @@
> clock-output-names = "ext_gmac";
> };
>
> - io_domains: io_domains {
> - compatible = "rockchip,rk3288-io-voltage-domain";
> -
> - status = "okay";
> - sdcard-supply = <&vdd_io_sd>;
> - flash0-supply = <&vdd_emmc_io>;
> - flash1-supply = <&vdd_misc_1v8>;
> - gpio1830-supply = <&vdd_3v3_io>;
> - gpio30-supply = <&vdd_3v3_io>;
> - bb-supply = <&vdd_3v3_io>;
> - dvp-supply = <&vdd_3v3_io>;
> - lcdc-supply = <&vdd_3v3_io>;
> - wifi-supply = <&vdd_3v3_io>;
> - audio-supply = <&vdd_3v3_io>;
> - };
> -
> leds: user-leds {
> compatible = "gpio-leds";
> pinctrl-names = "default";
> @@ -197,6 +181,20 @@
> ddc-i2c-bus = <&i2c5>;
> };
>
> +&io_domains {
> + audio-supply = <&vdd_3v3_io>;
> + bb-supply = <&vdd_3v3_io>;
> + dvp-supply = <&vdd_3v3_io>;
> + flash0-supply = <&vdd_emmc_io>;
> + flash1-supply = <&vdd_misc_1v8>;
> + gpio1830-supply = <&vdd_3v3_io>;
> + gpio30-supply = <&vdd_3v3_io>;
> + lcdc-supply = <&vdd_3v3_io>;
> + sdcard-supply = <&vdd_io_sd>;
> + wifi-supply = <&vdd_3v3_io>;
> + status = "okay";
> +};
> +
> &i2c0 {
> status = "okay";
> clock-frequency = <400000>;
> diff --git a/arch/arm/dts/rk3288-popmetal.dtsi b/arch/arm/dts/rk3288-popmetal.dtsi
> index 0253933a..d732a706 100644
> --- a/arch/arm/dts/rk3288-popmetal.dtsi
> +++ b/arch/arm/dts/rk3288-popmetal.dtsi
> @@ -71,22 +71,6 @@
> };
> };
>
> - io_domains: io-domains {
> - compatible = "rockchip,rk3288-io-voltage-domain";
> - rockchip,grf = <&grf>;
> -
> - audio-supply = <&vcca_33>;
> - bb-supply = <&vcc_io>;
> - dvp-supply = <&vcc18_dvp>;
> - flash0-supply = <&vcc_flash>;
> - flash1-supply = <&vcc_lan>;
> - gpio30-supply = <&vcc_io>;
> - gpio1830-supply = <&vcc_io>;
> - lcdc-supply = <&vcc_io>;
> - sdcard-supply = <&vccio_sd>;
> - wifi-supply = <&vccio_wl>;
> - };
> -
> ir: ir-receiver {
> compatible = "gpio-ir-receiver";
> gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
> @@ -443,6 +427,20 @@
> status = "okay";
> };
>
> +&io_domains {
> + audio-supply = <&vcca_33>;
> + bb-supply = <&vcc_io>;
> + dvp-supply = <&vcc18_dvp>;
> + flash0-supply = <&vcc_flash>;
> + flash1-supply = <&vcc_lan>;
> + gpio30-supply = <&vcc_io>;
> + gpio1830-supply = <&vcc_io>;
> + lcdc-supply = <&vcc_io>;
> + sdcard-supply = <&vccio_sd>;
> + wifi-supply = <&vccio_wl>;
> + status = "okay";
> +};
> +
> &pinctrl {
> ak8963 {
> comp_int: comp-int {
> diff --git a/arch/arm/dts/rk3288-veyron.dtsi b/arch/arm/dts/rk3288-veyron.dtsi
> index 35db8827..434b0d49 100644
> --- a/arch/arm/dts/rk3288-veyron.dtsi
> +++ b/arch/arm/dts/rk3288-veyron.dtsi
> @@ -198,21 +198,6 @@
> /* Faux input supply. See bt_regulator description. */
> vin-supply = <&bt_regulator>;
> };
> -
> - io-domains {
> - compatible = "rockchip,rk3288-io-voltage-domain";
> - rockchip,grf = <&grf>;
> -
> - audio-supply = <&vcc18_codec>;
> - bb-supply = <&vcc33_io>;
> - dvp-supply = <&vcc_18>;
> - flash0-supply = <&vcc18_flashio>;
> - gpio1830-supply = <&vcc33_io>;
> - gpio30-supply = <&vcc33_io>;
> - lcdc-supply = <&vcc33_lcd>;
> - sdcard-supply = <&vccio_sd>;
> - wifi-supply = <&vcc18_wl>;
> - };
> };
>
> &cpu0 {
> @@ -503,6 +488,19 @@
> clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>, <&cru SCLK_I2S0_OUT>;
> };
>
> +&io_domains {
> + audio-supply = <&vcc18_codec>;
> + bb-supply = <&vcc33_io>;
> + dvp-supply = <&vcc_18>;
> + flash0-supply = <&vcc18_flashio>;
> + gpio1830-supply = <&vcc33_io>;
> + gpio30-supply = <&vcc33_io>;
> + lcdc-supply = <&vcc33_lcd>;
> + sdcard-supply = <&vccio_sd>;
> + wifi-supply = <&vcc18_wl>;
> + status = "okay";
> +};
> +
> &wdt {
> status = "okay";
> };
> diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi
> index 8c394c1e..9cfb86f9 100644
> --- a/arch/arm/dts/rk3288.dtsi
> +++ b/arch/arm/dts/rk3288.dtsi
> @@ -762,6 +762,11 @@
> grf: syscon@ff770000 {
> compatible = "rockchip,rk3288-grf", "syscon";
> reg = <0xff770000 0x1000>;
> +
> + io_domains: io-domains {
> + compatible = "rockchip,rk3288-io-voltage-domain";
> + status = "disabled";
> + };
> };
>
> wdt: watchdog@ff800000 {
> --
> 2.20.1
>
^ permalink raw reply [flat|nested] 14+ messages in thread