[U-Boot] [PATCH 1/3] arm: socfpga: Convert reset manager from struct to defines

Ley Foon Tan
2019-08-20T02:35:03Z

Convert reset manager for Gen5, Arria 10 and Stratix 10 from struct
to defines.
No functional change.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
---
.../mach-socfpga/include/mach/reset_manager.h | 12 +++++
.../include/mach/reset_manager_arria10.h | 41 +++-------------
.../include/mach/reset_manager_gen5.h | 20 +++-----
.../include/mach/reset_manager_s10.h | 33 ++-----------
arch/arm/mach-socfpga/misc_gen5.c | 6 +--
arch/arm/mach-socfpga/reset_manager_arria10.c | 49 +++++++++----------
arch/arm/mach-socfpga/reset_manager_gen5.c | 26 +++++-----
arch/arm/mach-socfpga/reset_manager_s10.c | 35 ++++++-------
drivers/sysreset/sysreset_socfpga.c | 6 +--
9 files changed, 86 insertions(+), 142 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index 6ad037e325..c460e89d22 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -6,6 +6,18 @@
#ifndef _RESET_MANAGER_H_
#define _RESET_MANAGER_H_

+#define RSTMGR_READL(reg) \
+ readl(SOCFPGA_RSTMGR_ADDRESS + (reg))
+
+#define RSTMGR_WRITEL(data, reg) \
+ writel(data, SOCFPGA_RSTMGR_ADDRESS + (reg))
+
+#define RSTMGR_CLRBITS(reg, mask) \
+ clrbits_le32(SOCFPGA_RSTMGR_ADDRESS + (reg), mask)
+
+#define RSTMGR_SETBITS(reg, mask) \
+ setbits_le32(SOCFPGA_RSTMGR_ADDRESS + (reg), mask)
+
void reset_cpu(ulong addr);

void socfpga_per_reset(u32 reset, int set);
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
index 6623ebee65..8b72f41498 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
@@ -14,40 +14,13 @@ int socfpga_reset_deassert_bridges_handoff(void);
void socfpga_reset_deassert_osc1wd0(void);
int socfpga_bridges_reset(void);

-struct socfpga_reset_manager {
- u32 stat;
- u32 ramstat;
- u32 miscstat;
- u32 ctrl;
- u32 hdsken;
- u32 hdskreq;
- u32 hdskack;
- u32 counts;
- u32 mpumodrst;
- u32 per0modrst;
- u32 per1modrst;
- u32 brgmodrst;
- u32 sysmodrst;
- u32 coldmodrst;
- u32 nrstmodrst;
- u32 dbgmodrst;
- u32 mpuwarmmask;
- u32 per0warmmask;
- u32 per1warmmask;
- u32 brgwarmmask;
- u32 syswarmmask;
- u32 nrstwarmmask;
- u32 l3warmmask;
- u32 tststa;
- u32 tstscratch;
- u32 hdsktimeout;
- u32 hmcintr;
- u32 hmcintren;
- u32 hmcintrens;
- u32 hmcintrenr;
- u32 hmcgpout;
- u32 hmcgpin;
-};
+#define RSTMGR_STATUS 0
+#define RSTMGR_CTRL 0xc
+#define RSTMGR_MPUMODRST 0x20
+#define RSTMGR_PER0MODRST 0x24
+#define RSTMGR_PER1MODRST 0x28
+#define RSTMGR_BRGMODRST 0x2c
+#define RSTMGR_SYSMODRST 0x30

/*
* SocFPGA Arria10 reset IDs, bank mapping is as follows:
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h b/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
index f4dcb14623..1b308a2b0e 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
@@ -11,19 +11,13 @@
void socfpga_bridges_set_handoff_regs(bool h2f, bool lwh2f, bool f2h);
void socfpga_bridges_reset(int enable);

-struct socfpga_reset_manager {
- u32 status;
- u32 ctrl;
- u32 counts;
- u32 padding1;
- u32 mpu_mod_reset;
- u32 per_mod_reset;
- u32 per2_mod_reset;
- u32 brg_mod_reset;
- u32 misc_mod_reset;
- u32 padding2[12];
- u32 tstscratch;
-};
+#define RSTMGR_STATUS 0
+#define RSTMGR_CTRL 4
+#define RSTMGR_MPUMODRST 0x10
+#define RSTMGR_PERMODRST 0x14
+#define RSTMGR_PER2MODRST 0x18
+#define RSTMGR_BRGMODRST 0x1c
+#define RSTMGR_MISCMODRST 0x20

/*
* SocFPGA Cyclone V/Arria V reset IDs, bank mapping is as follows:
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
index 452147b017..64519c1d92 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
@@ -15,34 +15,11 @@ void socfpga_bridges_reset(int enable);
void socfpga_per_reset(u32 reset, int set);
void socfpga_per_reset_all(void);

-struct socfpga_reset_manager {
- u32 status;
- u32 mpu_rst_stat;
- u32 misc_stat;
- u32 padding1;
- u32 hdsk_en;
- u32 hdsk_req;
- u32 hdsk_ack;
- u32 hdsk_stall;
- u32 mpumodrst;
- u32 per0modrst;
- u32 per1modrst;
- u32 brgmodrst;
- u32 padding2;
- u32 cold_mod_reset;
- u32 padding3;
- u32 dbg_mod_reset;
- u32 tap_mod_reset;
- u32 padding4;
- u32 padding5;
- u32 brg_warm_mask;
- u32 padding6[3];
- u32 tst_stat;
- u32 padding7;
- u32 hdsk_timeout;
- u32 mpul2flushtimeout;
- u32 dbghdsktimeout;
-};
+#define RSTMGR_STATUS 0
+#define RSTMGR_MPUMODRST 0x20
+#define RSTMGR_PER0MODRST 0x24
+#define RSTMGR_PER1MODRST 0x28
+#define RSTMGR_BRGMODRST 0x2c

#define RSTMGR_MPUMODRST_CORE0 0
#define RSTMGR_PER0MODRST_OCP_MASK 0x0020bf00
diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c
index 31681b799d..353c0e7acc 100644
--- a/arch/arm/mach-socfpga/misc_gen5.c
+++ b/arch/arm/mach-socfpga/misc_gen5.c
@@ -206,8 +206,6 @@ int arch_early_init_r(void)
}

#ifndef CONFIG_SPL_BUILD
-static struct socfpga_reset_manager *reset_manager_base =
- (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
static struct socfpga_sdr_ctrl *sdr_ctrl =
(struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;

@@ -226,12 +224,12 @@ void do_bridge_reset(int enable, unsigned int mask)

writel(iswgrp_handoff[2], &sysmgr_regs->fpgaintfgrp_module);
writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst);
- writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset);
+ RSTMGR_WRITEL(iswgrp_handoff[0], RSTMGR_BRGMODRST);
writel(iswgrp_handoff[1], &nic301_regs->remap);
} else {
writel(0, &sysmgr_regs->fpgaintfgrp_module);
writel(0, &sdr_ctrl->fpgaport_rst);
- writel(0, &reset_manager_base->brg_mod_reset);
+ RSTMGR_WRITEL(0, RSTMGR_BRGMODRST);
writel(1, &nic301_regs->remap);
}
}
diff --git a/arch/arm/mach-socfpga/reset_manager_arria10.c b/arch/arm/mach-socfpga/reset_manager_arria10.c
index 471a3045af..100df81d11 100644
--- a/arch/arm/mach-socfpga/reset_manager_arria10.c
+++ b/arch/arm/mach-socfpga/reset_manager_arria10.c
@@ -15,8 +15,6 @@

DECLARE_GLOBAL_DATA_PTR;

-static const struct socfpga_reset_manager *reset_manager_base =
- (void *)SOCFPGA_RSTMGR_ADDRESS;
static const struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;

@@ -63,15 +61,13 @@ static const struct bridge_cfg bridge_cfg_tbl[] = {
void socfpga_watchdog_disable(void)
{
/* assert reset for watchdog */
- setbits_le32(&reset_manager_base->per1modrst,
- ALT_RSTMGR_PER1MODRST_WD0_SET_MSK);
+ RSTMGR_SETBITS(RSTMGR_PER1MODRST, ALT_RSTMGR_PER1MODRST_WD0_SET_MSK);
}

/* Release NOC ddr scheduler from reset */
void socfpga_reset_deassert_noc_ddr_scheduler(void)
{
- clrbits_le32(&reset_manager_base->brgmodrst,
- ALT_RSTMGR_BRGMODRST_DDRSCH_SET_MSK);
+ RSTMGR_CLRBITS(RSTMGR_BRGMODRST, ALT_RSTMGR_BRGMODRST_DDRSCH_SET_MSK);
}

static int get_bridge_init_val(const void *blob, int compat_id)
@@ -103,7 +99,7 @@ int socfpga_reset_deassert_bridges_handoff(void)
setbits_le32(&sysmgr_regs->noc_idlereq_clr, mask_noc);

/* Release bridges from reset state per handoff value */
- clrbits_le32(&reset_manager_base->brgmodrst, mask_rstmgr);
+ RSTMGR_CLRBITS(RSTMGR_BRGMODRST, mask_rstmgr);

/* Poll until all idleack to 0, timeout at 1000ms */
return wait_for_bit_le32(&sysmgr_regs->noc_idleack, mask_noc,
@@ -113,8 +109,7 @@ int socfpga_reset_deassert_bridges_handoff(void)
/* Release L4 OSC1 Watchdog Timer 0 from reset through reset manager */
void socfpga_reset_deassert_osc1wd0(void)
{
- clrbits_le32(&reset_manager_base->per1modrst,
- ALT_RSTMGR_PER1MODRST_WD0_SET_MSK);
+ RSTMGR_CLRBITS(RSTMGR_PER1MODRST, ALT_RSTMGR_PER1MODRST_WD0_SET_MSK);
}

/*
@@ -122,24 +117,24 @@ void socfpga_reset_deassert_osc1wd0(void)
*/
void socfpga_per_reset(u32 reset, int set)
{
- const u32 *reg;
+ unsigned long reg;
u32 rstmgr_bank = RSTMGR_BANK(reset);

switch (rstmgr_bank) {
case 0:
- reg = &reset_manager_base->mpumodrst;
+ reg = RSTMGR_MPUMODRST;
break;
case 1:
- reg = &reset_manager_base->per0modrst;
+ reg = RSTMGR_PER0MODRST;
break;
case 2:
- reg = &reset_manager_base->per1modrst;
+ reg = RSTMGR_PER1MODRST;
break;
case 3:
- reg = &reset_manager_base->brgmodrst;
+ reg = RSTMGR_BRGMODRST;
break;
case 4:
- reg = &reset_manager_base->sysmodrst;
+ reg = RSTMGR_SYSMODRST;
break;

default:
@@ -147,9 +142,9 @@ void socfpga_per_reset(u32 reset, int set)
}

if (set)
- setbits_le32(reg, 1 << RSTMGR_RESET(reset));
+ RSTMGR_SETBITS(reg, 1 << RSTMGR_RESET(reset));
else
- clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
+ RSTMGR_CLRBITS(reg, 1 << RSTMGR_RESET(reset));
}

/*
@@ -174,11 +169,11 @@ void socfpga_per_reset_all(void)
ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK;

/* disable all components except ECC_OCP, L4 Timer0 and L4 WD0 */
- writel(~l4wd0, &reset_manager_base->per1modrst);
- setbits_le32(&reset_manager_base->per0modrst, ~mask_ecc_ocp);
+ RSTMGR_WRITEL(~l4wd0, RSTMGR_PER1MODRST);
+ RSTMGR_SETBITS(RSTMGR_PER0MODRST, ~mask_ecc_ocp);

/* Finally disable the ECC_OCP */
- setbits_le32(&reset_manager_base->per0modrst, mask_ecc_ocp);
+ RSTMGR_SETBITS(RSTMGR_PER0MODRST, mask_ecc_ocp);
}

int socfpga_bridges_reset(void)
@@ -224,13 +219,13 @@ int socfpga_bridges_reset(void)
return ret;

/* Put all bridges (except NOR DDR scheduler) into reset state */
- setbits_le32(&reset_manager_base->brgmodrst,
- (ALT_RSTMGR_BRGMODRST_H2F_SET_MSK |
- ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK |
- ALT_RSTMGR_BRGMODRST_F2H_SET_MSK |
- ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET_MSK |
- ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET_MSK |
- ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK));
+ RSTMGR_SETBITS(RSTMGR_BRGMODRST,
+ (ALT_RSTMGR_BRGMODRST_H2F_SET_MSK |
+ ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK |
+ ALT_RSTMGR_BRGMODRST_F2H_SET_MSK |
+ ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET_MSK |
+ ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET_MSK |
+ ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK));

/* Disable NOC timeout */
writel(0, &sysmgr_regs->noc_timeout);
diff --git a/arch/arm/mach-socfpga/reset_manager_gen5.c b/arch/arm/mach-socfpga/reset_manager_gen5.c
index 9a32f5abfe..1d85ac8bd4 100644
--- a/arch/arm/mach-socfpga/reset_manager_gen5.c
+++ b/arch/arm/mach-socfpga/reset_manager_gen5.c
@@ -10,32 +10,30 @@
#include <asm/arch/reset_manager.h>
#include <asm/arch/system_manager.h>

-static const struct socfpga_reset_manager *reset_manager_base =
- (void *)SOCFPGA_RSTMGR_ADDRESS;
static const struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;

/* Assert or de-assert SoCFPGA reset manager reset. */
void socfpga_per_reset(u32 reset, int set)
{
- const u32 *reg;
+ unsigned long reg;
u32 rstmgr_bank = RSTMGR_BANK(reset);

switch (rstmgr_bank) {
case 0:
- reg = &reset_manager_base->mpu_mod_reset;
+ reg = RSTMGR_MPUMODRST;
break;
case 1:
- reg = &reset_manager_base->per_mod_reset;
+ reg = RSTMGR_PERMODRST;
break;
case 2:
- reg = &reset_manager_base->per2_mod_reset;
+ reg = RSTMGR_PER2MODRST;
break;
case 3:
- reg = &reset_manager_base->brg_mod_reset;
+ reg = RSTMGR_BRGMODRST;
break;
case 4:
- reg = &reset_manager_base->misc_mod_reset;
+ reg = RSTMGR_MISCMODRST;
break;

default:
@@ -43,9 +41,9 @@ void socfpga_per_reset(u32 reset, int set)
}

if (set)
- setbits_le32(reg, 1 << RSTMGR_RESET(reset));
+ RSTMGR_SETBITS(reg, 1 << RSTMGR_RESET(reset));
else
- clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
+ RSTMGR_CLRBITS(reg, 1 << RSTMGR_RESET(reset));
}

/*
@@ -57,8 +55,8 @@ void socfpga_per_reset_all(void)
{
const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0));

- writel(~l4wd0, &reset_manager_base->per_mod_reset);
- writel(0xffffffff, &reset_manager_base->per2_mod_reset);
+ RSTMGR_WRITEL(~l4wd0, RSTMGR_PERMODRST);
+ RSTMGR_WRITEL(0xffffffff, RSTMGR_PER2MODRST);
}

#define L3REGS_REMAP_LWHPS2FPGA_MASK 0x10
@@ -95,7 +93,7 @@ void socfpga_bridges_reset(int enable)

if (enable) {
/* brdmodrst */
- writel(0x7, &reset_manager_base->brg_mod_reset);
+ RSTMGR_WRITEL(0x7, RSTMGR_BRGMODRST);
writel(L3REGS_REMAP_OCRAM_MASK, SOCFPGA_L3REGS_ADDRESS);
} else {
socfpga_bridges_set_handoff_regs(false, false, false);
@@ -109,7 +107,7 @@ void socfpga_bridges_reset(int enable)
}

/* brdmodrst */
- writel(0, &reset_manager_base->brg_mod_reset);
+ RSTMGR_WRITEL(0, RSTMGR_BRGMODRST);

/* Remap the bridges into memory map */
writel(l3mask, SOCFPGA_L3REGS_ADDRESS);
diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c
index 499a84aff5..78a531f747 100644
--- a/arch/arm/mach-socfpga/reset_manager_s10.c
+++ b/arch/arm/mach-socfpga/reset_manager_s10.c
@@ -12,31 +12,29 @@

DECLARE_GLOBAL_DATA_PTR;

-static const struct socfpga_reset_manager *reset_manager_base =
- (void *)SOCFPGA_RSTMGR_ADDRESS;
static const struct socfpga_system_manager *system_manager_base =
(void *)SOCFPGA_SYSMGR_ADDRESS;

/* Assert or de-assert SoCFPGA reset manager reset. */
void socfpga_per_reset(u32 reset, int set)
{
- const void *reg;
+ unsigned long reg;

if (RSTMGR_BANK(reset) == 0)
- reg = &reset_manager_base->mpumodrst;
+ reg = RSTMGR_MPUMODRST;
else if (RSTMGR_BANK(reset) == 1)
- reg = &reset_manager_base->per0modrst;
+ reg = RSTMGR_PER0MODRST;
else if (RSTMGR_BANK(reset) == 2)
- reg = &reset_manager_base->per1modrst;
+ reg = RSTMGR_PER1MODRST;
else if (RSTMGR_BANK(reset) == 3)
- reg = &reset_manager_base->brgmodrst;
+ reg = RSTMGR_BRGMODRST;
else /* Invalid reset register, do nothing */
return;

if (set)
- setbits_le32(reg, 1 << RSTMGR_RESET(reset));
+ RSTMGR_SETBITS(reg, 1 << RSTMGR_RESET(reset));
else
- clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
+ RSTMGR_CLRBITS(reg, 1 << RSTMGR_RESET(reset));
}

/*
@@ -49,10 +47,10 @@ void socfpga_per_reset_all(void)
const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0));

/* disable all except OCP and l4wd0. OCP disable later */
- writel(~(l4wd0 | RSTMGR_PER0MODRST_OCP_MASK),
- &reset_manager_base->per0modrst);
- writel(~l4wd0, &reset_manager_base->per0modrst);
- writel(0xffffffff, &reset_manager_base->per1modrst);
+ RSTMGR_WRITEL(~(l4wd0 | RSTMGR_PER0MODRST_OCP_MASK),
+ RSTMGR_PER0MODRST);
+ RSTMGR_WRITEL(~l4wd0, RSTMGR_PER0MODRST);
+ RSTMGR_WRITEL(0xffffffff, RSTMGR_PER1MODRST);
}

void socfpga_bridges_reset(int enable)
@@ -62,7 +60,7 @@ void socfpga_bridges_reset(int enable)
setbits_le32(&system_manager_base->noc_idlereq_clr, ~0);

/* Release all bridges from reset state */
- clrbits_le32(&reset_manager_base->brgmodrst, ~0);
+ RSTMGR_CLRBITS(RSTMGR_BRGMODRST, ~0);

/* Poll until all idleack to 0 */
while (readl(&system_manager_base->noc_idleack))
@@ -85,9 +83,9 @@ void socfpga_bridges_reset(int enable)
;

/* Reset all bridges (except NOR DDR scheduler & F2S) */
- setbits_le32(&reset_manager_base->brgmodrst,
- ~(RSTMGR_BRGMODRST_DDRSCH_MASK |
- RSTMGR_BRGMODRST_FPGA2SOC_MASK));
+ RSTMGR_SETBITS(RSTMGR_BRGMODRST,
+ ~(RSTMGR_BRGMODRST_DDRSCH_MASK |
+ RSTMGR_BRGMODRST_FPGA2SOC_MASK));

/* Disable NOC timeout */
writel(0, &system_manager_base->noc_timeout);
@@ -99,6 +97,5 @@ void socfpga_bridges_reset(int enable)
*/
int cpu_has_been_warmreset(void)
{
- return readl(&reset_manager_base->status) &
- RSTMGR_L4WD_MPU_WARMRESET_MASK;
+ return RSTMGR_READL(RSTMGR_STATUS) & RSTMGR_L4WD_MPU_WARMRESET_MASK;
}
diff --git a/drivers/sysreset/sysreset_socfpga.c b/drivers/sysreset/sysreset_socfpga.c
index d6c26a5b23..3390b7bdc2 100644
--- a/drivers/sysreset/sysreset_socfpga.c
+++ b/drivers/sysreset/sysreset_socfpga.c
@@ -12,7 +12,7 @@
#include <asm/arch/reset_manager.h>

struct socfpga_sysreset_data {
- struct socfpga_reset_manager *rstmgr_base;
+ void __iomem *rstmgr_base;
};

static int socfpga_sysreset_request(struct udevice *dev,
@@ -23,11 +23,11 @@ static int socfpga_sysreset_request(struct udevice *dev,
switch (type) {
case SYSRESET_WARM:
writel(BIT(RSTMGR_CTRL_SWWARMRSTREQ_LSB),
- &data->rstmgr_base->ctrl);
+ data->rstmgr_base + RSTMGR_CTRL);
break;
case SYSRESET_COLD:
writel(BIT(RSTMGR_CTRL_SWCOLDRSTREQ_LSB),
- &data->rstmgr_base->ctrl);
+ data->rstmgr_base + RSTMGR_CTRL);
break;
default:
return -EPROTONOSUPPORT;
--
2.19.0