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Fri, 09 Jul 2021 11:03:22 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 6E47010002A; Fri, 9 Jul 2021 11:03:19 +0200 (CEST) Received: from Webmail-eu.st.com (sfhdag2node3.st.com [10.75.127.6]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 5FDB3218C9D; Fri, 9 Jul 2021 11:03:19 +0200 (CEST) Received: from lmecxl0994.lme.st.com (10.75.127.50) by SFHDAG2NODE3.st.com (10.75.127.6) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 9 Jul 2021 11:03:18 +0200 Subject: Re: [PATCH v4 4/5] stm32mp1: spl: Configure TrustZone controller for OP-TEE To: Alexandru Gagniuc , , CC: , References: <20210531174314.1395666-1-mr.nuke.me@gmail.com> <20210531174314.1395666-5-mr.nuke.me@gmail.com> From: Patrick DELAUNAY Message-ID: Date: Fri, 9 Jul 2021 11:03:18 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: <20210531174314.1395666-5-mr.nuke.me@gmail.com> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: 7bit Content-Language: en-US X-Originating-IP: [10.75.127.50] X-ClientProxiedBy: SFHDAG2NODE1.st.com (10.75.127.4) To SFHDAG2NODE3.st.com (10.75.127.6) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-07-09_04:2021-07-09, 2021-07-09 signatures=0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Hi, On 5/31/21 7:43 PM, Alexandru Gagniuc wrote: > OP-TEE is very particular about how the TZC should be configured. > When booting an OP-TEE payload, an incorrect TZC configuration will > result in a panic. > > Most information can be derived from the SPL devicetree. The only > information we don't have is the split between TZDRAM and shared > memory. This has to be hardcoded. The rest of the configuration is > fairly easy, and only requires 3 TZC regions. Configure them. > > Signed-off-by: Alexandru Gagniuc > --- > arch/arm/mach-stm32mp/spl.c | 92 +++++++++++++++++++++++++++++++++++++ > 1 file changed, 92 insertions(+) > Reviewed-by: Patrick Delaunay Thanks Patrick