[U-Boot] [PATCH v3 2/9] sunxi: clk: A80: add MMC clock support

Jagan Teki
2019-01-21T10:31:08Z

From: Andre Przywara <andre.przywara@arm.com>

The A80 handles resets and clock gates for the MMC devices differently,
outside of the CCU IP block. Consequently we have a separate clock
device with a separate binding for that.

Implement that with the respective clock gates and resets to allow the
A80 taking part in the DM_MMC game.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
[jagan: fix a80 mmc clock config compatible]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
drivers/clk/sunxi/clk_a80.c | 28 +++++++++++++++++++++++++++-
1 file changed, 27 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/sunxi/clk_a80.c b/drivers/clk/sunxi/clk_a80.c
index d6dd6a1fa1..efcc7a433d 100644
--- a/drivers/clk/sunxi/clk_a80.c
+++ b/drivers/clk/sunxi/clk_a80.c
@@ -30,19 +30,45 @@ static const struct ccu_reset a80_resets[] = {
[RST_BUS_UART5] = RESET(0x5b4, BIT(21)),
};

+static const struct ccu_clk_gate a80_mmc_gates[] = {
+ [0] = GATE(0x0, BIT(16)),
+ [1] = GATE(0x4, BIT(16)),
+ [2] = GATE(0x8, BIT(16)),
+ [3] = GATE(0xc, BIT(16)),
+};
+
+static const struct ccu_reset a80_mmc_resets[] = {
+ [0] = GATE(0x0, BIT(18)),
+ [1] = GATE(0x4, BIT(18)),
+ [2] = GATE(0x8, BIT(18)),
+ [3] = GATE(0xc, BIT(18)),
+};
+
static const struct ccu_desc a80_ccu_desc = {
.gates = a80_gates,
.resets = a80_resets,
};

+static const struct ccu_desc a80_mmc_clk_desc = {
+ .gates = a80_mmc_gates,
+ .resets = a80_mmc_resets,
+};
+
static int a80_clk_bind(struct udevice *dev)
{
- return sunxi_reset_bind(dev, ARRAY_SIZE(a80_resets));
+ ulong count = ARRAY_SIZE(a80_resets);
+
+ if (device_is_compatible(dev, "allwinner,allwinner,sun9i-a80-mmc"))
+ count = ARRAY_SIZE(a80_mmc_resets);
+
+ return sunxi_reset_bind(dev, count);
}

static const struct udevice_id a80_ccu_ids[] = {
{ .compatible = "allwinner,sun9i-a80-ccu",
.data = (ulong)&a80_ccu_desc },
+ { .compatible = "allwinner,sun9i-a80-mmc-config-clk",
+ .data = (ulong)&a80_mmc_clk_desc },
{ }
};

--
2.18.0.321.gffc6fa0e3