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dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=a-govindraju@ti.com Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 16J6mUZb014722; Mon, 19 Jul 2021 01:48:30 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1626677310; bh=biRr47wn0djIpW2NA6hiOXpyTv4uVb5p6dQzi0J7uEU=; h=Subject:From:To:CC:References:Date:In-Reply-To; b=a26a8/DoHiR4yWzlr7xK5PNvFn92CvDe2t5c/siY21+o8hUhTf3w8qD2g9RvpW8TP HZsjD5t2ZEOvjbKHF+gK4MdmKp42trCcVkn9KOh+UBuqyeqyxwf40C2rVhY/ANe4zr sECwkYxE4LkgMGL78Jk35vFd70aLdMvxWfnfkNKA= Received: from DFLE112.ent.ti.com (dfle112.ent.ti.com [10.64.6.33]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 16J6mUsm095865 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 19 Jul 2021 01:48:30 -0500 Received: from DFLE108.ent.ti.com (10.64.6.29) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Mon, 19 Jul 2021 01:48:30 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Mon, 19 Jul 2021 01:48:30 -0500 Received: from [10.250.235.117] (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 16J6mOIs079627; Mon, 19 Jul 2021 01:48:26 -0500 Subject: Re: [PATCH] mmc: sdhci: Write to HOST_CONTROL2 register for HS400 speed mode From: Aswath Govindraju To: Peng Fan CC: Jaehoon Chung , , Praneeth Bajjuri , Lokesh Vutla , Kishon Vijay Abraham I , Vignesh Raghavendra , Faiz Abbas References: <20210405144428.12159-1-a-govindraju@ti.com> <4e298cce-03d4-ede4-dfe5-5abc8080fad2@ti.com> Message-ID: Date: Mon, 19 Jul 2021 12:18:22 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <4e298cce-03d4-ede4-dfe5-5abc8080fad2@ti.com> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Hi Peng, On 09/06/21 8:56 pm, Aswath Govindraju wrote: > Hi Peng, > > On 10/05/21 7:18 pm, Aswath Govindraju wrote: >> Hi Peng, >> >> On 07/04/21 3:52 am, Jaehoon Chung wrote: >>> On 4/5/21 11:44 PM, Aswath Govindraju wrote: >>>> From: Faiz Abbas >>>> >>>> Enable HS400 speed mode by writing to HOST_CONTROL2 register. >>>> >>>> Signed-off-by: Faiz Abbas >>>> Signed-off-by: Aswath Govindraju >>> >>> Reviewed-by: Jaehoon Chung >>> >> >> Can you please pick this patch if there are no comments. >> > > May I know if this okay to be merged ? > A gentle reminder on this patch. This patch has other dependencies that and are pending merge[1][2]. [1] - https://patchwork.ozlabs.org/project/uboot/list/?series=247000 [2] - https://patchwork.ozlabs.org/project/uboot/list/?series=245579 Thanks, Aswath > Thanks, > Aswath > >> Thanks, >> Aswath >> >>> Best Regards, >>> Jaehoon Chung >>> >>>> --- >>>> drivers/mmc/sdhci.c | 3 +++ >>>> 1 file changed, 3 insertions(+) >>>> >>>> diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c >>>> index d9ab6a0a839e..eea4701d8af5 100644 >>>> --- a/drivers/mmc/sdhci.c >>>> +++ b/drivers/mmc/sdhci.c >>>> @@ -507,6 +507,9 @@ void sdhci_set_uhs_timing(struct sdhci_host *host) >>>> case MMC_HS_200: >>>> reg |= SDHCI_CTRL_UHS_SDR104; >>>> break; >>>> + case MMC_HS_400: >>>> + reg |= SDHCI_CTRL_HS400; >>>> + break; >>>> default: >>>> reg |= SDHCI_CTRL_UHS_SDR12; >>>> } >>>> >>> >> >