* [U-Boot-Users] Low-boot configuration for MPC8272ADS
@ 2005-11-02 3:16 Dmytro Bablinyuk
2005-11-02 5:39 ` [U-Boot-Users] " Dmytro Bablinyuk
2005-11-02 9:46 ` [U-Boot-Users] " Yuli Barcohen
0 siblings, 2 replies; 3+ messages in thread
From: Dmytro Bablinyuk @ 2005-11-02 3:16 UTC (permalink / raw)
To: u-boot
I've seen one thread on this subject
http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/19224
and tried to repeat the same trick.
1. I have updated (latest snapshot) u-boot:
include/configs/MPC8260ADS.h
#define CFG_HRCW_MASTER 0x0e72b605
board/mpc8260ads/config.mk
TEXT_BASE = 0xff800000
2. Using BDI2000 (MPC8272ADS JP9 is configured to take Hard Reset
Configuration source from BCSR - otherwise board keep reseting)
8272>load
8272>unlock 0xff800000 0x40000 32
8272>erase 0xFF800000 BLOCK
8272>prog 0xFF800000 u-boot.bin BIN
3. Change JP9 to take Hard Reset Configuration from FLASH (SW2 Boot
Source is FLASH)
After power cycling BDI and board - the board keep reseting (BDI is
attached to the board). Yes, 0xFFF00100 is not valid breakpoint anymore
- I guess it should be something like 0x00000100.
But I suspect even I got u-boot wrong BDI still should "freeze" the
board instead of reseting. Is anyone got BDI and u-boot working on
MPC8272ADS in low boot mode?
Any help is really appreciated.
Below is output of BDI while reseting and BDI init from config file.
...
*** TARGET: reset detected, restarting target
- BDI asserts HRESET
- Reset JTAG controller passed
- Bypass check: 0x00000001 => 0x00000001
- JTAG exists check passed
- COP status is 0x01
- Check running state passed
- BDI scans COP freeze command
- BDI removes HRESET
- Target PVR is 0x80822014
- Target SVR is 0x00000000
- COP status is 0x05
- Check stopped state passed
- Check LSRL length passed
- BDI sets breakpoint at 0xFFF00100
- BDI resumes program execution
- Waiting for target stop passed
- TARGET: Target PVR is 0x80822014
- TARGET: resetting target passed
- TARGET: processing target startup ....
- TARGET: processing target startup passed
Here is the init core from BDI config:
[INIT]
; init core register
WREG MSR 0x00001002 ;MSR : ME,RI
WM32 0x0F010004 0xFFFFFFC3 ;SYPCR: disable watchdog
WM32 0x0F0101A8 0x04700000 ;IMMR : internal space @ 0x04700000
WM32 0x04710024 0x100C0000 ;BCR : Single PQ2, ..
WM32 0x04710c94 0x00000001 ;RMR : checkstop reset enable
;
; init memory controller
WM32 0x04710104 0xFF800876 ;OR0: Flash 8MB, CS early
negate, 11 w.s., Timing relax
WM32 0x04710100 0xFF801801 ;BR0: Flash @0xFF800000, 32bit,
no parity
WM32 0x0471010C 0xFFFF8010 ;OR1: BCSR 32KB, all types
access, 1 w.s.
WM32 0x04710108 0x04501801 ;BR1: BCSR @0x04500000, 32bit,
no parity
WM32 0x04710124 0xFFFF8866 ;OR4: EEPROM 32KB, all types
access, 6 w.s.
WM32 0x04710120 0xC2000801 ;BR4: EEPROM @0xC2000000, 8bit,
no parity
;
; init SDRAM Init (PPC bus)
WM16 0x04710184 0x2800 ;MPTPR: Divide Bus clock by 41
WM8 0x0471019C 0x13 ;PSRT : Divide MPTPR output by 20
WM32 0x04710114 0xfe002ec0 ;OR2 : 32MB, 2 banks, row start
at A9, 11 rows
WM32 0x04710110 0x00000041 ;BR2 : SDRAM @0x00000000,
64bit, no parity
WM32 0x04710190 0x824b36a3 ;PSDMR: Precharge all banks
WM32 0x04710190 0xaa4b36a3
WM8 0x00000000 0x00 ;Access SDRAM
WM32 0x04710190 0x8a4b36a3 ;PSDMR: CBR Refresh
WM8 0x00000000 0xFF ;Access SDRAM
WM8 0x00000000 0xFF ;Access SDRAM
WM8 0x00000000 0xFF ;Access SDRAM
WM8 0x00000000 0xFF ;Access SDRAM
WM8 0x00000000 0xFF ;Access SDRAM
WM8 0x00000000 0xFF ;Access SDRAM
WM8 0x00000000 0xFF ;Access SDRAM
WM8 0x00000000 0xFF ;Access SDRAM
WM32 0x04710190 0x9a4b36a3 ;PSDMR: Mode Set
WM8 0x00000190 0x00 ;Access SDRAM
WM32 0x04710190 0xc24b36a3 ;PSDMR: enable refresh, normal
operation
^ permalink raw reply [flat|nested] 3+ messages in thread
* [U-Boot-Users] Re: Low-boot configuration for MPC8272ADS
2005-11-02 3:16 [U-Boot-Users] Low-boot configuration for MPC8272ADS Dmytro Bablinyuk
@ 2005-11-02 5:39 ` Dmytro Bablinyuk
2005-11-02 9:46 ` [U-Boot-Users] " Yuli Barcohen
1 sibling, 0 replies; 3+ messages in thread
From: Dmytro Bablinyuk @ 2005-11-02 5:39 UTC (permalink / raw)
To: u-boot
> 1. I have updated (latest snapshot) u-boot:
>
> include/configs/MPC8260ADS.h
>
> #define CFG_HRCW_MASTER 0x0e72b605
>
> board/mpc8260ads/config.mk
>
> TEXT_BASE = 0xff800000
1. I tried 'make MPC8272ADS_lowboot_config' but it keeps resetting with
or without BDI attached (JP9 in position MEMORY, SW2 is FLASH ON).
2. Burn (to burn I need to move JP9 in position BCSR, otherwise it's
just resetting)
8272>load
8272>unlock 0xff800000 0x40000 32
8272>erase 0xFF800000 BLOCK
8272>prog 0xFF800000 u-boot.bin BIN
3. Move JP9 in position MEMORY
4. Power cycle
5. Board keeps resetting with or without BDI.
Can anybody help, please?
Thank you
^ permalink raw reply [flat|nested] 3+ messages in thread
* [U-Boot-Users] Low-boot configuration for MPC8272ADS
2005-11-02 3:16 [U-Boot-Users] Low-boot configuration for MPC8272ADS Dmytro Bablinyuk
2005-11-02 5:39 ` [U-Boot-Users] " Dmytro Bablinyuk
@ 2005-11-02 9:46 ` Yuli Barcohen
1 sibling, 0 replies; 3+ messages in thread
From: Yuli Barcohen @ 2005-11-02 9:46 UTC (permalink / raw)
To: u-boot
>>>>> Dmytro Bablinyuk writes:
Dmytro> I've seen one thread on this subject
Dmytro> http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/19224
Dmytro> and tried to repeat the same trick.
Dmytro> 1. I have updated (latest snapshot) u-boot:
Dmytro> include/configs/MPC8260ADS.h
Dmytro> #define CFG_HRCW_MASTER 0x0e72b605
IMHO this HRCW value is incompatible with MPC8272 (reserved fields are
not cleared, for example). Read the chip's manual to find correct values
(or copy them from BCSR-supplied HRCW).
Dmytro> board/mpc8260ads/config.mk
Dmytro> TEXT_BASE = 0xff800000
This is unnecessary because lowboot_config takes care of TEXT_BASE.
Dmytro> 2. Using BDI2000 (MPC8272ADS JP9 is configured to take Hard
Dmytro> Reset Configuration source from BCSR - otherwise board
Dmytro> keep reseting)
Probably because your BDI configuration file tries to use default IMMR
0x0F000000 while in fact the IMMR is 0xF0000000 due to the HRCW.
Dmytro> load
Dmytro> unlock 0xff800000 0x40000 32
Dmytro> erase 0xFF800000 BLOCK
Dmytro> prog 0xFF800000 u-boot.bin BIN
Dmytro> 3. Change JP9 to take Hard Reset Configuration from FLASH
Dmytro> (SW2 Boot Source is FLASH)
Dmytro> After power cycling BDI and board - the board keep reseting
Dmytro> (BDI is attached to the board).
See above.
Dmytro> Yes, 0xFFF00100 is not valid breakpoint anymore - I guess it
Dmytro> should be something like 0x00000100. But I suspect even I
Dmytro> got u-boot wrong BDI still should "freeze" the board instead
Dmytro> of reseting. Is anyone got BDI and u-boot working on
Dmytro> MPC8272ADS in low boot mode? Any help is really
Dmytro> appreciated. Below is output of BDI while reseting and BDI
Dmytro> init from config file.
[...deleted...]
--
========================================================================
Yuli Barcohen | Phone +972-9-765-1788 | Software Project Leader
yuli at arabellasw.com | Fax +972-9-765-7494 | Arabella Software, Israel
========================================================================
^ permalink raw reply [flat|nested] 3+ messages in thread
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2005-11-02 9:46 ` [U-Boot-Users] " Yuli Barcohen
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