[PATCH v4 12/27] clk: ti: add support for clkctrl clocks

Dario Binacchi
2020-10-19T16:46:43Z

Until now the clkctrl clocks have been enabled/disabled through platform
routines. Thanks to this patch they can be enabled and configured directly
by the probed devices that need to use them.

For DT binding details see Linux doc:
- Documentation/devicetree/bindings/clock/ti-clkctrl.txt

Signed-off-by: Dario Binacchi <dariobin@libero.it>

---

Changes in v4:
- Include device_compat.h header for dev_xxx macros.
- Fix compilation errors on the dev parameter of the dev_xx macros.

Changes in v3:
- Fix access to registers listed by device tree following resync of
am33xx-clock.dtsi with Linux 5.9-rc7.
- Remove doc/device-tree-bindings/clock/ti,clkctrl.txt.
- Add to commit message the references to linux kernel dt binding
documentation.

drivers/clk/Kconfig | 6 ++
drivers/clk/Makefile | 1 +
drivers/clk/clk-ti-ctrl.c | 154 ++++++++++++++++++++++++++++++++++++++
3 files changed, 161 insertions(+)
create mode 100644 drivers/clk/clk-ti-ctrl.c

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 480ffc7d9c..f383e295d3 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -105,6 +105,12 @@ config CLK_TI_AM3_DPLL
This enables the DPLL clock drivers support on AM33XX SoCs. The DPLL
provides all interface clocks and functional clocks to the processor.

+config CLK_TI_CTRL
+ bool "TI OMAP4 clock controller"
+ depends on CLK && OF_CONTROL
+ help
+ This enables the clock controller driver support on TI's SoCs.
+
config CLK_TI_DIVIDER
bool "TI divider clock driver"
depends on CLK && OF_CONTROL && CLK_CCF
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 809672e92e..c98aa27e71 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -49,6 +49,7 @@ obj-$(CONFIG_SANDBOX) += clk_sandbox_test.o
obj-$(CONFIG_SANDBOX_CLK_CCF) += clk_sandbox_ccf.o
obj-$(CONFIG_STM32H7) += clk_stm32h7.o
obj-$(CONFIG_CLK_TI_AM3_DPLL) += clk-ti-am3-dpll.o clk-ti-am3-dpll-x2.o
+obj-$(CONFIG_CLK_TI_CTRL) += clk-ti-ctrl.o
obj-$(CONFIG_CLK_TI_DIVIDER) += clk-ti-divider.o
obj-$(CONFIG_CLK_TI_GATE) += clk-ti-gate.o
obj-$(CONFIG_CLK_TI_MUX) += clk-ti-mux.o
diff --git a/drivers/clk/clk-ti-ctrl.c b/drivers/clk/clk-ti-ctrl.c
new file mode 100644
index 0000000000..74271aaf56
--- /dev/null
+++ b/drivers/clk/clk-ti-ctrl.c
@@ -0,0 +1,154 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * OMAP clock controller support
+ *
+ * Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <clk-uclass.h>
+#include <asm/arch-am33xx/clock.h>
+
+struct clk_ti_ctrl_offs {
+ fdt_addr_t start;
+ fdt_size_t end;
+};
+
+struct clk_ti_ctrl_priv {
+ int offs_num;
+ struct clk_ti_ctrl_offs *offs;
+};
+
+static int clk_ti_ctrl_check_offs(struct clk *clk, fdt_addr_t offs)
+{
+ struct clk_ti_ctrl_priv *priv = dev_get_priv(clk->dev);
+ int i;
+
+ for (i = 0; i < priv->offs_num; i++) {
+ if (offs >= priv->offs[i].start && offs <= priv->offs[i].end)
+ return 0;
+ }
+
+ return -EFAULT;
+}
+
+static int clk_ti_ctrl_disable(struct clk *clk)
+{
+ struct clk_ti_ctrl_priv *priv = dev_get_priv(clk->dev);
+ u32 *clk_modules[2] = { };
+ fdt_addr_t offs;
+ int err;
+
+ offs = priv->offs[0].start + clk->id;
+ err = clk_ti_ctrl_check_offs(clk, offs);
+ if (err) {
+ dev_err(clk->dev, "invalid offset: 0x%lx\n", offs);
+ return err;
+ }
+
+ clk_modules[0] = (u32 *)(offs);
+ dev_dbg(clk->dev, "module address=%p\n", clk_modules[0]);
+ do_disable_clocks(NULL, clk_modules, 1);
+ return 0;
+}
+
+static int clk_ti_ctrl_enable(struct clk *clk)
+{
+ struct clk_ti_ctrl_priv *priv = dev_get_priv(clk->dev);
+ u32 *clk_modules[2] = { };
+ fdt_addr_t offs;
+ int err;
+
+ offs = priv->offs[0].start + clk->id;
+ err = clk_ti_ctrl_check_offs(clk, offs);
+ if (err) {
+ dev_err(clk->dev, "invalid offset: 0x%lx\n", offs);
+ return err;
+ }
+
+ clk_modules[0] = (u32 *)(offs);
+ dev_dbg(clk->dev, "module address=%p\n", clk_modules[0]);
+ do_enable_clocks(NULL, clk_modules, 1);
+ return 0;
+}
+
+static ulong clk_ti_ctrl_get_rate(struct clk *clk)
+{
+ return 0;
+}
+
+static int clk_ti_ctrl_of_xlate(struct clk *clk,
+ struct ofnode_phandle_args *args)
+{
+ if (args->args_count != 2) {
+ dev_err(clk->dev, "invaild args_count: %d\n", args->args_count);
+ return -EINVAL;
+ }
+
+ if (args->args_count)
+ clk->id = args->args[0];
+ else
+ clk->id = 0;
+
+ dev_dbg(clk->dev, "name=%s, id=%ld\n", clk->dev->name, clk->id);
+ return 0;
+}
+
+static int clk_ti_ctrl_ofdata_to_platdata(struct udevice *dev)
+{
+ struct clk_ti_ctrl_priv *priv = dev_get_priv(dev);
+ fdt_size_t fdt_size;
+ int i, size;
+
+ size = dev_read_size(dev, "reg");
+ if (size < 0) {
+ dev_err(dev, "failed to get 'reg' size\n");
+ return size;
+ }
+
+ priv->offs_num = size / 2 / sizeof(u32);
+ dev_dbg(dev, "size=%d, regs_num=%d\n", size, priv->offs_num);
+
+ priv->offs = kmalloc_array(priv->offs_num, sizeof(*priv->offs),
+ GFP_KERNEL);
+ if (!priv->offs)
+ return -ENOMEM;
+
+ for (i = 0; i < priv->offs_num; i++) {
+ priv->offs[i].start =
+ dev_read_addr_size_index(dev, i, &fdt_size);
+ if (priv->offs[i].start == FDT_ADDR_T_NONE) {
+ dev_err(dev, "failed to get offset %d\n", i);
+ return -EINVAL;
+ }
+
+ priv->offs[i].end = priv->offs[i].start + fdt_size;
+ dev_dbg(dev, "start=0x%08lx, end=0x%08lx\n",
+ priv->offs[i].start, priv->offs[i].end);
+ }
+
+ return 0;
+}
+
+static struct clk_ops clk_ti_ctrl_ops = {
+ .of_xlate = clk_ti_ctrl_of_xlate,
+ .enable = clk_ti_ctrl_enable,
+ .disable = clk_ti_ctrl_disable,
+ .get_rate = clk_ti_ctrl_get_rate,
+};
+
+static const struct udevice_id clk_ti_ctrl_ids[] = {
+ {.compatible = "ti,clkctrl"},
+ {},
+};
+
+U_BOOT_DRIVER(clk_ti_ctrl) = {
+ .name = "ti_ctrl_clk",
+ .id = UCLASS_CLK,
+ .of_match = clk_ti_ctrl_ids,
+ .ofdata_to_platdata = clk_ti_ctrl_ofdata_to_platdata,
+ .ops = &clk_ti_ctrl_ops,
+ .priv_auto_alloc_size = sizeof(struct clk_ti_ctrl_priv),
+};
--
2.17.1