From: Sam Edwards <cfsworks@gmail.com>
To: Andre Przywara <andre.przywara@arm.com>
Cc: u-boot@lists.denx.de
Subject: Re: [RFC PATCH 00/17] sunxi: rework pinctrl and add T113s support
Date: Mon, 12 Jun 2023 15:18:17 -0600 [thread overview]
Message-ID: <e68e5c2f-9dbe-aa2b-b8a0-839f31271514@gmail.com> (raw)
In-Reply-To: <20230612012056.65883683@slackpad.lan>
Hey Andre,
On 6/11/23 18:20, Andre Przywara wrote:
> Thanks for the update and the list! Can you confirm where you
> still needed code changes compared to say my github branch plus the
> changes we already discussed? Trying some guesses below, please confirm
> or deny:
Preeeeetttttyyy much everything I've changed locally has been submitted
to the list or discussed in the relevant patchset. Have you updated your
GitHub branch recently (past couple of weeks)? I haven't been watching
it but I can pull it again and see which of my local changes are still
required.
>> I have a build of U-Boot for my target, complete with:
>> - UART3 initialized correctly
>
> this is problematic because of the other pinmux used on your board,
> which cannot easily be encoded alongside the existing UART3 pinmux?
Actually no, my board's UART3 is on PB6/PB7, nice and standard.
>> - DRAM coming up correctly
>> - SPL sets configured boot clock correctly
>
> This should work as per github?
Yep, everything was working satisfactorily once I figured out I needed
to set CONFIG_SYS_CLK_FREQ to get acceptable boot speeds.
>> - SPI-NAND support (SPL and U-Boot proper)
>
> This is with Icenow's series? Any D1 specific changes needed there?
Yes, with Icenowy's series (322733).
I learned that the BROM sets the boot medium code to 0x04 when it's an
SPI-*NAND* (while older chips used 0x03 for "it's either SPI-NOR or
SPI-NAND, good luck figuring out which"). Since `env_get_location`
assumes BOOT_DEVICE_SPI is NOR (and my target needs to load env from UBI
iff booting from NAND), I'm hoping I can convince Icenowy to separate
out the SPI-NAND and SPI-NOR load methods entirely (vs. her current
try-NAND-then-NOR approach) with the aid of some disambiguation logic to
probe for an SPI-NAND on the older chips known to report these as 0x03.
I also needed Maksim's patch series (355747) to support the D1 SPI master.
>> - MMC support (SPL and U-Boot proper)
>> - SPL boot from FEL
>
> again worked already in github?
Yes and yes. I was just confirming they're good; no local work needed
from me here.
>> - USB gadget support
>
> So with the fixed SUNXI_SRAMC_BASE you said it worked? What about the
> USB PHY? That needs at least wiring in the compatible string? If you
> have such a patch, can you please rebase it on top of my v2 USB PHY
> series and post that?
Yes, with corrected SUNXI_SRAMC_BASE -- though I also needed my patches
to make musb-new/sunxi.c use the UDC gadget model in DM (series 358842),
as I don't think there's another way to init the controller at runtime.
I can't say whether the endpoint limit is correct or that mUSB *host*
operation works.
The USB PHY only required that CONFIG_PHY_SUN4I_USB be enabled. The
correct compatible is already wired up. It does look like your PHY
series drops the explicit requirement to set PHY_SUN4I_USB so that's
better than what I was doing (adding a `select` directive under R528).
I can test your series if you want but I doubt it intersects my work
here in any significant way.
>> - Ethernet MAC+PHY support
>
> Anything surprising here? Is that using an already supported external
> PHY?
The only surprise was this was how I noticed that CONFIG_CLK_SUN20I_D1
was not being implicitly enabled. Enabling that was then how I found
that the clock driver wasn't compatible with current upstream (which I
already mentioned).
The PHY is external and already supported, adding it to my DT required
very little work.
>> - I²C support *
>> - GPIO support (LEDs, buttons, misc. board management)
>
> again should work out of the box, minus your board specific
> configuration?
GPIO is completely OotB, yes. I²C is OotB once MVTWSI_CONTROL_CLEAR_IFLG
is set correctly. (The pinctrl requirements for it are a little harder,
more on that below.)
>> - `reset` working (requries CONFIG_SYSRESET unset, WDT key)
>
> Isn't "CONFIG_SYSRESET unset" a hack? I dimly remember we had this for
> some other SoC initially, but later got rid of it?
Unsetting it is required for reset_cpu() to be defined. Your patchset
updates that function (albeit without adding the WDT key, so the current
patch is broken) to support NCAT2 already. U-Boot has no driver for
"allwinner,sun20i-d1-wdt-reset", so this is the only way for `reset` to
work.
> For the WDT key: it seems like Linux got a nice patch to integrate this
> neatly into the driver without quirking this too much, do you have
> something ready for U-Boot as well? Would love to see it on the list
> then ;-)
I just hacked the correct value into the function; nothing really
suitable for the list, sorry.
>> - PSCI, nonsec
>
> ah yeah, owe you some reviews on this one ...
It occurs to me that my work *might* support H6 as well (they both use
CPUX blocks, right?) so perhaps it would be better if I de-RFC'd my
series and instead worked to upstream it chasing H6, for you to come
along later and tack on NCAT2 support with your R528 patchset?
>> - Able to boot Linux ;)
>>
>> * Requires nonzero `MVTWSI_CONTROL_CLEAR_IFLG` for NCAT2, and a patch to
>> the pinctrl driver to configure the proper mux function for my necessary
>> pins.
>
> Are those pinmuxes straight forward to add to the pinctrl driver? Or
> are there conflicts similar to UART3?
The conflict is that I'm on i2c2 + muxval 2. I suspect this one's going
to be a downstream patch to add the necessary line:
{ "i2c2", 2 }, /* PE12-PE13 */
...and since no other assignment for i2c2 uses muxval 2, the only hope
for this to be supported upstream would be for the pinctrl driver to
include the full pin->muxval LUT.
>> I figured I'd share this list as a sort of checklist for your own work,
>> too. The remainder of my efforts now will probably be focused on
>> mainlining this stuff (let me know how else I can be of help), and then
>> I'm afraid I'll have to disappear back downstream to the Turing Pi 2
>> development effort, but maybe our paths will cross again in the kernel
>> lists. :)
>
> Yeah, as you may know, the DT has to go through the kernel list. DT
> patches can be tedious to upstream, there is now much attention to
> every detail. Running checkpatch and dtbs_check should reveal most
> issues beforehand, though.
At this time I have no interest in upstreaming the DT. That might change
in the future, but for now it's very much meant to be out-of-tree.
> Cheers,
> Andre
Likewise,
Sam
next prev parent reply other threads:[~2023-06-12 21:21 UTC|newest]
Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-06 0:45 [RFC PATCH 00/17] sunxi: rework pinctrl and add T113s support Andre Przywara
2022-12-06 0:45 ` [RFC PATCH 01/17] sunxi: remove CONFIG_SATAPWR Andre Przywara
2022-12-14 8:37 ` Samuel Holland
2022-12-14 14:25 ` Andre Przywara
2022-12-14 23:40 ` Samuel Holland
2022-12-06 0:45 ` [RFC PATCH 02/17] sunxi: remove CONFIG_MACPWR Andre Przywara
2022-12-14 9:09 ` Samuel Holland
2022-12-14 14:23 ` Andre Przywara
2022-12-06 0:45 ` [RFC PATCH 03/17] pinctrl: sunxi: remove struct sunxi_gpio Andre Przywara
2022-12-06 0:45 ` [RFC PATCH 04/17] pinctrl: sunxi: add GPIO in/out wrappers Andre Przywara
2022-12-15 5:59 ` Samuel Holland
2022-12-06 0:45 ` [RFC PATCH 05/17] pinctrl: sunxi: move pinctrl code and remove GPIO_EXTRA_HEADER Andre Przywara
2022-12-06 0:45 ` [RFC PATCH 06/17] pinctrl: sunxi: move PIO_BASE into sunxi_gpio.h Andre Przywara
2022-12-06 0:45 ` [RFC PATCH 07/17] pinctrl: sunxi: add new D1 pinctrl support Andre Przywara
2022-12-06 0:45 ` [RFC PATCH 08/17] sunxi: introduce NCAT2 generation model Andre Przywara
2022-12-06 5:38 ` Icenowy Zheng
2023-05-16 2:32 ` Sam Edwards
2023-05-16 21:08 ` Andre Przywara
2023-05-16 23:53 ` Sam Edwards
2023-05-17 0:43 ` Andre Przywara
2023-05-17 8:56 ` Andre Przywara
2023-05-17 14:04 ` Maxim Kiselev
2023-05-25 18:25 ` Maksim Kiselev
2023-05-26 11:05 ` Andre Przywara
2023-06-03 18:03 ` Sam Edwards
2022-12-06 0:45 ` [RFC PATCH 09/17] pinctrl: sunxi: add Allwinner D1 pinctrl description Andre Przywara
2022-12-06 0:45 ` [RFC PATCH 10/17] clk: sunxi: Add support for the D1 CCU Andre Przywara
2023-05-22 3:57 ` Sam Edwards
2023-05-24 0:58 ` Andre Przywara
2023-05-26 0:34 ` Sam Edwards
2023-05-26 10:50 ` Andre Przywara
2023-05-26 19:27 ` Maksim Kiselev
2023-05-26 20:22 ` Sam Edwards
2023-05-26 22:07 ` Andre Przywara
2023-05-27 2:15 ` Sam Edwards
2023-05-30 0:58 ` Sam Edwards
2023-05-31 15:19 ` Andre Przywara
2022-12-06 0:45 ` [RFC PATCH 11/17] sunxi: clock: D1/R528: Enable PLL LDO during PLL1 setup Andre Przywara
2022-12-06 0:45 ` [RFC PATCH 12/17] sunxi: clock: support D1/R528 PLL6 clock Andre Przywara
2022-12-06 0:45 ` [RFC PATCH 13/17] sunxi: add early Allwinner R528/T113 SoC support Andre Przywara
2023-05-16 2:52 ` Sam Edwards
2023-05-16 22:01 ` Andre Przywara
2022-12-06 0:45 ` [RFC PATCH 14/17] sunxi: refactor serial base addresses to avoid asm/arch/cpu.h Andre Przywara
2022-12-06 0:45 ` [RFC PATCH 15/17] riscv: dts: allwinner: Add the D1/D1s SoC devicetree Andre Przywara
2022-12-06 0:45 ` [RFC PATCH 16/17] arm: sunxi: add Allwinner T113s devicetree stub Andre Przywara
2022-12-06 5:55 ` Icenowy Zheng
2023-01-03 17:38 ` Andre Przywara
2023-01-04 5:49 ` Icenowy Zheng
2022-12-06 0:45 ` [RFC PATCH 17/17] sunxi: add preliminary MangoPi MQ-R board support Andre Przywara
2023-06-09 22:16 ` [RFC PATCH 00/17] sunxi: rework pinctrl and add T113s support Sam Edwards
2023-06-12 0:20 ` Andre Przywara
2023-06-12 21:18 ` Sam Edwards [this message]
2023-06-15 0:07 ` Andre Przywara
2023-06-18 19:01 ` Sam Edwards
2023-06-20 12:42 ` Andre Przywara
2023-06-20 22:11 ` Sam Edwards
2023-06-21 10:55 ` Andre Przywara
2023-06-21 20:22 ` Sam Edwards
2023-06-16 15:59 ` Andre Przywara
2023-06-16 16:27 ` Maxim Kiselev
2023-06-16 16:36 ` Andre Przywara
2023-06-17 8:26 ` Maxim Kiselev
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