[U-Boot] [PATCH v3 39/57] ram: rk3399: Update lpddr4 mode_sel based on io settings

Jagan Teki
2019-07-16T11:57:27Z

The mode_sel on lpddr4 value is depending on IO settings
of rd_vref.

Add support for it.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
drivers/ram/rockchip/sdram_rk3399.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 4a2622a440..63763062f9 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -347,7 +347,7 @@ static int phy_io_config(const struct chan_info *chan,
u32 drv_value, odt_value;
u32 speed;

- /* vref setting */
+ /* vref setting & mode setting */
if (params->base.dramtype == LPDDR4) {
struct io_setting *io = lpddr4_get_io_settings(params, mr5);
u32 rd_vref = io->rd_vref * 1000;
@@ -355,15 +355,18 @@ static int phy_io_config(const struct chan_info *chan,
if (rd_vref < 36700) {
/* MODE_LV[2:0] = LPDDR4 (Range 2)*/
vref_mode_dq = 0x7;
+ /* MODE[2:0]= LPDDR4 Range 2(0.4*VDDQ) */
+ mode_sel = 0x5;
vref_value_dq = (rd_vref - 3300) / 521;
} else {
/* MODE_LV[2:0] = LPDDR4 (Range 1)*/
vref_mode_dq = 0x6;
+ /* MODE[2:0]= LPDDR4 Range 1(0.33*VDDQ) */
+ mode_sel = 0x4;
vref_value_dq = (rd_vref - 15300) / 521;
}
vref_mode_ac = 0x6;
vref_value_ac = 0x1f;
- mode_sel = 0x6;
} else if (params->base.dramtype == LPDDR3) {
if (params->base.odt == 1) {
vref_mode_dq = 0x5; /* LPDDR3 ODT */
--
2.18.0.321.gffc6fa0e3