[U-Boot] [PATCH v3 47/57] clk: rockchip: rk3399: Set 50MHz ddr clock

Kever Yang
2019-07-16T13:19:37Z

On 2019/7/16 下午7:57, Jagan Teki wrote:
> Add support for setting 50MHz ddr clock.
>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> Signed-off-by: YouMin Chen <cym@rock-chips.com>

Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>

Thanks,
- Kever
> ---
> drivers/clk/rockchip/clk_rk3399.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
> index 5d1ad94e85..1de21c9f3e 100644
> --- a/drivers/clk/rockchip/clk_rk3399.c
> +++ b/drivers/clk/rockchip/clk_rk3399.c
> @@ -827,6 +827,10 @@ static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru,
>
> /* clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */
> switch (set_rate) {
> + case 50 * MHz:
> + dpll_cfg = (struct pll_div)
> + {.refdiv = 1, .fbdiv = 12, .postdiv1 = 3, .postdiv2 = 2};
> + break;
> case 200 * MHz:
> dpll_cfg = (struct pll_div)
> {.refdiv = 1, .fbdiv = 50, .postdiv1 = 6, .postdiv2 = 1};