[PATCH 0/4] Enable USB 3.1 for Agilex5 SoCFPGA

[PATCH 0/4] Enable USB 3.1 for Agilex5 SoCFPGA

[Naresh Kumar Ravulapalli]

Required configurations for USB 3.1 are enabled for Agilex5
boards. Testing has been successfully carried out on Agilex5
devkits.

Naresh Kumar Ravulapalli (4):
  arch: arm: dts: Enable USB3.1 for Agilex5
  configs: Enable USB DWC3 host drivers for Agilex5
  configs: Increase USB Hub debounce timeout in Agilex5
  arch: arm: socfpga: Configure USB3 System Manager registers

 arch/arm/dts/socfpga_agilex5_socdk.dts        |  5 ++++
 .../include/mach/system_manager_soc64.h       | 12 +++++++++
 arch/arm/mach-socfpga/system_manager_soc64.c  | 26 ++++++++++++++++++-
 configs/socfpga_agilex5_defconfig             |  3 +++
 4 files changed, 45 insertions(+), 1 deletion(-)

-- 
2.35.3

[PATCH 1/4] arch: arm: dts: Enable USB3.1 for Agilex5

[Naresh Kumar Ravulapalli]

USB 3.1 node is enabled for Agilex5.

Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
---
 arch/arm/dts/socfpga_agilex5_socdk.dts | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/dts/socfpga_agilex5_socdk.dts b/arch/arm/dts/socfpga_agilex5_socdk.dts
index 2ab143e38f8..86e6d374948 100644
--- a/arch/arm/dts/socfpga_agilex5_socdk.dts
+++ b/arch/arm/dts/socfpga_agilex5_socdk.dts
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier:     GPL-2.0
 /*
  * Copyright (C) 2024 Intel Corporation <www.intel.com>
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
  */
 #include "socfpga_agilex5.dtsi"
 
@@ -87,6 +88,10 @@
 	disable-over-current;
 };
 
+&usb31 {
+	status = "okay";
+};
+
 &watchdog0 {
 	status = "okay";
 };
-- 
2.35.3

[PATCH 2/4] configs: Enable USB DWC3 host drivers for Agilex5

[Naresh Kumar Ravulapalli]

Required USB DWC3 host driver configurations are enabled
for Agilex5.

Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
---
 configs/socfpga_agilex5_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/configs/socfpga_agilex5_defconfig b/configs/socfpga_agilex5_defconfig
index cc812c7008c..859750f02e7 100644
--- a/configs/socfpga_agilex5_defconfig
+++ b/configs/socfpga_agilex5_defconfig
@@ -98,7 +98,9 @@ CONFIG_TIMER=y
 CONFIG_DESIGNWARE_APB_TIMER=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC2=y
+CONFIG_USB_DWC3=y
 CONFIG_DESIGNWARE_WATCHDOG=y
 CONFIG_WDT=y
 # CONFIG_SPL_USE_TINY_PRINTF is not set
-- 
2.35.3

[PATCH 3/4] configs: Increase USB Hub debounce timeout in Agilex5

[Naresh Kumar Ravulapalli]

Some USB devices need more time to be initialized. Hence,
increasing the default USB Hub debounce timeout value for
devices to be discovered, connected to Agilex5 boards.

Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
---
 configs/socfpga_agilex5_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/socfpga_agilex5_defconfig b/configs/socfpga_agilex5_defconfig
index 859750f02e7..6f7a2cb11a5 100644
--- a/configs/socfpga_agilex5_defconfig
+++ b/configs/socfpga_agilex5_defconfig
@@ -101,6 +101,7 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC2=y
 CONFIG_USB_DWC3=y
+CONFIG_USB_HUB_DEBOUNCE_TIMEOUT=3000
 CONFIG_DESIGNWARE_WATCHDOG=y
 CONFIG_WDT=y
 # CONFIG_SPL_USE_TINY_PRINTF is not set
-- 
2.35.3

[PATCH 4/4] arch: arm: socfpga: Configure USB3 System Manager registers

[Naresh Kumar Ravulapalli]

For successful reset staggering pulse operation, reset pulse
override bit is set. Port overcurrent bit 1, which in reality
reflects PIPE power present signal is set to avoid giving
false information of Vbus status to HPS controller.

Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
---
 .../include/mach/system_manager_soc64.h       | 12 +++++++++
 arch/arm/mach-socfpga/system_manager_soc64.c  | 26 ++++++++++++++++++-
 2 files changed, 37 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
index c2ca0a50e35..8a7d47bee44 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
@@ -33,6 +33,7 @@ void populate_sysmgr_pinmux(void);
 #define SYSMGR_SOC64_ECC_INTMASK_CLR		0x98
 #define SYSMGR_SOC64_ECC_INTMASK_SERR		0x9C
 #define SYSMGR_SOC64_ECC_INTMASK_DERR		0xA0
+#define SYSMGR_SOC64_USB3_MISC_CTRL_REG0	0x1F0
 #define SYSMGR_SOC64_MPFE_CONFIG		0x228
 #define SYSMGR_SOC64_BOOT_SCRATCH_POR0		0x258
 #define SYSMGR_SOC64_BOOT_SCRATCH_POR1		0x25C
@@ -47,6 +48,17 @@ void populate_sysmgr_pinmux(void);
 #define ALT_SYSMGR_SCRATCH_REG_POR_0_DDR_PROGRESS_MASK	BIT(0)
 #define ALT_SYSMGR_SCRATCH_REG_POR_1_REVA_WORKAROUND_USER_MODE_MASK	BIT(0)
 #define ALT_SYSMGR_SCRATCH_REG_POR_1_REVA_WORKAROUND_MASK	BIT(1)
+
+/*
+ * Bits for SYSMGR_SOC64_USB3_MISC_CTRL_REG0
+ * Bits[14:13] Port Overcurrent
+ * Bit[12] Reset Pulse Override
+ */
+#define SYSMGR_SOC64_USB3_MISC_CTRL_REG0_PORT_OVR_CURR	GENMASK(14, 13)
+#define SYSMGR_SOC64_USB3_MISC_CTRL_REG0_RESET_PUL_OVR	BIT(12)
+#define SET_USB3_MISC_CTRL_REG0_PORT_RESET_PUL_OVR	1
+// BIT 1 actually reflects PIPE power present signal
+#define SET_USB3_MISC_CTRL_REG0_PORT_OVR_CURR_BIT_1	2
 #else
 #define SYSMGR_SOC64_NAND_AXUSER		0x5c
 #define SYSMGR_SOC64_DMA_L3MASTER		0x74
diff --git a/arch/arm/mach-socfpga/system_manager_soc64.c b/arch/arm/mach-socfpga/system_manager_soc64.c
index 4b42158be9d..88d538cdcda 100644
--- a/arch/arm/mach-socfpga/system_manager_soc64.c
+++ b/arch/arm/mach-socfpga/system_manager_soc64.c
@@ -1,16 +1,36 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
  * Copyright (C) 2016-2021 Intel Corporation <www.intel.com>
- *
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
  */
 
 #include <asm/arch/handoff_soc64.h>
 #include <asm/arch/system_manager.h>
 #include <asm/global_data.h>
 #include <asm/io.h>
+#include <linux/bitfield.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+/*
+ * Setting RESET_PULSE_OVERRIDE bit for successful reset staggering pulse
+ * generation and setting PORT_OVERCURRENT bit so that until we turn on the
+ * Vbus, it doesn't give false information about Vbus to the HPS controller.
+ */
+static void sysmgr_config_usb3(void)
+{
+	u32 reg_val = 0;
+
+	reg_val = readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_USB3_MISC_CTRL_REG0);
+	reg_val |= FIELD_PREP(SYSMGR_SOC64_USB3_MISC_CTRL_REG0_RESET_PUL_OVR,
+				SET_USB3_MISC_CTRL_REG0_PORT_RESET_PUL_OVR);
+	reg_val |= FIELD_PREP(SYSMGR_SOC64_USB3_MISC_CTRL_REG0_PORT_OVR_CURR,
+				SET_USB3_MISC_CTRL_REG0_PORT_OVR_CURR_BIT_1);
+	writel(reg_val, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_USB3_MISC_CTRL_REG0);
+}
+#endif
+
 /*
  * Configure all the pin muxes
  */
@@ -18,6 +38,10 @@ void sysmgr_pinmux_init(void)
 {
 	populate_sysmgr_pinmux();
 	populate_sysmgr_fpgaintf_module();
+
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+	sysmgr_config_usb3();
+#endif
 }
 
 /*
-- 
2.35.3

RE: [PATCH 4/4] arch: arm: socfpga: Configure USB3 System Manager registers

[Chee, Tien Fong]

Hi,

> -----Original Message-----
> From: Ravulapalli, Naresh Kumar <naresh.kumar.ravulapalli@altera.com>
> Sent: Friday, August 8, 2025 6:04 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut <marex@denx.de>; Simon Goldschmidt
> <simon.k.r.goldschmidt@gmail.com>; Chee, Tien Fong
> <tien.fong.chee@altera.com>; Tom Rini <trini@konsulko.com>; Ravulapalli,
> Naresh Kumar <naresh.kumar.ravulapalli@altera.com>
> Subject: [PATCH 4/4] arch: arm: socfpga: Configure USB3 System Manager
> registers
> 
> For successful reset staggering pulse operation, reset pulse override bit is set.
> Port overcurrent bit 1, which in reality reflects PIPE power present signal is
> set to avoid giving false information of Vbus status to HPS controller.
> 
> Signed-off-by: Naresh Kumar Ravulapalli
> <nareshkumar.ravulapalli@altera.com>
> ---
>  .../include/mach/system_manager_soc64.h       | 12 +++++++++
>  arch/arm/mach-socfpga/system_manager_soc64.c  | 26
> ++++++++++++++++++-
>  2 files changed, 37 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
> b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
> index c2ca0a50e35..8a7d47bee44 100644
> --- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
> +++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
> @@ -33,6 +33,7 @@ void populate_sysmgr_pinmux(void);
>  #define SYSMGR_SOC64_ECC_INTMASK_CLR		0x98
>  #define SYSMGR_SOC64_ECC_INTMASK_SERR		0x9C
>  #define SYSMGR_SOC64_ECC_INTMASK_DERR		0xA0
> +#define SYSMGR_SOC64_USB3_MISC_CTRL_REG0	0x1F0
>  #define SYSMGR_SOC64_MPFE_CONFIG		0x228
>  #define SYSMGR_SOC64_BOOT_SCRATCH_POR0		0x258
>  #define SYSMGR_SOC64_BOOT_SCRATCH_POR1		0x25C
> @@ -47,6 +48,17 @@ void populate_sysmgr_pinmux(void);
>  #define ALT_SYSMGR_SCRATCH_REG_POR_0_DDR_PROGRESS_MASK
> 	BIT(0)
>  #define
> ALT_SYSMGR_SCRATCH_REG_POR_1_REVA_WORKAROUND_USER_MODE_
> MASK	BIT(0)
>  #define
> ALT_SYSMGR_SCRATCH_REG_POR_1_REVA_WORKAROUND_MASK	BIT(1)
> +
> +/*
> + * Bits for SYSMGR_SOC64_USB3_MISC_CTRL_REG0
> + * Bits[14:13] Port Overcurrent
> + * Bit[12] Reset Pulse Override
> + */
> +#define SYSMGR_SOC64_USB3_MISC_CTRL_REG0_PORT_OVR_CURR
> 	GENMASK(14, 13)
> +#define SYSMGR_SOC64_USB3_MISC_CTRL_REG0_RESET_PUL_OVR	BIT(12)
> +#define SET_USB3_MISC_CTRL_REG0_PORT_RESET_PUL_OVR	1
> +// BIT 1 actually reflects PIPE power present signal

Using /* ... */

[...]

Best regards,
Tien Fong

Re: [PATCH 4/4] arch: arm: socfpga: Configure USB3 System Manager registers

[Ravulapalli, Naresh Kumar]

Hi

On 25-Aug-25 8:36 AM, Chee, Tien Fong wrote:
> Hi,
> 
>> -----Original Message-----
>> From: Ravulapalli, Naresh Kumar <naresh.kumar.ravulapalli@altera.com>
>> Sent: Friday, August 8, 2025 6:04 PM
>> To: u-boot@lists.denx.de
>> Cc: Marek Vasut <marex@denx.de>; Simon Goldschmidt
>> <simon.k.r.goldschmidt@gmail.com>; Chee, Tien Fong
>> <tien.fong.chee@altera.com>; Tom Rini <trini@konsulko.com>; Ravulapalli,
>> Naresh Kumar <naresh.kumar.ravulapalli@altera.com>
>> Subject: [PATCH 4/4] arch: arm: socfpga: Configure USB3 System Manager
>> registers
>>
>> For successful reset staggering pulse operation, reset pulse override bit is set.
>> Port overcurrent bit 1, which in reality reflects PIPE power present signal is
>> set to avoid giving false information of Vbus status to HPS controller.
>>
>> Signed-off-by: Naresh Kumar Ravulapalli
>> <nareshkumar.ravulapalli@altera.com>
>> ---
>>   .../include/mach/system_manager_soc64.h       | 12 +++++++++
>>   arch/arm/mach-socfpga/system_manager_soc64.c  | 26
>> ++++++++++++++++++-
>>   2 files changed, 37 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
>> b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
>> index c2ca0a50e35..8a7d47bee44 100644
>> --- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
>> +++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
>> @@ -33,6 +33,7 @@ void populate_sysmgr_pinmux(void);
>>   #define SYSMGR_SOC64_ECC_INTMASK_CLR		0x98
>>   #define SYSMGR_SOC64_ECC_INTMASK_SERR		0x9C
>>   #define SYSMGR_SOC64_ECC_INTMASK_DERR		0xA0
>> +#define SYSMGR_SOC64_USB3_MISC_CTRL_REG0	0x1F0
>>   #define SYSMGR_SOC64_MPFE_CONFIG		0x228
>>   #define SYSMGR_SOC64_BOOT_SCRATCH_POR0		0x258
>>   #define SYSMGR_SOC64_BOOT_SCRATCH_POR1		0x25C
>> @@ -47,6 +48,17 @@ void populate_sysmgr_pinmux(void);
>>   #define ALT_SYSMGR_SCRATCH_REG_POR_0_DDR_PROGRESS_MASK
>> 	BIT(0)
>>   #define
>> ALT_SYSMGR_SCRATCH_REG_POR_1_REVA_WORKAROUND_USER_MODE_
>> MASK	BIT(0)
>>   #define
>> ALT_SYSMGR_SCRATCH_REG_POR_1_REVA_WORKAROUND_MASK	BIT(1)
>> +
>> +/*
>> + * Bits for SYSMGR_SOC64_USB3_MISC_CTRL_REG0
>> + * Bits[14:13] Port Overcurrent
>> + * Bit[12] Reset Pulse Override
>> + */
>> +#define SYSMGR_SOC64_USB3_MISC_CTRL_REG0_PORT_OVR_CURR
>> 	GENMASK(14, 13)
>> +#define SYSMGR_SOC64_USB3_MISC_CTRL_REG0_RESET_PUL_OVR	BIT(12)
>> +#define SET_USB3_MISC_CTRL_REG0_PORT_RESET_PUL_OVR	1
>> +// BIT 1 actually reflects PIPE power present signal
> 
> Using /* ... */
> 

Noted, will make the change.

Kind Regards
Naresh

RE: [PATCH 1/4] arch: arm: dts: Enable USB3.1 for Agilex5

[Chee, Tien Fong]

> -----Original Message-----
> From: Ravulapalli, Naresh Kumar <naresh.kumar.ravulapalli@altera.com>
> Sent: Friday, August 8, 2025 6:04 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut <marex@denx.de>; Simon Goldschmidt
> <simon.k.r.goldschmidt@gmail.com>; Chee, Tien Fong
> <tien.fong.chee@altera.com>; Tom Rini <trini@konsulko.com>; Ravulapalli,
> Naresh Kumar <naresh.kumar.ravulapalli@altera.com>
> Subject: [PATCH 1/4] arch: arm: dts: Enable USB3.1 for Agilex5
> 
> USB 3.1 node is enabled for Agilex5.
> 
> Signed-off-by: Naresh Kumar Ravulapalli
> <nareshkumar.ravulapalli@altera.com>
> ---
>  arch/arm/dts/socfpga_agilex5_socdk.dts | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/arch/arm/dts/socfpga_agilex5_socdk.dts
> b/arch/arm/dts/socfpga_agilex5_socdk.dts
> index 2ab143e38f8..86e6d374948 100644
> --- a/arch/arm/dts/socfpga_agilex5_socdk.dts
> +++ b/arch/arm/dts/socfpga_agilex5_socdk.dts
> @@ -1,6 +1,7 @@
>  // SPDX-License-Identifier:     GPL-2.0
>  /*
>   * Copyright (C) 2024 Intel Corporation <www.intel.com>
> + * Copyright (C) 2025 Altera Corporation <www.altera.com>
>   */
>  #include "socfpga_agilex5.dtsi"
> 
> @@ -87,6 +88,10 @@
>  	disable-over-current;
>  };
> 
> +&usb31 {
> +	status = "okay";
> +};
> +
>  &watchdog0 {
>  	status = "okay";
>  };
> --
> 2.35.3

Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>

Best regards,
Tien Fong

RE: [PATCH 2/4] configs: Enable USB DWC3 host drivers for Agilex5

[Chee, Tien Fong]

> -----Original Message-----
> From: Ravulapalli, Naresh Kumar <naresh.kumar.ravulapalli@altera.com>
> Sent: Friday, August 8, 2025 6:04 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut <marex@denx.de>; Simon Goldschmidt
> <simon.k.r.goldschmidt@gmail.com>; Chee, Tien Fong
> <tien.fong.chee@altera.com>; Tom Rini <trini@konsulko.com>; Ravulapalli,
> Naresh Kumar <naresh.kumar.ravulapalli@altera.com>
> Subject: [PATCH 2/4] configs: Enable USB DWC3 host drivers for Agilex5
> 
> Required USB DWC3 host driver configurations are enabled for Agilex5.
> 
> Signed-off-by: Naresh Kumar Ravulapalli
> <nareshkumar.ravulapalli@altera.com>
> ---
>  configs/socfpga_agilex5_defconfig | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/configs/socfpga_agilex5_defconfig
> b/configs/socfpga_agilex5_defconfig
> index cc812c7008c..859750f02e7 100644
> --- a/configs/socfpga_agilex5_defconfig
> +++ b/configs/socfpga_agilex5_defconfig
> @@ -98,7 +98,9 @@ CONFIG_TIMER=y
>  CONFIG_DESIGNWARE_APB_TIMER=y
>  CONFIG_USB=y
>  CONFIG_USB_XHCI_HCD=y
> +CONFIG_USB_XHCI_DWC3=y
>  CONFIG_USB_DWC2=y
> +CONFIG_USB_DWC3=y
>  CONFIG_DESIGNWARE_WATCHDOG=y
>  CONFIG_WDT=y
>  # CONFIG_SPL_USE_TINY_PRINTF is not set
> --
> 2.35.3

Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>

Best regards,
Tien Fong

RE: [PATCH 3/4] configs: Increase USB Hub debounce timeout in Agilex5

[Chee, Tien Fong]

> -----Original Message-----
> From: Ravulapalli, Naresh Kumar <naresh.kumar.ravulapalli@altera.com>
> Sent: Friday, August 8, 2025 6:04 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut <marex@denx.de>; Simon Goldschmidt
> <simon.k.r.goldschmidt@gmail.com>; Chee, Tien Fong
> <tien.fong.chee@altera.com>; Tom Rini <trini@konsulko.com>; Ravulapalli,
> Naresh Kumar <naresh.kumar.ravulapalli@altera.com>
> Subject: [PATCH 3/4] configs: Increase USB Hub debounce timeout in Agilex5
> 
> Some USB devices need more time to be initialized. Hence, increasing the
> default USB Hub debounce timeout value for devices to be discovered,
> connected to Agilex5 boards.
> 
> Signed-off-by: Naresh Kumar Ravulapalli
> <nareshkumar.ravulapalli@altera.com>
> ---
>  configs/socfpga_agilex5_defconfig | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/configs/socfpga_agilex5_defconfig
> b/configs/socfpga_agilex5_defconfig
> index 859750f02e7..6f7a2cb11a5 100644
> --- a/configs/socfpga_agilex5_defconfig
> +++ b/configs/socfpga_agilex5_defconfig
> @@ -101,6 +101,7 @@ CONFIG_USB_XHCI_HCD=y
> CONFIG_USB_XHCI_DWC3=y  CONFIG_USB_DWC2=y
> CONFIG_USB_DWC3=y
> +CONFIG_USB_HUB_DEBOUNCE_TIMEOUT=3000
>  CONFIG_DESIGNWARE_WATCHDOG=y
>  CONFIG_WDT=y
>  # CONFIG_SPL_USE_TINY_PRINTF is not set
> --
> 2.35.3

Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>

Best regards,
Tien Fong

RE: [PATCH 3/4] configs: Increase USB Hub debounce timeout in Agilex5

[Chee, Tien Fong]

> -----Original Message-----
> From: Ravulapalli, Naresh Kumar <naresh.kumar.ravulapalli@altera.com>
> Sent: Friday, August 8, 2025 6:04 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut <marex@denx.de>; Simon Goldschmidt
> <simon.k.r.goldschmidt@gmail.com>; Chee, Tien Fong
> <tien.fong.chee@altera.com>; Tom Rini <trini@konsulko.com>; Ravulapalli,
> Naresh Kumar <naresh.kumar.ravulapalli@altera.com>
> Subject: [PATCH 3/4] configs: Increase USB Hub debounce timeout in Agilex5
> 
> Some USB devices need more time to be initialized. Hence, increasing the
> default USB Hub debounce timeout value for devices to be discovered,
> connected to Agilex5 boards.
> 
> Signed-off-by: Naresh Kumar Ravulapalli
> <nareshkumar.ravulapalli@altera.com>
> ---
>  configs/socfpga_agilex5_defconfig | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/configs/socfpga_agilex5_defconfig
> b/configs/socfpga_agilex5_defconfig
> index 859750f02e7..6f7a2cb11a5 100644
> --- a/configs/socfpga_agilex5_defconfig
> +++ b/configs/socfpga_agilex5_defconfig
> @@ -101,6 +101,7 @@ CONFIG_USB_XHCI_HCD=y
> CONFIG_USB_XHCI_DWC3=y  CONFIG_USB_DWC2=y
> CONFIG_USB_DWC3=y
> +CONFIG_USB_HUB_DEBOUNCE_TIMEOUT=3000
>  CONFIG_DESIGNWARE_WATCHDOG=y
>  CONFIG_WDT=y
>  # CONFIG_SPL_USE_TINY_PRINTF is not set
> --
> 2.35.3

Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>

Best regards,
Tien Fong

Re: [PATCH 3/4] configs: Increase USB Hub debounce timeout in Agilex5

[Marek Vasut]

On 8/8/25 12:04 PM, Naresh Kumar Ravulapalli wrote:
> Some USB devices need more time to be initialized. Hence,
> increasing the default USB Hub debounce timeout value for
> devices to be discovered, connected to Agilex5 boards.
Is this really hub debounce timeout or usb_pgood_delay ?

Which devices are those, include that in the commit message.

Re: [PATCH 3/4] configs: Increase USB Hub debounce timeout in Agilex5

[Ravulapalli, Naresh Kumar]

Hi Marek

On 29-Aug-25 2:11 PM, Marek Vasut wrote:
> 
> On 8/8/25 12:04 PM, Naresh Kumar Ravulapalli wrote:
>> Some USB devices need more time to be initialized. Hence,
>> increasing the default USB Hub debounce timeout value for
>> devices to be discovered, connected to Agilex5 boards.
> Is this really hub debounce timeout or usb_pgood_delay ?
> 
> Which devices are those, include that in the commit message.

Yes, timeout is related to USB connect/disconnect signal bounces not 
about bus stability during init.

Issue was mainly observed with legacy flash drives. Maybe I will change 
commit text from "Some USB devices need more time to be initialized..." 
to "Some old USB flash drives need more time to be initialized during 
connect or disconnect events ..."?

Note that I am not modifying the default Kconfig value in general; 
change is only made for an SoCFPGA devkit we tested.

Kind Regards
Naresh

Re: [PATCH 3/4] configs: Increase USB Hub debounce timeout in Agilex5

[Marek Vasut]

On 8/29/25 6:19 PM, Ravulapalli, Naresh Kumar wrote:
> Hi Marek
> 
> On 29-Aug-25 2:11 PM, Marek Vasut wrote:
>>
>> On 8/8/25 12:04 PM, Naresh Kumar Ravulapalli wrote:
>>> Some USB devices need more time to be initialized. Hence,
>>> increasing the default USB Hub debounce timeout value for
>>> devices to be discovered, connected to Agilex5 boards.
>> Is this really hub debounce timeout or usb_pgood_delay ?
>>
>> Which devices are those, include that in the commit message.
> 
> Yes, timeout is related to USB connect/disconnect signal bounces not 
> about bus stability during init.
> 
> Issue was mainly observed with legacy flash drives. Maybe I will change 
> commit text from "Some USB devices need more time to be initialized..." 
> to "Some old USB flash drives need more time to be initialized during 
> connect or disconnect events ..."?
> 
> Note that I am not modifying the default Kconfig value in general; 
> change is only made for an SoCFPGA devkit we tested.
Does this same issue go away if you set usb_pgood_delay to 2000 or 
higher too ?

Re: [PATCH 3/4] configs: Increase USB Hub debounce timeout in Agilex5

[Ravulapalli, Naresh Kumar]

On 30-Aug-25 5:30 AM, Marek Vasut wrote:
> 
> On 8/29/25 6:19 PM, Ravulapalli, Naresh Kumar wrote:
>> Hi Marek
>>
>> On 29-Aug-25 2:11 PM, Marek Vasut wrote:
>>>
>>> On 8/8/25 12:04 PM, Naresh Kumar Ravulapalli wrote:
>>>> Some USB devices need more time to be initialized. Hence,
>>>> increasing the default USB Hub debounce timeout value for
>>>> devices to be discovered, connected to Agilex5 boards.
>>> Is this really hub debounce timeout or usb_pgood_delay ?
>>>
>>> Which devices are those, include that in the commit message.
>>
>> Yes, timeout is related to USB connect/disconnect signal bounces not
>> about bus stability during init.
>>
>> Issue was mainly observed with legacy flash drives. Maybe I will change
>> commit text from "Some USB devices need more time to be initialized..."
>> to "Some old USB flash drives need more time to be initialized during
>> connect or disconnect events ..."?
>>
>> Note that I am not modifying the default Kconfig value in general;
>> change is only made for an SoCFPGA devkit we tested.
> Does this same issue go away if you set usb_pgood_delay to 2000 or
> higher too ?

No, changing USB HUB debounce timeout is working for us.

Re: [PATCH 3/4] configs: Increase USB Hub debounce timeout in Agilex5

[Marek Vasut]

On 9/2/25 9:52 AM, Ravulapalli, Naresh Kumar wrote:
> 
> 
> On 30-Aug-25 5:30 AM, Marek Vasut wrote:
>>
>> On 8/29/25 6:19 PM, Ravulapalli, Naresh Kumar wrote:
>>> Hi Marek
>>>
>>> On 29-Aug-25 2:11 PM, Marek Vasut wrote:
>>>>
>>>> On 8/8/25 12:04 PM, Naresh Kumar Ravulapalli wrote:
>>>>> Some USB devices need more time to be initialized. Hence,
>>>>> increasing the default USB Hub debounce timeout value for
>>>>> devices to be discovered, connected to Agilex5 boards.
>>>> Is this really hub debounce timeout or usb_pgood_delay ?
>>>>
>>>> Which devices are those, include that in the commit message.
>>>
>>> Yes, timeout is related to USB connect/disconnect signal bounces not
>>> about bus stability during init.
>>>
>>> Issue was mainly observed with legacy flash drives. Maybe I will change
>>> commit text from "Some USB devices need more time to be initialized..."
>>> to "Some old USB flash drives need more time to be initialized during
>>> connect or disconnect events ..."?
>>>
>>> Note that I am not modifying the default Kconfig value in general;
>>> change is only made for an SoCFPGA devkit we tested.
>> Does this same issue go away if you set usb_pgood_delay to 2000 or
>> higher too ?
> 
> No, changing USB HUB debounce timeout is working for us.
Look at this code:

https://source.denx.de/u-boot/u-boot/-/blob/master/common/usb_hub.c?ref_type=heads#L199

"
#if CONFIG_IS_ENABLED(ENV_SUPPORT)
	env = env_get("usb_pgood_delay");
	if (env)
		pgood_delay = max(pgood_delay,
			          (unsigned)simple_strtol(env, NULL, 0));
#endif
	debug("pgood_delay=%dms\n", pgood_delay);

	/*
	 * Do a minimum delay of the larger value of 100ms or pgood_delay
	 * so that the power can stablize before the devices are queried
	 */
	hub->query_delay = get_timer(0) + max(100, (int)pgood_delay);

	/*
	 * Record the power-on timeout here. The max. delay (timeout)
	 * will be done based on this value in the USB port loop in
	 * usb_hub_configure() later.
	 */
	hub->connect_timeout = hub->query_delay + HUB_DEBOUNCE_TIMEOUT;
	debug("devnum=%d poweron: query_delay=%d connect_timeout=%d\n",
	      dev->devnum, max(100, (int)pgood_delay),
	      max(100, (int)pgood_delay) + HUB_DEBOUNCE_TIMEOUT);
"

Changing both usb_pgood_delay or (CONFIG_USB_)HUB_DEBOUNCE_TIMEOUT 
should have the same effect. How come it does not ?