From: Dinh Nguyen <dinguyen@kernel.org>
To: u-boot@lists.denx.de
Subject: [U-Boot] [v4 18/29] arm: socfpga: stratix10: Add SOCFPGA Stratix10 base address
Date: Mon, 9 Jan 2017 08:47:48 -0600 [thread overview]
Message-ID: <f28adb59-cd14-0e3f-e1bf-ed829d530ba2@kernel.org> (raw)
In-Reply-To: <1483961514-3918-1-git-send-email-tien.fong.chee@intel.com>
On 01/09/2017 05:31 AM, Chee Tien Fong wrote:
> From: Tien Fong Chee <tien.fong.chee@intel.com>
>
> Add base address header file for Stratix10 SoC
>
> Signed-off-by: Chin Liang See <clsee@altera.com>
> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> Cc: Ley Foon Tan <lftan@altera.com>
> ---
> arch/arm/mach-socfpga/include/mach/base_addr_s10.h | 48 ++++++++++++++++++++
> 1 files changed, 48 insertions(+), 0 deletions(-)
> create mode 100755 arch/arm/mach-socfpga/include/mach/base_addr_s10.h
While this is really nice to see, but can you separate this patch out
from the Arria10 series. It's already confusing enough.
Dinh
next prev parent reply other threads:[~2017-01-09 14:47 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-09 11:31 [U-Boot] [v4 18/29] arm: socfpga: stratix10: Add SOCFPGA Stratix10 base address Chee Tien Fong
2017-01-09 11:31 ` [U-Boot] [v4 19/29] ARM:dts: Added device tree for socfpga arria10 development kit sdmmc Chee Tien Fong
2017-01-09 11:31 ` [U-Boot] [v4 20/29] arm: socfpga: arria10: Enable SPL for Arria 10 Chee Tien Fong
2017-01-09 11:31 ` [U-Boot] [v4 21/29] arm: socfpga: arria10: Added clock manager and pin mux compat macro Chee Tien Fong
2017-01-09 11:31 ` [U-Boot] [v4 22/29] arm: socfpga: arria10: Added some hardware base address for Arria 10 Chee Tien Fong
2017-01-09 11:31 ` [U-Boot] [v4 23/29] arm: socfpga: arria10: Added support for Arria 10 socdk Chee Tien Fong
2017-01-09 11:31 ` [U-Boot] [v4 24/29] arm: socfpga: arria10: Added drivers for Arria10 Reset Manager Chee Tien Fong
2017-01-09 11:31 ` [U-Boot] [v4 25/29] arm: socfpga: arria10: Added miscellaneous drivers for Arria 10 Chee Tien Fong
2017-01-09 11:31 ` [U-Boot] [v4 26/29] arm: socfpga: arria10: Added drivers for Arria10 clock manager Chee Tien Fong
2017-01-09 11:31 ` [U-Boot] [v4 27/29] arm: socfpga: arria10: Added drivers for Arria10 pinmux/pins configuration Chee Tien Fong
2017-01-09 11:31 ` [U-Boot] [v4 28/29] arm: socfpga: arria10: Added Arria10 critical HW initialization to spl Chee Tien Fong
2017-01-09 11:31 ` [U-Boot] [v4 29/29] arm: socfpga: arria10: Enable fpga driver build for SPL Chee Tien Fong
2017-01-09 14:47 ` Dinh Nguyen [this message]
2017-01-10 3:42 ` [U-Boot] [v4 18/29] arm: socfpga: stratix10: Add SOCFPGA Stratix10 base address Chee, Tien Fong
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