From mboxrd@z Thu Jan  1 00:00:00 1970
From: Mugunthan V N <mugunthanvnm@ti.com>
Date: Fri, 29 Jul 2016 14:12:29 +0530
Subject: [U-Boot] [PATCH 1/4] ARM: dra7xx: Change DPLL_PER_HS13 divider
	value
In-Reply-To: <20160725101547.18503-2-vigneshr@ti.com>
References: <20160725101547.18503-1-vigneshr@ti.com>
 <20160725101547.18503-2-vigneshr@ti.com>
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On Monday 25 July 2016 03:45 PM, Vignesh R wrote:
> From: Lokesh Vutla <lokeshvutla@ti.com>
> 
> According to AM572x DM SPRS953A, QSPI bus speed can be 76.8MHz, hence
> update QSPI input clock divider value (DPLL_PER_HS13) to provide 76.8MHz
> clock, so that driver can use the same.
> 
> Signed-off-by: Vignesh R <vigneshr@ti.com>
> ---

Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>

Regards
Mugunthan V N