From: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v5 07/19] arm: socfpga: Move Stratix10 and Agilex clock manager common code
Date: Tue, 22 Oct 2019 20:29:13 +0200 [thread overview]
Message-ID: <f52660db-648d-edd8-ec5e-45bca4e50253@gmail.com> (raw)
In-Reply-To: <1570787542-40896-8-git-send-email-ley.foon.tan@intel.com>
Am 11.10.2019 um 11:52 schrieb Ley Foon Tan:
> Move Stratix10 and Agilex clock manager common code to new header file.
>
> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
>
> ---
> v5:
> - Revert CLKMGR_INTOSC_HZ to 460MHz.
> ---
> .../include/mach/clock_manager_s10.h | 16 +++----------
> .../include/mach/clock_manager_soc64.h | 23 +++++++++++++++++++
> 2 files changed, 26 insertions(+), 13 deletions(-)
> create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h
>
> diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
> index fa0ba26f09..223940ba0c 100644
> --- a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
> +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
> @@ -1,6 +1,6 @@
> /* SPDX-License-Identifier: GPL-2.0
> *
> - * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
> + * Copyright (C) 2016-2019 Intel Corporation <www.intel.com>
> *
> */
>
> @@ -14,18 +14,6 @@ unsigned int cm_get_l4_sp_clk_hz(void);
> unsigned int cm_get_mmc_controller_clk_hz(void);
> unsigned int cm_get_qspi_controller_clk_hz(void);
> unsigned int cm_get_spi_controller_clk_hz(void);
> -const unsigned int cm_get_osc_clk_hz(void);
> -const unsigned int cm_get_f2s_per_ref_clk_hz(void);
> -const unsigned int cm_get_f2s_sdr_ref_clk_hz(void);
> -const unsigned int cm_get_intosc_clk_hz(void);
> -const unsigned int cm_get_fpga_clk_hz(void);
> -
> -#define CLKMGR_EOSC1_HZ 25000000
> -#define CLKMGR_INTOSC_HZ 460000000
> -#define CLKMGR_FPGA_CLK_HZ 50000000
> -
> -/* Clock configuration accessors */
> -const struct cm_config * const cm_get_default_config(void);
>
> struct cm_config {
> /* main group */
> @@ -186,4 +174,6 @@ void cm_basic_init(const struct cm_config * const cfg);
>
> #define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK 0x00000020
>
> +#include <asm/arch/clock_manager_soc64.h>
Includes are normally at the top, what prevents you from moving this up?
> +
> #endif /* _CLOCK_MANAGER_S10_ */
> diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h
> new file mode 100644
> index 0000000000..3b4bb62ca5
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h
> @@ -0,0 +1,23 @@
> +/* SPDX-License-Identifier: GPL-2.0
> + *
> + * Copyright (C) 2016-2019 Intel Corporation <www.intel.com>
> + *
> + */
> +
> +#ifndef _CLOCK_MANAGER_SOC64_
> +#define _CLOCK_MANAGER_SOC64_
> +
> +const unsigned int cm_get_osc_clk_hz(void);
> +const unsigned int cm_get_f2s_per_ref_clk_hz(void);
> +const unsigned int cm_get_f2s_sdr_ref_clk_hz(void);
> +const unsigned int cm_get_intosc_clk_hz(void);
> +const unsigned int cm_get_fpga_clk_hz(void);
> +
> +#define CLKMGR_EOSC1_HZ 25000000
> +#define CLKMGR_INTOSC_HZ 460000000
> +#define CLKMGR_FPGA_CLK_HZ 50000000
> +
> +/* Clock configuration accessors */
> +const struct cm_config * const cm_get_default_config(void);
> +
> +#endif /* _CLOCK_MANAGER_SOC64_ */
>
next prev parent reply other threads:[~2019-10-22 18:29 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-11 9:52 [U-Boot] [PATCH v5 00/19] Add Intel Agilex SoC support Ley Foon Tan
2019-10-11 9:52 ` [U-Boot] [PATCH v5 01/19] arm: socfpga: agilex: Add base address for Intel Agilex SoC Ley Foon Tan
2019-10-11 9:52 ` [U-Boot] [PATCH v5 02/19] arm: socfpga: Move firewall code to firewall file Ley Foon Tan
2019-10-11 9:52 ` [U-Boot] [PATCH v5 03/19] arm: socfpga: Move Stratix10 and Agilex reset manager common code Ley Foon Tan
2019-10-11 9:52 ` [U-Boot] [PATCH v5 04/19] arm: socfpga: agilex: Add reset manager support Ley Foon Tan
2019-10-22 18:26 ` Simon Goldschmidt
2019-10-11 9:52 ` [U-Boot] [PATCH v5 05/19] arm: socfpga: Move Stratix10 and Agilex system manager common code Ley Foon Tan
2019-10-11 9:52 ` [U-Boot] [PATCH v5 06/19] arm: socfpga: agilex: Add system manager support Ley Foon Tan
2019-10-22 18:27 ` Simon Goldschmidt
2019-10-11 9:52 ` [U-Boot] [PATCH v5 07/19] arm: socfpga: Move Stratix10 and Agilex clock manager common code Ley Foon Tan
2019-10-22 18:29 ` Simon Goldschmidt [this message]
2019-10-25 9:19 ` Ley Foon Tan
2019-10-11 9:52 ` [U-Boot] [PATCH v5 08/19] arm: socfpga: Fix CLKMGR_INTOSC_HZ to 400MHz Ley Foon Tan
2019-10-22 18:31 ` Simon Goldschmidt
2019-10-25 8:47 ` Ley Foon Tan
2019-10-11 9:52 ` [U-Boot] [PATCH v5 09/19] clk: agilex: Add clock driver for Agilex Ley Foon Tan
2019-10-11 9:52 ` [U-Boot] [PATCH v5 10/19] arm: socfpga: agilex: Add clock wrapper functions Ley Foon Tan
2019-10-11 9:52 ` [U-Boot] [PATCH v5 11/19] cache: Add Arteris Ncore cache coherent unit driver Ley Foon Tan
2019-10-22 18:32 ` Simon Goldschmidt
2019-10-11 9:52 ` [U-Boot] [PATCH v5 12/19] drivers: Enable cache driver build in SPL Ley Foon Tan
2019-10-22 18:34 ` Simon Goldschmidt
2019-10-25 9:25 ` Ley Foon Tan
2019-10-11 9:52 ` [U-Boot] [PATCH v5 13/19] arm: agilex: Add clock handoff offset for Agilex Ley Foon Tan
2019-10-11 9:52 ` [U-Boot] [PATCH v5 14/19] ddr: altera: Restructure Stratix 10 SDRAM driver Ley Foon Tan
2019-10-22 18:40 ` Simon Goldschmidt
2019-10-25 8:40 ` Ley Foon Tan
2019-10-11 9:52 ` [U-Boot] [PATCH v5 15/19] ddr: altera: agilex: Add SDRAM driver for Agilex Ley Foon Tan
2019-10-11 9:52 ` [U-Boot] [PATCH v5 16/19] board: intel: agilex: Add socdk board support for Intel Agilex SoC Ley Foon Tan
2019-10-11 9:52 ` [U-Boot] [PATCH v5 17/19] arm: socfpga: agilex: Add SPL for " Ley Foon Tan
2019-10-11 9:52 ` [U-Boot] [PATCH v5 18/19] arm: dts: agilex: Add base dtsi and devkit dts Ley Foon Tan
2019-10-11 9:52 ` [U-Boot] [PATCH v5 19/19] arm: socfpga: agilex: Enable Agilex SoC build Ley Foon Tan
2019-10-22 7:02 ` Simon Goldschmidt
2019-10-25 8:38 ` Ley Foon Tan
2019-10-22 18:42 ` Simon Goldschmidt
2019-10-25 8:39 ` Ley Foon Tan
2019-10-21 9:05 ` [U-Boot] [PATCH v5 00/19] Add Intel Agilex SoC support Ley Foon Tan
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=f52660db-648d-edd8-ec5e-45bca4e50253@gmail.com \
--to=simon.k.r.goldschmidt@gmail.com \
--cc=u-boot@lists.denx.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox