Re: DDR timing for vendor board

Rob Kramer
2022-12-09T11:10:29Z

Hi Jack,

Thanks for your suggestion, I hadn't thought of using just the rkbin ddr file together with u-boot SPL. My biggest objection was the rkbin miniloader that makes assumptions on partition layout.

It seems to work, but now I'm in for some DT pain :)

Cheers,

Rob

9 Dec 2022 00:49:30 Jack Mitchell <ml@embed.me.uk>:

> On 08/12/2022 04:01, Rob Kramer wrote:
>> Hi all,
>>
>> I have a RK3288 board from a Chinese display vendor that came with the
>> usual giant Rockchip tarball that they patched here and there to make
>> the board work. It seems to be based on a rk3288-evb, since that is what
>> they patched in the kernel. The kernel is a 4.4 kernel with Android
>> stuff in it (i.e. fiq-debugger) and a large amount of Rockchip patches,
>> u-boot is 2017.09, with rk patches.
>>
>> It turns out that u-boot TPL/SPL won't boot because the DDR timings are
>> incorrect, and the Chinese vendor uses the Rockchip
>> rk3288_ddr_400MHz_v1.09.bin loader. I'm using u-boot 2022.01 for now,
>> and I've tried to naively modify the timing in
>> arch/arm/dts/rk3288-evb.dts, but it doesn't work at all, with varying
>> errors on boot.
>>
>> The Rockchip loader provides the following info when booting:
>>
>>   In
>>   Channel a: DDR3 400MHz
>>   Bus Width=32 Col=10 Bank=8 Row=15 CS=1 Die Bus-Width=16 Size=1024MB
>>   Memory OK
>>   OUT
>>   Boot1 Release Time: Apr 11 2018 10:32:58, version: 2.36
>>   ChipType = 0x8, 232
>>
>> I've tried various DDR3 (not LPDDR3) settings from other boards, for
>> example for a Firefly (666 MHz DDR3):
>>
>>   U-Boot TPL 2022.01 (Jan 10 2022 - 18:46:34)
>>   Col detect error
>>   DRAM init failed!
>>   ### ERROR ### Please RESET the board ###
>>
>> It was expected that 666MHz doesn't work, but if I just change the
>> frequency in the dts, that also fails (error -22).
>>
>> How can I support the DDR for this board? I can't even see what the ID
>> on the chips is, because the heatsink is blocking sight and seems to be
>> attached with some sort of thermal glue.
>>
>> Is there a way to read back the DDR timings (phy-timing, sdram-params)
>> from the kernel/SoC on a board that is booted using the proprietary loader?
>>
>> Cheers!
>>
>>     Rob
>>
>
> Hi Rob,
>
> You could be in for a world of hurt here as Rockchip are very poor at
> supporting different DDR init configurations in u-boot. In the past with
> awkward boards I've used the Rockchip DDR init blob as the TPL binary
> for u-boot then skip the DRAM init in the u-boot SPL.
>
> From my travels in this area I've found that single channel RAM boards
> are particularly difficult to get working as the majority if not all
> mainlined board use dual channel RAM.
>
> Sorry I can't be more help, but trying to use the DDR blob is a good
> starting point to get you going on mainline.
>
> Good Luck!
>
> --
> Jack Mitchell, Consultant
> https://www.tuxable.co.uk