From mboxrd@z Thu Jan  1 00:00:00 1970
From: Aswath Govindraju <a-govindraju@ti.com>
Date: Tue, 6 Apr 2021 10:50:29 +0530
Subject: [PATCH] mmc: sdhci: Write to HOST_CONTROL2 register for HS400
 speed mode
In-Reply-To: <6cc5f2a0-0efe-66e0-81f5-82626b50d085@samsung.com>
References: <CGME20210405144459epcas1p3d6df22765afb126a2b2037c5364b0b2e@epcas1p3.samsung.com>
 <20210405144428.12159-1-a-govindraju@ti.com>
 <6cc5f2a0-0efe-66e0-81f5-82626b50d085@samsung.com>
Message-ID: <fdee31c5-bb0f-a458-8483-250d0ba2968e@ti.com>
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Hi Jaehoon,

On 06/04/21 3:48 am, Jaehoon Chung wrote:
> Hi,
> 
> On 4/5/21 11:44 PM, Aswath Govindraju wrote:
>> From: Faiz Abbas <faiz_abbas@ti.com>
>>
>> Enable HS400 speed mode by writing to HOST_CONTROL2 register.
> 
> I didn't find HS400 bit at HOST_CONTROL2 register. (I have checked SD Specific v4.20)
> If I missed something, let me know, plz.
> 
> In include/sdhci.h, it mentioned to "Non-standard".
> 

Thank you for pointing this out.

Yes, this is not a part of SD specification and in the specification
this field is marked as reserved. I have added this, as this bit mask
has been defined in include/sdhci.h. Sorry about this. I'll post a
respin taking this into a consideration.

Thanks,
Aswath

> Best Regards,
> Jaehoon Chung
> 
>>
>> Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
>> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
>> ---
>>  drivers/mmc/sdhci.c | 3 +++
>>  1 file changed, 3 insertions(+)
>>
>> diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
>> index d9ab6a0a839e..eea4701d8af5 100644
>> --- a/drivers/mmc/sdhci.c
>> +++ b/drivers/mmc/sdhci.c
>> @@ -507,6 +507,9 @@ void sdhci_set_uhs_timing(struct sdhci_host *host)
>>  	case MMC_HS_200:
>>  		reg |= SDHCI_CTRL_UHS_SDR104;
>>  		break;
>> +	case MMC_HS_400:
>> +		reg |= SDHCI_CTRL_HS400;
>> +		break;
>>  	default:
>>  		reg |= SDHCI_CTRL_UHS_SDR12;
>>  	}
>>
>