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[46.150.62.216]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48fc8d16bbdsm10829585e9.1.2026.05.12.10.37.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 May 2026 10:37:07 -0700 (PDT) From: Jernej =?UTF-8?B?xaBrcmFiZWM=?= To: u-boot@lists.denx.de, Andre Przywara Cc: Tom Rini , Chen-Yu Tsai , Paul Kocialkowski , linux-sunxi@lists.linux.dev Subject: Re: [PATCH 2/5] sunxi: spl: spi: Clean up SPI0 pinmux setting Date: Tue, 12 May 2026 19:37:06 +0200 Message-ID: In-Reply-To: <20260511213713.15943-3-andre.przywara@arm.com> References: <20260511213713.15943-1-andre.przywara@arm.com> <20260511213713.15943-3-andre.przywara@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Dne ponedeljek, 11. maj 2026 ob 23:37:10 Srednjeevropski poletni =C4=8Das j= e Andre Przywara napisal(a): > The function to set the pinmux for the Port C SPI0 pins was looking more > like a logic puzzle from a magazine than something that readers could > understand and extend. >=20 > Replace the convoluted pinmux setup, grouped by pin, with a simple array > of the four pins involved, and just initialise this array at build time, > based on the selected SoC. >=20 > This makes it easy to see which pins are needed, and even easier to exten= d. >=20 > Signed-off-by: Andre Przywara > --- > arch/arm/mach-sunxi/spl_spi_sunxi.c | 43 ++++++++++++----------------- > 1 file changed, 18 insertions(+), 25 deletions(-) >=20 > diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c b/arch/arm/mach-sunxi/sp= l_spi_sunxi.c > index 5f72e809952..905a7db2a77 100644 > --- a/arch/arm/mach-sunxi/spl_spi_sunxi.c > +++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c > @@ -105,35 +105,28 @@ > =20 > /* > * Allwinner A10/A20 SoCs were using pins PC0,PC1,PC2,PC23 for booting > - * from SPI Flash, everything else is using pins PC0,PC1,PC2,PC3. > - * The H6 uses PC0, PC2, PC3, PC5, the H616 PC0, PC2, PC3, PC4. > + * from SPI Flash, later SoCs are using pins PC0,PC1,PC2,PC3. > + * Newer SoCs are all over the place. > */ > static void spi0_pinmux_setup(unsigned int pin_function) > { > - /* All chips use PC2. And all chips use PC0, except R528/T113 */ > - if (!IS_ENABLED(CONFIG_MACH_SUN8I_R528)) > - sunxi_gpio_set_cfgpin(SUNXI_GPC(0), pin_function); > - > - sunxi_gpio_set_cfgpin(SUNXI_GPC(2), pin_function); > + const u16 spi0_pc_pins[4] =3D { > +#if IS_ENABLED(CONFIG_MACH_SUN8I_R528) > + SUNXI_GPC(2), SUNXI_GPC(3), SUNXI_GPC(4), SUNXI_GPC(5) > +#elif IS_ENABLED(CONFIG_MACH_SUN50I_H616) > + SUNXI_GPC(0), SUNXI_GPC(2), SUNXI_GPC(3), SUNXI_GPC(4) > +#elif IS_ENABLED(CONFIG_MACH_SUN50I_H6) > + SUNXI_GPC(0), SUNXI_GPC(2), SUNXI_GPC(3), SUNXI_GPC(5) > +#elif IS_ENABLED(CONFIG_MACH_SUN4I) || IS_ENABLED(CONFIG_MACH_SUN5I) || \ Are you sure about CONFIG_MACH_SUN5I? It seems to me that it should fall to= PC3 pin. Also A13 datasheet confirms it. Best regards, Jernej > + IS_ENABLED(CONFIG_MACH_SUN7I) || IS_ENABLED(CONFIG_MACH_SUN8I_R40) > + SUNXI_GPC(0), SUNXI_GPC(1), SUNXI_GPC(2), SUNXI_GPC(23) > +#else > + SUNXI_GPC(0), SUNXI_GPC(1), SUNXI_GPC(2), SUNXI_GPC(3) > +#endif > + }; > =20 > - /* All chips except H6/H616/R528/T113 use PC1. */ > - if (!IS_ENABLED(CONFIG_SUN50I_GEN_H6) && > - !IS_ENABLED(CONFIG_MACH_SUN8I_R528)) > - sunxi_gpio_set_cfgpin(SUNXI_GPC(1), pin_function); > - > - if (IS_ENABLED(CONFIG_MACH_SUN50I_H6) || > - IS_ENABLED(CONFIG_MACH_SUN8I_R528)) > - sunxi_gpio_set_cfgpin(SUNXI_GPC(5), pin_function); > - if (IS_ENABLED(CONFIG_MACH_SUN50I_H616) || > - IS_ENABLED(CONFIG_MACH_SUN8I_R528)) > - sunxi_gpio_set_cfgpin(SUNXI_GPC(4), pin_function); > - > - /* Older generations use PC23 for CS, newer ones use PC3. */ > - if (IS_ENABLED(CONFIG_MACH_SUN4I) || IS_ENABLED(CONFIG_MACH_SUN7I) || > - IS_ENABLED(CONFIG_MACH_SUN8I_R40)) > - sunxi_gpio_set_cfgpin(SUNXI_GPC(23), pin_function); > - else > - sunxi_gpio_set_cfgpin(SUNXI_GPC(3), pin_function); > + for (int i =3D 0; i < 4; i++) > + sunxi_gpio_set_cfgpin(spi0_pc_pins[i], pin_function); > } > =20 > static bool is_sun6i_gen_spi(void) >=20