From mboxrd@z Thu Jan  1 00:00:00 1970
From: Gregg Nemas <gnemas@gmail.com>
Date: Thu, 6 Oct 2005 17:37:31 +0000 (UTC)
Subject: [U-Boot-Users] Burst I/O on PPC440GP
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I am trying to perform I/O with a device attached to the external peripheral bus
on a PPC440GP embedded processor. I am able to address the device and read and
write to it, but I am only able to do non-burst I/O. Do I need to do something
special to enable burst transactions? I've programmed the EBC0_B5CR and
EBC0_B5AP device control registers appropriately to enable burst mode, but the
transactions are still single I/O.

I've been testing this by using the u-boot mw.l command. Do I need to use
PPC-specific instructions to perform burst I/O, or should an ordinary programmed
I/O (using 32-bit write operations) be automatically queued up and converted to
burst transactions?

The TLB I've added for the I/O region has the caching inhibit (I) and guarded
(G) bits set. Does caching or speculative access need to be enabled to allow
bursting? Even if I added a TLB entry, it wouldn't do me any good in Linux,
since it manages TLBs itself. So how would I do this from a Linux kernel driver?

Thanks.

Gregg