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From: Detlev Zundel <dzu@denx.de>
To: u-boot@lists.denx.de
Subject: [U-Boot-Users] Enabling Cache in MPC5200
Date: Wed, 05 Sep 2007 12:54:42 +0200	[thread overview]
Message-ID: <m21wdd9ybx.fsf@ohwell.denx.de> (raw)
In-Reply-To: <18006748.3362451188893499288.JavaMail.nabble@isper.nabble.com> (santoshguru@yahoo.com's message of "Tue\, 04 Sep 2007 01\:11\:39 -0700")

Hi San,

> I am using a LITE5200 evaluation board, and am not able to enable the cache.
> The execution hangs in these calls.
> void EnableInstCache(void)
> {

[...]

> }
>
> void EnableDataCache(void)
> {

[...]

> }
> What could be the problem?

It might be one of our favourites, i.e. wrong ram initialization.
When enabling the caches, the CPU generates burst accesses for the
first time.  It is pretty common (on this mailing list) that not quite
correctly initialized RAM works for single beat but fails for bursts.
So my advice would be to check the RAM init.

Is is really a standard lite5200 board that you use?

Cheers
  Detlev

-- 
The best way to predict the future is to invent it.
                                           -- Alan Kay
--
DENX Software Engineering GmbH,      MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich,  Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-40 Fax: (+49)-8142-66989-80 Email: dzu at denx.de

  reply	other threads:[~2007-09-05 10:54 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2007-09-04  8:11 [U-Boot-Users] Enabling Cache in MPC5200 santoshguru at yahoo.com
2007-09-05 10:54 ` Detlev Zundel [this message]
2007-09-05 12:25   ` sanguru

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