[U-Boot] unassigned-patches/24: [PATCH] PHY: Add support for the M88E1121R Marvell chip.

[U-Boot] unassigned-patches/24: [PATCH] PHY: Add support for the M88E1121R Marvell chip.

[u-boot at bugs.denx.de]

Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>

---
Added to GNATS database as unassigned-patches/24
>Responsible:    patch-coord
>Message-Id:     <1218807733-26929-1-git-send-email-dzu@denx.de>
>In-Reply-To:    
>References:     
>Patch-Date:     Fri Aug 15 15:42:08 +0200 2008
---
 drivers/net/tsec.c |   50 ++++++++++++++++++++++++++++++++++++++++++++++++++
 drivers/net/tsec.h |    7 +++++++
 2 files changed, 57 insertions(+), 0 deletions(-)

diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index 6e0f2c6..fb5002d 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -1157,6 +1157,55 @@ struct phy_info phy_info_M88E1118 = {
 		},
 };
 
+/*
+ *  Since to access LED register we need do switch the page, we
+ * do LED configuring in the miim_read-like function as follows
+ */
+uint mii_88E1121_set_led (uint mii_reg, struct tsec_private *priv)
+{
+	uint pg;
+
+	/* Switch the page to access the led register */
+	pg = read_phy_reg(priv, MIIM_88E1121_PHY_PAGE);
+	write_phy_reg(priv, MIIM_88E1121_PHY_PAGE, MIIM_88E1121_PHY_LED_PAGE);
+
+	/* Configure leds */
+	write_phy_reg(priv, MIIM_88E1121_PHY_LED_CTRL,
+		      MIIM_88E1121_PHY_LED_DEF);
+
+	/* Restore the page pointer */
+	write_phy_reg(priv, MIIM_88E1121_PHY_PAGE, pg);
+	return 0;
+}
+
+struct phy_info phy_info_M88E1121R = {
+	0x01410cb,
+	"Marvell 88E1121R",
+	4,
+	(struct phy_cmd[]){	/* config */
+		/* Reset and configure the PHY */
+		{MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
+		{MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
+		{MIIM_ANAR, MIIM_ANAR_INIT, NULL},
+		/* Configure leds */
+		{MIIM_88E1121_PHY_LED_CTRL, miim_read,
+		 &mii_88E1121_set_led},
+		{MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
+		{miim_end,}
+		},
+	(struct phy_cmd[]){	/* startup */
+		/* Status is read once to clear old link state */
+		{MIIM_STATUS, miim_read, NULL},
+		{MIIM_STATUS, miim_read, &mii_parse_sr},
+		{MIIM_STATUS, miim_read, &mii_parse_link},
+		{miim_end,}
+		},
+	(struct phy_cmd[]){	/* shutdown */
+		{miim_end,}
+		},
+};
+
+
 static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv)
 {
 	uint mii_data = read_phy_reg(priv, mii_reg);
@@ -1522,6 +1571,7 @@ struct phy_info *phy_info[] = {
 	&phy_info_M88E1011S,
 	&phy_info_M88E1111S,
 	&phy_info_M88E1118,
+	&phy_info_M88E1121R,
 	&phy_info_M88E1145,
 	&phy_info_M88E1149S,
 	&phy_info_dm9161,
diff --git a/drivers/net/tsec.h b/drivers/net/tsec.h
index 6a2338b..fee5934 100644
--- a/drivers/net/tsec.h
+++ b/drivers/net/tsec.h
@@ -184,6 +184,13 @@
 #define MIIM_88E1111_PHY_LED_DIRECT	0x4100
 #define MIIM_88E1111_PHY_LED_COMBINE	0x411C
 
+/* 88E1121 PHY LED Control Register */
+#define MIIM_88E1121_PHY_LED_CTRL	16
+#define MIIM_88E1121_PHY_LED_PAGE	3
+#define MIIM_88E1121_PHY_LED_DEF	0x0030
+
+#define MIIM_88E1121_PHY_PAGE		22
+
 /* 88E1145 Extended PHY Specific Control Register */
 #define MIIM_88E1145_PHY_EXT_CR 20
 #define MIIM_M88E1145_RGMII_RX_DELAY	0x0080
-- 
1.5.6.1

[U-Boot] unassigned-patches/24: [PATCH] PHY: Add support for the M88E1121R Marvell chip.

[Detlev Zundel]

Hi Ben,

> Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
> Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
>
> ---
> Added to GNATS database as unassigned-patches/24
>>Responsible:    patch-coord
>>Message-Id:     <1218807733-26929-1-git-send-email-dzu@denx.de>
>>In-Reply-To:    
>>References:     
>>Patch-Date:     Fri Aug 15 15:42:08 +0200 2008
> ---
>  drivers/net/tsec.c |   50 ++++++++++++++++++++++++++++++++++++++++++++++++++
>  drivers/net/tsec.h |    7 +++++++
>  2 files changed, 57 insertions(+), 0 deletions(-)

Any comments on this patch?

Thanks
  Detlev

-- 
The limits of my language stand for the limits of my world.
                                        -- Ludwig Wittgenstein
--
DENX Software Engineering GmbH,      MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich,  Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-40 Fax: (+49)-8142-66989-80 Email: dzu at denx.de

[U-Boot] unassigned-patches/24: [PATCH] PHY: Add support for the M88E1121R Marvell chip.

[Ben Warren]

Hi Detlev,

Detlev Zundel wrote:
> Hi Ben,
>
>   
>> Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
>> Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
>>
>> ---
>> Added to GNATS database as unassigned-patches/24
>>     
>>> Responsible:    patch-coord
>>> Message-Id:     <1218807733-26929-1-git-send-email-dzu@denx.de>
>>> In-Reply-To:    
>>> References:     
>>> Patch-Date:     Fri Aug 15 15:42:08 +0200 2008
>>>       
>> ---
>>  drivers/net/tsec.c |   50 ++++++++++++++++++++++++++++++++++++++++++++++++++
>>  drivers/net/tsec.h |    7 +++++++
>>  2 files changed, 57 insertions(+), 0 deletions(-)
>>     
>
> Any comments on this patch?
>
> Thanks
>   Detlev
>
>   
Hi Detlev,

It looks like this one slipped through the cracks. I've looked through 
my e-mails and found one from Wolfgang on 6/8 where he said he'd apply 
it, so I acked the patch rather than pulling it myself. For whatever 
reason, it didn't make it in.

I've rejigged the patch to apply to TOT, and have applied to the net 
repo. Please find the fixed-up patch attached, as applied to 
e99e9575bbeba1b7c48e046547cae065ec0071de

[PATCH] PHY: Add support for the M88E1121R Marvell chip.

From: Sergei Poselenov <sposelenov@emcraft.com>

Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
---
 drivers/net/tsec.c |   49 +++++++++++++++++++++++++++++++++++++++++++++++++
 drivers/net/tsec.h |    7 +++++++
 2 files changed, 56 insertions(+), 0 deletions(-)

diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index c7af930..565da5c 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -1157,6 +1157,54 @@ struct phy_info phy_info_M88E1118 = {
 		},
 };
 
+/*
+ *  Since to access LED register we need do switch the page, we
+ * do LED configuring in the miim_read-like function as follows
+ */
+uint mii_88E1121_set_led (uint mii_reg, struct tsec_private *priv)
+{
+	uint pg;
+
+	/* Switch the page to access the led register */
+	pg = read_phy_reg(priv, MIIM_88E1121_PHY_PAGE);
+	write_phy_reg(priv, MIIM_88E1121_PHY_PAGE, MIIM_88E1121_PHY_LED_PAGE);
+
+	/* Configure leds */
+	write_phy_reg(priv, MIIM_88E1121_PHY_LED_CTRL,
+		      MIIM_88E1121_PHY_LED_DEF);
+
+	/* Restore the page pointer */
+	write_phy_reg(priv, MIIM_88E1121_PHY_PAGE, pg);
+	return 0;
+}
+
+struct phy_info phy_info_M88E1121R = {
+	0x01410cb,
+	"Marvell 88E1121R",
+	4,
+	(struct phy_cmd[]){	/* config */
+			   /* Reset and configure the PHY */
+			   {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
+			   {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
+			   {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
+			   /* Configure leds */
+			   {MIIM_88E1121_PHY_LED_CTRL, miim_read,
+			    &mii_88E1121_set_led},
+			   {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
+			   {miim_end,}
+			   },
+	(struct phy_cmd[]){	/* startup */
+			   /* Status is read once to clear old link state */
+			   {MIIM_STATUS, miim_read, NULL},
+			   {MIIM_STATUS, miim_read, &mii_parse_sr},
+			   {MIIM_STATUS, miim_read, &mii_parse_link},
+			   {miim_end,}
+			   },
+	(struct phy_cmd[]){	/* shutdown */
+			   {miim_end,}
+			   },
+};
+
 static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv)
 {
 	uint mii_data = read_phy_reg(priv, mii_reg);
@@ -1521,6 +1569,7 @@ struct phy_info *phy_info[] = {
 	&phy_info_BCM5464S,
 	&phy_info_M88E1011S,
 	&phy_info_M88E1111S,
 	&phy_info_M88E1118,
+	&phy_info_M88E1121R,
 	&phy_info_M88E1145,
 	&phy_info_M88E1149S,
diff --git a/drivers/net/tsec.h b/drivers/net/tsec.h
index 6a2338b..fee5934 100644
--- a/drivers/net/tsec.h
+++ b/drivers/net/tsec.h
@@ -184,6 +184,13 @@
 #define MIIM_88E1111_PHY_LED_DIRECT	0x4100
 #define MIIM_88E1111_PHY_LED_COMBINE	0x411C
 
+/* 88E1121 PHY LED Control Register */
+#define MIIM_88E1121_PHY_LED_CTRL	16
+#define MIIM_88E1121_PHY_LED_PAGE	3
+#define MIIM_88E1121_PHY_LED_DEF	0x0030
+
+#define MIIM_88E1121_PHY_PAGE		22
+
 /* 88E1145 Extended PHY Specific Control Register */
 #define MIIM_88E1145_PHY_EXT_CR 20
 #define MIIM_M88E1145_RGMII_RX_DELAY	0x0080
-- 
1.5.4.2

[U-Boot] unassigned-patches/24: [PATCH] PHY: Add support for the M88E1121R Marvell chip.

[Detlev Zundel]

Hi Ben,

> It looks like this one slipped through the cracks. I've looked through
> my e-mails and found one from Wolfgang on 6/8 where he said he'd apply
> it, so I acked the patch rather than pulling it myself. For whatever
> reason, it didn't make it in.
>
> I've rejigged the patch to apply to TOT, and have applied to the net
> repo. Please find the fixed-up patch attached, as applied to
> e99e9575bbeba1b7c48e046547cae065ec0071de

Excellent.  Any idea on when you will send a pull request?

Thanks
  Detlev

-- 
five monkeys, two typewriters, ten minutes
--
DENX Software Engineering GmbH,      MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich,  Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-40 Fax: (+49)-8142-66989-80 Email: dzu at denx.de

[U-Boot] unassigned-patches/24: [PATCH] PHY: Add support for the M88E1121R Marvell chip.

[Ben Warren]

Hi Detlev,

On Mon, Sep 1, 2008 at 3:48 PM, Detlev Zundel <dzu@denx.de> wrote:
> Hi Ben,
>
>> It looks like this one slipped through the cracks. I've looked through
>> my e-mails and found one from Wolfgang on 6/8 where he said he'd apply
>> it, so I acked the patch rather than pulling it myself. For whatever
>> reason, it didn't make it in.
>>
>> I've rejigged the patch to apply to TOT, and have applied to the net
>> repo. Please find the fixed-up patch attached, as applied to
>> e99e9575bbeba1b7c48e046547cae065ec0071de
>
> Excellent.  Any idea on when you will send a pull request?
>

The only thing holding me back is that there are quite a few changes
that were posted over the weekend or today (a statutory holiday in the
U.S. and Canada) and would like to give people more time to review.
If it's OK with you, I'll send a pull request tomorrow night so you
guys have it first thing Wednesday morning.

If you don't think this precaution is necessary, I can send a request tonight.

regards,
Ben

[U-Boot] unassigned-patches/24: [PATCH] PHY: Add support for the M88E1121R Marvell chip.

[Detlev Zundel]

Hi Ben,

> Hi Detlev,
>
> On Mon, Sep 1, 2008 at 3:48 PM, Detlev Zundel <dzu@denx.de> wrote:
>> Hi Ben,
>>
>>> It looks like this one slipped through the cracks. I've looked through
>>> my e-mails and found one from Wolfgang on 6/8 where he said he'd apply
>>> it, so I acked the patch rather than pulling it myself. For whatever
>>> reason, it didn't make it in.
>>>
>>> I've rejigged the patch to apply to TOT, and have applied to the net
>>> repo. Please find the fixed-up patch attached, as applied to
>>> e99e9575bbeba1b7c48e046547cae065ec0071de
>>
>> Excellent.  Any idea on when you will send a pull request?
>>
>
> The only thing holding me back is that there are quite a few changes
> that were posted over the weekend or today (a statutory holiday in the
> U.S. and Canada) and would like to give people more time to review.
> If it's OK with you, I'll send a pull request tomorrow night so you
> guys have it first thing Wednesday morning.

Thats fine.

> If you don't think this precaution is necessary, I can send a request tonight.

Don't get me wrong, I did not want to push you.  I only wanted to know
at what time I'd need to send reminders again ;)

Cheers
  Detlev

-- 
5.7: Practically speaking, what is the difference between arrays and pointers?
About the difference between alcohol and marijuana; they have different
characteristics, and that's not a problem if you don't mix them too carelessly.
                           - Infrequently Asked Questions in comp.lang.c
--
DENX Software Engineering GmbH,      MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich,  Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-40 Fax: (+49)-8142-66989-80 Email: dzu at denx.de

[U-Boot] unassigned-patches/23: [PATCH] RX 8025 RTC: analyze 12/24-hour mode flag in rtc_get().

[u-boot at bugs.denx.de]

Signed-off-by: Yuri Tikhonov <yur@emcraft.com>

---
Added to GNATS database as unassigned-patches/23
>Responsible:    patch-coord
>Message-Id:     <1218807733-26929-2-git-send-email-dzu@denx.de>
>In-Reply-To:    <1218807733-26929-1-git-send-email-dzu@denx.de>
>References:     <1218807733-26929-1-git-send-email-dzu@denx.de>
>Patch-Date:     Fri Aug 15 15:42:09 +0200 2008
---
 drivers/rtc/rx8025.c |    6 +++++-
 1 files changed, 5 insertions(+), 1 deletions(-)

diff --git a/drivers/rtc/rx8025.c b/drivers/rtc/rx8025.c
index 64eafe5..6ba9df2 100644
--- a/drivers/rtc/rx8025.c
+++ b/drivers/rtc/rx8025.c
@@ -136,7 +136,11 @@ int rtc_get (struct rtc_time *tmp)
 
 	tmp->tm_sec  = bcd2bin (sec & 0x7F);
 	tmp->tm_min  = bcd2bin (min & 0x7F);
-	tmp->tm_hour = bcd2bin (hour & 0x3F);
+	if (rtc_read(RTC_CTL1_REG_ADDR) & RTC_CTL1_BIT_2412)
+		tmp->tm_hour = bcd2bin (hour & 0x3F);
+	else
+		tmp->tm_hour = bcd2bin (hour & 0x1F) % 12 +
+			       ((hour & 0x20) ? 12 : 0);
 	tmp->tm_mday = bcd2bin (mday & 0x3F);
 	tmp->tm_mon  = bcd2bin (mon & 0x1F);
 	tmp->tm_year = bcd2bin (year) + ( bcd2bin (year) >= 70 ? 1900 : 2000);
-- 
1.5.6.1

[U-Boot] unassigned-patches/23: [PATCH] RX 8025 RTC: analyze 12/24-hour mode flag in rtc_get().

[Detlev Zundel]

Hi Wolfgang,

> Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
>
> ---
> Added to GNATS database as unassigned-patches/23
>>Responsible:    patch-coord
>>Message-Id:     <1218807733-26929-2-git-send-email-dzu@denx.de>
>>In-Reply-To:    <1218807733-26929-1-git-send-email-dzu@denx.de>
>>References:     <1218807733-26929-1-git-send-email-dzu@denx.de>
>>Patch-Date:     Fri Aug 15 15:42:09 +0200 2008
> ---
>  drivers/rtc/rx8025.c |    6 +++++-
>  1 files changed, 5 insertions(+), 1 deletions(-)

Any comments on this?

Thanks
  Detlev

-- 
Q:  What does FAQ stand for?
A:  We are Frequently Asked this Question, and we have no idea.
--
DENX Software Engineering GmbH,      MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich,  Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-40 Fax: (+49)-8142-66989-80 Email: dzu at denx.de

[U-Boot] unassigned-patches/22: [PATCH] Removed hardcoded MxMR loop value from upmconfig() for MPC85xx.

[u-boot at bugs.denx.de]

Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>

---
Added to GNATS database as unassigned-patches/22
>Responsible:    patch-coord
>Message-Id:     <1218807733-26929-4-git-send-email-dzu@denx.de>
>In-Reply-To:    <1218807733-26929-3-git-send-email-dzu@denx.de>
>References:     <1218807733-26929-1-git-send-email-dzu@denx.de> <1218807733-26929-2-git-send-email-dzu@denx.de> <1218807733-26929-3-git-send-email-dzu@denx.de>
>Patch-Date:     Fri Aug 15 15:42:11 +0200 2008
---
 cpu/mpc85xx/cpu.c |   16 ++++++++--------
 1 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c
index bde8e56..eb041bb 100644
--- a/cpu/mpc85xx/cpu.c
+++ b/cpu/mpc85xx/cpu.c
@@ -288,16 +288,16 @@ int dma_xfer(void *dest, uint count, void *src) {
 	return dma_check();
 }
 #endif
+
 /*
- * Configures a UPM. Currently, the loop fields in MxMR (RLF, WLF and TLF)
- * are hardcoded as "1"."size" is the number or entries, not a sizeof.
+ * Configures a UPM. The function requires the respective MxMR to be set
+ * before calling this function. "size" is the number or entries, not a sizeof.
  */
 void upmconfig (uint upm, uint * table, uint size)
 {
 	int i, mdr, mad, old_mad = 0;
 	volatile u32 *mxmr;
 	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
-	int loopval = 0x00004440;
 	volatile u32 *brp,*orp;
 	volatile u8* dummy = NULL;
 	int upmmask;
@@ -325,8 +325,8 @@ void upmconfig (uint upm, uint * table, uint size)
 		 i++, brp += 2, orp += 2) {
 
 		/* Look for a valid BR with selected UPM */
-		if ((in_be32(brp) & (BR_V | upmmask)) == (BR_V | upmmask)) {
-			dummy = (volatile u8*)(in_be32(brp) >> BR_BA_SHIFT);
+		if ((in_be32(brp) & (BR_V | BR_MSEL)) == (BR_V | upmmask)) {
+			dummy = (volatile u8*)(in_be32(brp) & BR_BA);
 			break;
 		}
 	}
@@ -338,7 +338,7 @@ void upmconfig (uint upm, uint * table, uint size)
 
 	for (i = 0; i < size; i++) {
 		/* 1 */
-		out_be32(mxmr, loopval | 0x10000000 | i); /* OP_WRITE */
+		out_be32(mxmr,  (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_WARR | i);
 		/* 2 */
 		out_be32(&lbc->mdr, table[i]);
 		/* 3 */
@@ -347,11 +347,11 @@ void upmconfig (uint upm, uint * table, uint size)
 		*(volatile u8 *)dummy = 0;
 		/* 5 */
 		do {
-			mad = in_be32(mxmr) & 0x3f;
+			mad = in_be32(mxmr) & MxMR_MAD_MSK;
 		} while (mad <= old_mad && !(!mad && i == (size-1)));
 		old_mad = mad;
 	}
-	out_be32(mxmr, loopval); /* OP_NORMAL */
+	out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_NORM);
 }
 
 #if defined(CONFIG_TSEC_ENET) || defined(CONFIGMPC85XX_FEC)
-- 
1.5.6.1

[U-Boot] unassigned-patches/27: [PATCH] 85xx: Socrates: Major code update.

[u-boot at bugs.denx.de]

- Update the local bus ranges in the FDT for Linux for the various
  devices connected to the local bus via chip-select.

- Set the LCRR_DBYP bit in the LCRR for local bus frequencies
  lower than 66 MHz and uses I/O accessor functions consequently.

- UPM data update.

- Update of default environment and configuration.  Use I2C multibus
  as we do have two I2C buses.  Also enable sdram and ext2 commands.

Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
Signed-off-by: Detlev Zundel <dzu@denx.de>

---
Added to GNATS database as unassigned-patches/27
>Responsible:    patch-coord
>Message-Id:     <1218807733-26929-5-git-send-email-dzu@denx.de>
>In-Reply-To:    <1218807733-26929-4-git-send-email-dzu@denx.de>
>References:     <1218807733-26929-1-git-send-email-dzu@denx.de> <1218807733-26929-2-git-send-email-dzu@denx.de> <1218807733-26929-3-git-send-email-dzu@denx.de> <1218807733-26929-4-git-send-email-dzu@denx.de>
>Patch-Date:     Fri Aug 15 15:42:12 +0200 2008
---
 board/socrates/socrates.c  |   82 +++++++++++++++++++-------------
 board/socrates/upm_table.h |   32 ++++++------
 include/configs/socrates.h |  110 +++++++++++++++++++++++++++-----------------
 3 files changed, 132 insertions(+), 92 deletions(-)

diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c
index d791f11..63694a7 100644
--- a/board/socrates/socrates.c
+++ b/board/socrates/socrates.c
@@ -37,9 +37,8 @@
 #include <fdt_support.h>
 #include <asm/io.h>
 
-#if defined(CFG_FPGA_BASE)
 #include "upm_table.h"
-#endif
+
 DECLARE_GLOBAL_DATA_PTR;
 
 extern flash_info_t flash_info[];	/* FLASH chips info */
@@ -50,6 +49,7 @@ ulong flash_get_size (ulong base, int banknum);
 int checkboard (void)
 {
 	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+
 	char *src;
 	int f;
 	char *s = getenv("serial#");
@@ -79,10 +79,6 @@ int checkboard (void)
 	 * Initialize local bus.
 	 */
 	local_bus_init ();
-#if defined(CFG_FPGA_BASE)
-	/* Init UPMA for FPGA access */
-	upmconfig(UPMA, (uint *)UPMTableA, sizeof(UPMTableA)/sizeof(int));
-#endif
 	return 0;
 }
 
@@ -149,15 +145,34 @@ int misc_init_r (void)
  */
 void local_bus_init (void)
 {
-
 	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
 	volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
+	sys_info_t sysinfo;
+	uint clkdiv;
+	uint lbc_mhz;
+	uint lcrr = CFG_LBC_LCRR;
+
+	get_sys_info (&sysinfo);
+	clkdiv = lbc->lcrr & 0x0f;
+	lbc_mhz = sysinfo.freqSystemBus / 1000000 / clkdiv;
+
+	/* Disable PLL bypass for Local Bus Clock >= 66 MHz */
+	if (lbc_mhz >= 66)
+		lcrr &= ~LCRR_DBYP;	/* DLL Enabled */
+	else
+		lcrr |= LCRR_DBYP;	/* DLL Bypass */
+
+	out_be32 (&lbc->lcrr, lcrr);
+	asm ("sync;isync;msync");
 
-	lbc->ltesr = 0xffffffff;	/* Clear LBC error interrupts */
-	lbc->lteir = 0xffffffff;	/* Enable LBC error interrupts */
-	ecm->eedr = 0xffffffff;		/* Clear ecm errors */
-	ecm->eeer = 0xffffffff;		/* Enable ecm errors */
+	out_be32 (&lbc->ltesr, 0xffffffff);	/* Clear LBC error interrupts */
+	out_be32 (&lbc->lteir, 0xffffffff);	/* Enable LBC error interrupts */
+	out_be32 (&ecm->eedr, 0xffffffff);	/* Clear ecm errors */
+	out_be32 (&ecm->eeer, 0xffffffff);	/* Enable ecm errors */
 
+	/* Init UPMA for FPGA access */
+	out_be32 (&lbc->mamr, 0x44440); /* Use a customer-supplied value */
+	upmconfig (UPMA, (uint *)UPMTableA, sizeof(UPMTableA)/sizeof(int));
 }
 
 #if defined(CONFIG_PCI)
@@ -197,9 +212,14 @@ void pci_init_board (void)
 #ifdef CONFIG_BOARD_EARLY_INIT_R
 int board_early_init_r (void)
 {
-#ifdef CONFIG_PS2MULT
-	ps2mult_early_init();
-#endif /* CONFIG_PS2MULT */
+	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+
+	/* set and reset the GPIO pin 2 which will reset the W83782G chip */
+	out_8((unsigned char*)&gur->gpoutdr, 0x3F );
+	out_be32((unsigned int*)&gur->gpiocr, 0x200 );	/* enable GPOut */
+	udelay(200);
+	out_8( (unsigned char*)&gur->gpoutdr, 0x1F );
+
 	return (0);
 }
 #endif /* CONFIG_BOARD_EARLY_INIT_R */
@@ -208,31 +228,27 @@ int board_early_init_r (void)
 void
 ft_board_setup(void *blob, bd_t *bd)
 {
-	u32 val[4];
-	int rc;
+	u32 val[12];
+	int rc, i = 0;
 
 	ft_cpu_setup(blob, bd);
 
-	/* Fixup NOR mapping */
-	val[0] = 0;				/* chip select number */
-	val[1] = 0;				/* always 0 */
-	val[2] = gd->bd->bi_flashstart;
-	val[3] = gd->bd->bi_flashsize;
+	/* Fixup NOR FLASH mapping */
+	val[i++] = 0;				/* chip select number */
+	val[i++] = 0;				/* always 0 */
+	val[i++] = gd->bd->bi_flashstart;
+	val[i++] = gd->bd->bi_flashsize;
 
-	rc = fdt_find_and_setprop(blob, "/localbus", "ranges",
-				  val, sizeof(val), 1);
-	if (rc)
-		printf("Unable to update property NOR mapping, err=%s\n",
-		       fdt_strerror(rc));
+	/* Fixup FPGA mapping */
+	val[i++] = 3;				/* chip select number */
+	val[i++] = 0;				/* always 0 */
+	val[i++] = CFG_FPGA_BASE;
+	val[i++] = CFG_FPGA_SIZE;
 
-#if defined (CFG_FPGA_BASE)
-	memset(val, 0, sizeof(val));
-	val[0] = CFG_FPGA_BASE;
-	rc = fdt_find_and_setprop(blob, "/localbus/fpga", "virtual-reg",
-				  val, sizeof(val), 1);
+	rc = fdt_find_and_setprop(blob, "/localbus", "ranges",
+				  val, i * sizeof(u32), 1);
 	if (rc)
-		printf("Unable to update property \"fpga\", err=%s\n",
+		printf("Unable to update localbus ranges, err=%s\n",
 		       fdt_strerror(rc));
-#endif
 }
 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/socrates/upm_table.h b/board/socrates/upm_table.h
index ea64a59..ed8f887 100644
--- a/board/socrates/upm_table.h
+++ b/board/socrates/upm_table.h
@@ -34,22 +34,22 @@
 /* UPM Table Configuration Code for FPGA access */
 static const unsigned int UPMTableA[] =
 {
-	0x00fcfc00,  0x00fcfc00,  0x00fcfc00,  0x00fcfc00, /* Words  0 to  3 */
-	0x00fcfc00,  0x00fcfc00,  0x00fcfc00,  0x00fcfc05, /* Words  4 to  7 */
-	0x00fcfc00,  0x00fcfc00,  0x00fcfc04,  0x00fcfc04, /* Words  8 to 11 */
-	0x00fcfc04,  0x00fcfc04,  0x00fcfc04,  0x00fcfc04, /* Words 12 to 15 */
-	0x00fcfc04,  0x00fcfc04,  0x00fcfc00,  0xfffffc00, /* Words 16 to 19 */
-	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc01, /* Words 20 to 23 */
-	0x0ffffc00,  0x0ffffc00,  0x0ffffc00,  0x00f3fc04, /* Words 24 to 27 */
-	0x0ffffc00,  0xfffffc01,  0xfffffc00,  0xfffffc01, /* Words 28 to 31 */
-	0x0ffffc00,  0x00f3fc04,  0x00f3fc04,  0x00f3fc04, /* Words 32 to 35 */
-	0x00f3fc04,  0x00f3fc04,  0x00f3fc04,  0x00f3fc04, /* Words 36 to 39 */
-	0x00f3fc04,  0x0ffffc00,  0xfffffc00,  0xfffffc00, /* Words 40 to 43 */
-	0xfffffc01,  0xfffffc00,  0xfffffc00,  0xfffffc01, /* Words 44 to 47 */
-	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc00, /* Words 48 to 51 */
-	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc00, /* Words 52 to 55 */
-	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc01, /* Words 56 to 59 */
-	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc01  /* Words 60 to 63 */
+	0x00fcec00,  0x00fcec00,  0x00fcec00,  0x00fcec00, /* Words 0 to 3	*/
+	0x00fcec00,  0x00fcfc00,  0x00fcfc00,  0x00fcec05, /* Words 4 to 7	*/
+	0x00fcec00,  0x00fcec00,  0x00fcec04,  0x00fcec04, /* Words 8 to 11	*/
+	0x00fcec04,  0x00fcec04,  0x00fcec04,  0x00fcec04, /* Words 12 to 15	*/
+	0x00fcec04,  0x00fcec04,  0x0fffec00,  0xffffec00, /* Words 16 to 19	*/
+	0xffffec00,  0xffffec00,  0xffffec00,  0xffffec01, /* Words 20 to 23	*/
+	0x00ffec00,  0x00ffec00,  0x00f3ec00,  0x0fffec00, /* Words 24 to 27	*/
+	0x0ffffc04,  0xffffec00,  0xffffec00,  0xffffec01, /* Words 28 to 31	*/
+	0x00ffec00,  0x00ffec00,  0x00f3ec04,  0x00f3ec04, /* Words 32 to 35	*/
+	0x00f3ec04,  0x00f3ec04,  0x00f3ec04,  0x00f3ec04, /* Words 36 to 39	*/
+	0x00f3ec04,  0x00f3ec04,  0x0fffec00,  0xffffec00, /* Words 40 to 43	*/
+	0xffffec00,  0xffffec00,  0xffffec00,  0xffffec01, /* Words 44 to 47	*/
+	0xffffec00,  0xffffec00,  0xffffec00,  0xffffec00, /* Words 48 to 51	*/
+	0xffffec00,  0xffffec00,  0xffffec00,  0xffffec00, /* Words 52 to 55	*/
+	0xffffec00,  0xffffec00,  0xffffec00,  0xffffec01, /* Words 56 to 59	*/
+	0xffffec00,  0xffffec00,  0xffffec00,  0xffffec01  /* Words 60 to 63	*/
 };
 
 #endif
diff --git a/include/configs/socrates.h b/include/configs/socrates.h
index fdc1557..43e0050 100644
--- a/include/configs/socrates.h
+++ b/include/configs/socrates.h
@@ -45,6 +45,7 @@
 #define CONFIG_TSEC_ENET		/* tsec ethernet support	*/
 
 #define CONFIG_MISC_INIT_R	1	/* Call misc_init_r		*/
+#define CONFIG_BOARD_EARLY_INIT_R 1	/* Call board_early_init_r	*/
 
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
 
@@ -134,13 +135,12 @@
 #define CFG_FLASH_BASE		CFG_LBC_FLASH_BASE /* start of FLASH	*/
 
 #define CFG_BR0_PRELIM		0xfe001001	/* port size 16bit	*/
-#define CFG_OR0_PRELIM		0xfe000ff7	/* 32MB Flash		*/
+#define CFG_OR0_PRELIM		0xfe000030	/* 32MB Flash		*/
 #define CFG_BR1_PRELIM		0xfc001001	/* port size 16bit	*/
-#define CFG_OR1_PRELIM		0xfe000ff7	/* 32MB Flash		*/
+#define CFG_OR1_PRELIM		0xfe000030	/* 32MB Flash		*/
 
 #define CFG_FLASH_CFI				/* flash is CFI compat.	*/
 #define CONFIG_FLASH_CFI_DRIVER			/* Use common CFI driver*/
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector	*/
 
 #define CFG_MAX_FLASH_BANKS	2		/* number of banks	*/
 #define CFG_MAX_FLASH_SECT	256		/* sectors per device	*/
@@ -150,7 +150,7 @@
 
 #define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor	*/
 
-#define CFG_LBC_LCRR		0x00030008    /* LB clock ratio reg	*/
+#define CFG_LBC_LCRR		0x00030004    /* LB clock ratio reg	*/
 #define CFG_LBC_LBCR		0x00000000    /* LB config reg		*/
 #define CFG_LBC_LSRT		0x20000000    /* LB sdram refresh timer	*/
 #define CFG_LBC_MRTPR		0x20000000    /* LB refresh timer presc.*/
@@ -164,8 +164,20 @@
 #define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 #define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256kB for Mon*/
-#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserved for malloc	*/
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256kB for Mon */
+#define CFG_MALLOC_LEN		(4 << 20)	/* Reserve 4 MB for malloc */
+
+/* FPGA and NAND */
+#define CFG_FPGA_BASE		0xc0000000
+#define CFG_FPGA_SIZE		0x00100000	/* 1 MB		*/
+#define CFG_HMI_BASE		0xc0010000
+#define CFG_BR3_PRELIM		0xc0001881	/* UPMA, 32-bit */
+#define CFG_OR3_PRELIM		0xfff00000	/* 1 MB 	*/
+
+#define CFG_NAND_BASE		(CFG_FPGA_BASE + 0x70)
+#define CFG_MAX_NAND_DEVICE	1
+#define NAND_MAX_CHIPS		1
+#define CONFIG_CMD_NAND
 
 /* Serial Port */
 
@@ -197,11 +209,14 @@
 #define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
 #define CONFIG_HARD_I2C			/* I2C with hardware support	*/
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CFG_I2C_SPEED		102124	/* I2C speed and slave address	*/
 #define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_NOPROBES	{0x48}	/* Don't probe these addrs	*/
 #define CFG_I2C_OFFSET		0x3000
 
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
+#define CFG_I2C2_OFFSET		0x3100
+
 /* I2C RTC */
 #define CONFIG_RTC_RX8025		/* Use Epson rx8025 rtc via i2c	*/
 #define CFG_I2C_RTC_ADDR	0x32	/*@address 0x32		*/
@@ -295,18 +310,18 @@
 #define CONFIG_CMD_DTT
 #undef CONFIG_CMD_EEPROM
 #define CONFIG_CMD_I2C
+#define CONFIG_CMD_SDRAM
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_NFS
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_SNTP
 #define CONFIG_CMD_USB
-
+#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
 
 #if defined(CONFIG_PCI)
     #define CONFIG_CMD_PCI
 #endif
 
-
 #undef CONFIG_WATCHDOG			/* watchdog disabled		*/
 
 /*
@@ -350,50 +365,69 @@
 
 #define CONFIG_LOADADDR	 200000		/* default addr for tftp & bootm*/
 
-#define CONFIG_BOOTDELAY 5		/* -1 disables auto-boot	*/
+#define CONFIG_BOOTDELAY 1		/* -1 disables auto-boot	*/
 
 #define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
+	"echo Welcome on the ABB Socrates Board;" \
 	"echo"
 
 #undef	CONFIG_BOOTARGS		/* the boot command will set bootargs	*/
 
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"bootfile=$hostname/uImage\0"					\
 	"netdev=eth0\0"							\
 	"consdev=ttyS0\0"						\
-	"hostname=socrates\0"						\
+	"uboot_file=/home/tftp/syscon3/u-boot.bin\0"			\
+	"bootfile=/home/tftp/syscon3/uImage\0"				\
+	"fdt_file=/home/tftp/syscon3/socrates.dtb\0"			\
+	"initrd_file=/home/tftp/syscon3/uinitrd.gz\0"			\
+	"uboot_addr=FFFA0000\0"						\
+	"kernel_addr=FE000000\0"					\
+	"fdt_addr=FE1E0000\0"						\
+	"ramdisk_addr=FE200000\0"					\
+	"fdt_addr_r=B00000\0"						\
+	"kernel_addr_r=200000\0"					\
+	"ramdisk_addr_r=400000\0"					\
+	"rootpath=/opt/eldk/ppc_85xxDP\0"				\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
 		"nfsroot=$serverip:$rootpath\0"				\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addcons=setenv bootargs $bootargs "				\
+		"console=$consdev,$baudrate\0"				\
 	"addip=setenv bootargs $bootargs "				\
 		"ip=$ipaddr:$serverip:$gatewayip:$netmask"		\
 		":$hostname:$netdev:off panic=1\0"			\
-	"addcons=setenv bootargs $bootargs "				\
-		"console=$consdev,$baudrate\0"				\
-	"flash_self=run ramargs addip addcons;"				\
+	"boot_nor=run ramargs addcons;"					\
 		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
-	"flash_nfs=run nfsargs addip addcons;"				\
-		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
 	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; "			\
 		"tftp ${fdt_addr_r} ${fdt_file}; "			\
 		"run nfsargs addip addcons;"				\
 		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
-	"fdt_file=$hostname/socrates.dtb\0"				\
-	"fdt_addr_r=B00000\0"						\
-	"fdt_addr=FC1E0000\0"						\
-	"rootpath=/opt/eldk/ppc_85xxDP\0"				\
-	"kernel_addr=FC000000\0"					\
-	"kernel_addr_r=200000\0"					\
-	"ramdisk_addr=FC200000\0"					\
-	"ramdisk_addr_r=400000\0"					\
-	"load=tftp 100000 $hostname/u-boot.bin\0"		\
-	"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;"	\
-		"cp.b 100000 fffc0000 40000;"			        \
+	"update_uboot=tftp 100000 ${uboot_file};"			\
+		"protect off fffa0000 ffffffff;"			\
+		"era fffa0000 ffffffff;"				\
+		"cp.b 100000 fffa0000 ${filesize};"			\
+		"setenv filesize;saveenv\0"				\
+	"update_kernel=tftp 100000 ${bootfile};"			\
+		"era fe000000 fe1dffff;"				\
+		"cp.b 100000 fe000000 ${filesize};"			\
 		"setenv filesize;saveenv\0"				\
-	"upd=run load update\0"						\
+	"update_fdt=tftp 100000 ${fdt_file};" 				\
+		"era fe1e0000 fe1fffff;"				\
+		"cp.b 100000 fe1e0000 ${filesize};"			\
+		"setenv filesize;saveenv\0"				\
+	"update_initrd=tftp 100000 ${initrd_file};" 			\
+		"era fe200000 fe9fffff;"				\
+		"cp.b 100000 fe200000 ${filesize};"			\
+		"setenv filesize;saveenv\0"				\
+	"clean_data=era fea00000 fff5ffff\0"				\
+	"usbargs=setenv bootargs root=/dev/sda1 rw\0" 			\
+	"load_usb=usb start;" 						\
+		"ext2load usb 0:1 ${kernel_addr_r} /boot/uImage\0"	\
+	"boot_usb=run load_usb usbargs addcons;"			\
+		"bootm ${kernel_addr_r} - ${fdt_addr};"			\
+		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
 	""
-#define CONFIG_BOOTCOMMAND	"run flash_self"
+#define CONFIG_BOOTCOMMAND	"run boot_nor"
 
 /* pass open firmware flat tree */
 #define CONFIG_OF_LIBFDT	1
@@ -410,14 +444,4 @@
 #define CONFIG_DOS_PARTITION		1
 #define CONFIG_USB_STORAGE		1
 
-/* FPGA and NAND */
-#define CFG_FPGA_BASE			0xc0000000
-#define CFG_BR3_PRELIM			0xc0001881 /* UPMA, 32-bit */
-#define CFG_OR3_PRELIM			0xfff00000  /* 1 MB */
-
-#define CFG_NAND_BASE			(CFG_FPGA_BASE + 0x70)
-#define CFG_MAX_NAND_DEVICE		1
-#define NAND_MAX_CHIPS			1
-#define CONFIG_CMD_NAND
-
 #endif	/* __CONFIG_H */
-- 
1.5.6.1

[U-Boot] unassigned-patches/26: [PATCH] 85xx: socrates: Enable Lime support.

[u-boot at bugs.denx.de]

This patch adds Lime GDC support together with support for the PWM
backlight control through the w83782d chip.  The reset pin of the
latter is attached to GPIO, so we need to reset it in
early_board_init_r.

Signed-off-by: Anatolij Gustschin <agust@denx.de>

---
Added to GNATS database as unassigned-patches/26
>Responsible:    patch-coord
>Message-Id:     <1218807733-26929-6-git-send-email-dzu@denx.de>
>In-Reply-To:    <1218807733-26929-5-git-send-email-dzu@denx.de>
>References:     <1218807733-26929-1-git-send-email-dzu@denx.de> <1218807733-26929-2-git-send-email-dzu@denx.de> <1218807733-26929-3-git-send-email-dzu@denx.de> <1218807733-26929-4-git-send-email-dzu@denx.de> <1218807733-26929-5-git-send-email-dzu@denx.de>
>Patch-Date:     Fri Aug 15 15:42:13 +0200 2008
---
 board/socrates/law.c       |    4 +-
 board/socrates/socrates.c  |  198 ++++++++++++++++++++++++++++++++++++++++++++
 board/socrates/tlb.c       |   13 +++-
 board/socrates/upm_table.h |   20 +++++
 drivers/video/mb862xx.c    |    3 +-
 include/configs/socrates.h |   24 ++++++
 6 files changed, 259 insertions(+), 3 deletions(-)

diff --git a/board/socrates/law.c b/board/socrates/law.c
index 35c4a90..89b446f 100644
--- a/board/socrates/law.c
+++ b/board/socrates/law.c
@@ -36,6 +36,7 @@
  * 0x0000_0000	   0x2fff_ffff	   DDR			   512M
  * 0x8000_0000	   0x9fff_ffff	   PCI1 MEM		   512M
  * 0xc000_0000	   0xc00f_ffff	   FPGA			   1M
+ * 0xc800_0000	   0xcbff_ffff	   LIME			   64M
  * 0xe000_0000	   0xe00f_ffff	   CCSR			   1M (mapped by CCSRBAR)
  * 0xe200_0000	   0xe2ff_ffff	   PCI1 IO		   16M
  * 0xfc00_0000	   0xffff_ffff	   FLASH		   64M
@@ -48,11 +49,12 @@
 struct law_entry law_table[] = {
 	SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
 	SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
-	SET_LAW(CFG_LBC_FLASH_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
+	SET_LAW(CFG_LBC_FLASH_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
 	SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
 #if defined(CFG_FPGA_BASE)
 	SET_LAW(CFG_FPGA_BASE, LAWAR_SIZE_1M, LAW_TRGT_IF_LBC),
 #endif
+	SET_LAW(CFG_LIME_BASE, LAWAR_SIZE_64M, LAW_TRGT_IF_LBC),
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c
index 63694a7..73a2d9d 100644
--- a/board/socrates/socrates.c
+++ b/board/socrates/socrates.c
@@ -173,6 +173,12 @@ void local_bus_init (void)
 	/* Init UPMA for FPGA access */
 	out_be32 (&lbc->mamr, 0x44440); /* Use a customer-supplied value */
 	upmconfig (UPMA, (uint *)UPMTableA, sizeof(UPMTableA)/sizeof(int));
+
+	if (getenv("lime")) {
+		/* Init UPMB for Lime controller access */
+		out_be32 (&lbc->mbmr, 0x444440); /* Use a customer-supplied value */
+		upmconfig (UPMB, (uint *)UPMTableB, sizeof(UPMTableB)/sizeof(int));
+	}
 }
 
 #if defined(CONFIG_PCI)
@@ -239,6 +245,14 @@ ft_board_setup(void *blob, bd_t *bd)
 	val[i++] = gd->bd->bi_flashstart;
 	val[i++] = gd->bd->bi_flashsize;
 
+	if (getenv("lime")) {
+		/* Fixup LIME mapping */
+		val[i++] = 2;			/* chip select number */
+		val[i++] = 0;			/* always 0 */
+		val[i++] = CFG_LIME_BASE;
+		val[i++] = CFG_LIME_SIZE;
+	}
+
 	/* Fixup FPGA mapping */
 	val[i++] = 3;				/* chip select number */
 	val[i++] = 0;				/* always 0 */
@@ -252,3 +266,187 @@ ft_board_setup(void *blob, bd_t *bd)
 		       fdt_strerror(rc));
 }
 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+
+#include <i2c.h>
+#include <mb862xx.h>
+#include <video_fb.h>
+
+#define CFG_LIME_SRST		((CFG_LIME_BASE) + 0x01FC002C)
+#define CFG_LIME_CCF		((CFG_LIME_BASE) + 0x01FC0038)
+#define CFG_LIME_MMR		((CFG_LIME_BASE) + 0x01FCFFFC)
+/* Lime clock frequency */
+#define CFG_LIME_CLK_100MHZ	0x00000
+#define CFG_LIME_CLK_133MHZ	0x10000
+/* SDRAM parameter */
+#define CFG_LIME_MMR_VALUE	0x4157BA63
+
+#define DISPLAY_WIDTH		800
+#define DISPLAY_HEIGHT		480
+#define DEFAULT_BRIGHTNESS	25
+#define BACKLIGHT_ENABLE	(1 << 31)
+
+extern GraphicDevice mb862xx;
+
+static const gdc_regs init_regs [] =
+{
+	{0x0100, 0x00010f00},
+	{0x0020, 0x801901df},
+	{0x0024, 0x00000000},
+	{0x0028, 0x00000000},
+	{0x002c, 0x00000000},
+	{0x0110, 0x00000000},
+	{0x0114, 0x00000000},
+	{0x0118, 0x01df0320},
+	{0x0004, 0x041f0000},
+	{0x0008, 0x031f031f},
+	{0x000c, 0x017f0349},
+	{0x0010, 0x020c0000},
+	{0x0014, 0x01df01e9},
+	{0x0018, 0x00000000},
+	{0x001c, 0x01e00320},
+	{0x0100, 0x80010f00},
+	{0x0, 0x0}
+};
+
+const gdc_regs *board_get_regs (void)
+{
+	return init_regs;
+}
+
+/* Returns Lime base address */
+unsigned int board_video_init (void)
+{
+
+	if (!getenv("lime"))
+		return 0;
+
+	/*
+	 * Reset Lime controller
+	 */
+	out_be32((void *)CFG_LIME_SRST, 0x1);
+	udelay(200);
+
+	/* Set Lime clock to 133MHz */
+	out_be32((void *)CFG_LIME_CCF, CFG_LIME_CLK_133MHZ);
+	/* Delay required */
+	udelay(300);
+	/* Set memory parameters */
+	out_be32((void *)CFG_LIME_MMR, CFG_LIME_MMR_VALUE);
+
+	mb862xx.winSizeX = DISPLAY_WIDTH;
+	mb862xx.winSizeY = DISPLAY_HEIGHT;
+	mb862xx.gdfIndex = GDF_15BIT_555RGB;
+	mb862xx.gdfBytesPP = 2;
+
+	return CFG_LIME_BASE;
+}
+
+#define W83782D_REG_CFG		0x40
+#define W83782D_REG_BANK_SEL	0x4e
+#define W83782D_REG_ADCCLK	0x4b
+#define W83782D_REG_BEEP_CTRL	0x4d
+#define W83782D_REG_BEEP_CTRL2	0x57
+#define W83782D_REG_PWMOUT1	0x5b
+#define W83782D_REG_VBAT	0x5d
+
+static int w83782d_hwmon_init(void)
+{
+	u8 buf;
+
+	if (i2c_read(CFG_I2C_W83782G_ADDR, W83782D_REG_CFG, 1, &buf, 1))
+		return -1;
+
+	i2c_reg_write(CFG_I2C_W83782G_ADDR, W83782D_REG_CFG, 0x80);
+	i2c_reg_write(CFG_I2C_W83782G_ADDR, W83782D_REG_BANK_SEL, 0);
+	i2c_reg_write(CFG_I2C_W83782G_ADDR, W83782D_REG_ADCCLK, 0x40);
+
+	buf = i2c_reg_read(CFG_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL);
+	i2c_reg_write(CFG_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL,
+		      buf | 0x80);
+	i2c_reg_write(CFG_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL2, 0);
+	i2c_reg_write(CFG_I2C_W83782G_ADDR, W83782D_REG_PWMOUT1, 0x47);
+	i2c_reg_write(CFG_I2C_W83782G_ADDR, W83782D_REG_VBAT, 0x01);
+
+	buf = i2c_reg_read(CFG_I2C_W83782G_ADDR, W83782D_REG_CFG);
+	i2c_reg_write(CFG_I2C_W83782G_ADDR, W83782D_REG_CFG,
+		      (buf & 0xf4) | 0x01);
+	return 0;
+}
+
+static void board_backlight_brightness(int br)
+{
+	u32 reg;
+	u8 buf;
+	u8 old_buf;
+
+	/* Select bank 0 */
+	if (i2c_read(CFG_I2C_W83782G_ADDR, 0x4e, 1, &old_buf, 1))
+		goto err;
+	else
+		buf = old_buf & 0xf8;
+
+	if (i2c_write(CFG_I2C_W83782G_ADDR, 0x4e, 1, &buf, 1))
+		goto err;
+
+	if (br > 0) {
+		/* PWMOUT1 duty cycle ctrl */
+		buf = 255 / (100 / br);
+		if (i2c_write(CFG_I2C_W83782G_ADDR, 0x5b, 1, &buf, 1))
+			goto err;
+
+		/* LEDs on */
+		reg = in_be32((void *)(CFG_FPGA_BASE + 0x0c));
+		if (!(reg & BACKLIGHT_ENABLE));
+			out_be32((void *)(CFG_FPGA_BASE + 0x0c),
+				 reg | BACKLIGHT_ENABLE);
+	} else {
+		buf = 0;
+		if (i2c_write(CFG_I2C_W83782G_ADDR, 0x5b, 1, &buf, 1))
+			goto err;
+
+		/* LEDs off */
+		reg = in_be32((void *)(CFG_FPGA_BASE + 0x0c));
+		reg &= ~BACKLIGHT_ENABLE;
+		out_be32((void *)(CFG_FPGA_BASE + 0x0c), reg);
+	}
+	/* Restore previous bank setting */
+	if (i2c_write(CFG_I2C_W83782G_ADDR, 0x4e, 1, &old_buf, 1))
+		goto err;
+
+	return;
+err:
+	printf("W83782G I2C access failed\n");
+}
+
+void board_backlight_switch (int flag)
+{
+	char * param;
+	int rc;
+
+	if (w83782d_hwmon_init())
+		printf ("hwmon IC init failed\n");
+
+	if (flag) {
+		param = getenv("brightness");
+		rc = param ? simple_strtol(param, NULL, 10) : -1;
+		if (rc < 0)
+			rc = DEFAULT_BRIGHTNESS;
+	} else {
+		rc = 0;
+	}
+	board_backlight_brightness(rc);
+}
+
+#if defined(CONFIG_CONSOLE_EXTRA_INFO)
+/*
+ * Return text to be printed besides the logo.
+ */
+void video_get_info_str (int line_number, char *info)
+{
+	if (line_number == 1) {
+		strcpy (info, " Board: Socrates");
+	} else {
+		info [0] = '\0';
+	}
+}
+#endif
diff --git a/board/socrates/tlb.c b/board/socrates/tlb.c
index aea99ad..d255cea 100644
--- a/board/socrates/tlb.c
+++ b/board/socrates/tlb.c
@@ -46,7 +46,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 
 
 	/*
-	 * TLB 0:	64M	Non-cacheable, guarded
+	 * TLB 1:	64M	Non-cacheable, guarded
 	 * 0xfc000000	64M	FLASH
 	 * Out of reset this entry is only 4K.
 	 */
@@ -81,6 +81,17 @@ struct fsl_e_tlb_entry tlb_table[] = {
 #endif
 
 	/*
+	 * TLB 5:	64M	Non-cacheable, guarded
+	 * 0xc8000000	16M	LIME GDC framebuffer
+	 * 0xc9fc0000	256K	LIME GDC MMIO
+	 * (0xcbfc0000	256K	LIME GDC MMIO)
+	 * MMIO is relocatable and could be at 0xcbfc0000
+	 */
+	SET_TLB_ENTRY(1, CFG_LIME_BASE, CFG_LIME_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 5, BOOKE_PAGESZ_64M, 1),
+
+	/*
 	 * TLB 6:	64M	Non-cacheable, guarded
 	 * 0xe000_0000	1M	CCSRBAR
 	 * 0xe200_0000	16M	PCI1 IO
diff --git a/board/socrates/upm_table.h b/board/socrates/upm_table.h
index ed8f887..2a89c96 100644
--- a/board/socrates/upm_table.h
+++ b/board/socrates/upm_table.h
@@ -52,4 +52,24 @@ static const unsigned int UPMTableA[] =
 	0xffffec00,  0xffffec00,  0xffffec00,  0xffffec01  /* Words 60 to 63	*/
 };
 
+/* LIME UPM B Table Configuration Code */
+static unsigned int UPMTableB[] =
+{
+	0x0ffefc00,  0x0ffcfc00,  0x0ffcfc00,  0x0ffcfc00, /* Words 0 to 3	*/
+	0x0ffcfc00,  0x0ffcfc00,  0x0ffcfc04,  0x0ffffc01, /* Words 4 to 7	*/
+	0x0ffefc00,  0x0ffcfc00,  0x0ffcfc00,  0x0ffcfc00, /* Words 8 to 11	*/
+	0x0ffcfc00,  0x0ffcfc00,  0x0ffcfc04,  0x0ffcfc04, /* Words 12 to 15	*/
+	0x0ffcfc04,  0x0ffcfc04,  0x0ffcfc04,  0x0ffcfc04, /* Words 16 to 19	*/
+	0x0ffcfc04,  0x0ffcfc04,  0x0ffffc00,  0xfffffc01, /* Words 20 to 23	*/
+	0x0cfffc00,  0x00fffc00,  0x00fffc00,  0x00fffc00, /* Words 24 to 27	*/
+	0x00fffc00,  0x00fffc00,  0x00fffc04,  0x0ffffc01, /* Words 28 to 31	*/
+	0x0cfffc00,  0x00fffc00,  0x00fffc00,  0x00fffc00, /* Words 32 to 35	*/
+	0x00fffc00,  0x00fffc00,  0x00fffc04,  0x00fffc04, /* Words 36 to 39	*/
+	0x00fffc04,  0x00fffc04,  0x00fffc04,  0x00fffc04, /* Words 40 to 43	*/
+	0x00fffc04,  0x00fffc04,  0x0ffffc00,  0xfffffc01, /* Words 44 to 47	*/
+	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc00, /* Words 48 to 51	*/
+	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc00, /* Words 52 to 55	*/
+	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc01, /* Words 56 to 59	*/
+	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc01  /* Words 60 to 63	*/
+};
 #endif
diff --git a/drivers/video/mb862xx.c b/drivers/video/mb862xx.c
index 733d9a2..262963c 100644
--- a/drivers/video/mb862xx.c
+++ b/drivers/video/mb862xx.c
@@ -359,7 +359,8 @@ void *video_hw_init (void)
 	board_disp_init();
 #endif
 
-#if defined(CONFIG_LWMON5) && !(CONFIG_POST & CFG_POST_SYSMON)
+#if (defined(CONFIG_LWMON5) || \
+     defined(CONFIG_SOCRATES)) && !(CONFIG_POST & CFG_POST_SYSMON)
 	/* Lamp on */
 	board_backlight_switch (1);
 #endif
diff --git a/include/configs/socrates.h b/include/configs/socrates.h
index 43e0050..4c7308e 100644
--- a/include/configs/socrates.h
+++ b/include/configs/socrates.h
@@ -179,6 +179,26 @@
 #define NAND_MAX_CHIPS		1
 #define CONFIG_CMD_NAND
 
+/* LIME GDC */
+#define CFG_LIME_BASE		0xc8000000
+#define CFG_LIME_SIZE		0x04000000	/* 64 MB	*/
+#define CFG_BR2_PRELIM		0xc80018a1	/* UPMB, 32-bit	*/
+#define CFG_OR2_PRELIM		0xfc000000	/* 64 MB	*/
+
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_MB862xx
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_CONSOLE_EXTRA_INFO
+#define VIDEO_FB_16BPP_PIXEL_SWAP
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CFG_CONSOLE_IS_IN_ENV
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_VIDEO_BMP_GZIP
+#define CFG_VIDEO_LOGO_MAX_SIZE	(2 << 20)	/* decompressed img */
+
 /* Serial Port */
 
 #define CONFIG_CONS_INDEX     1
@@ -221,6 +241,9 @@
 #define CONFIG_RTC_RX8025		/* Use Epson rx8025 rtc via i2c	*/
 #define CFG_I2C_RTC_ADDR	0x32	/*@address 0x32		*/
 
+/* I2C W83782G HW-Monitoring IC */
+#define CFG_I2C_W83782G_ADDR	0x28	/* W83782G address 		*/
+
 /* I2C temp sensor */
 /* Socrates uses Maxim's	DS75, which is compatible with LM75 */
 #define CONFIG_DTT_LM75		1
@@ -317,6 +340,7 @@
 #define CONFIG_CMD_SNTP
 #define CONFIG_CMD_USB
 #define CONFIG_CMD_EXT2		/* EXT2 Support			*/
+#define CONFIG_CMD_BMP
 
 #if defined(CONFIG_PCI)
     #define CONFIG_CMD_PCI
-- 
1.5.6.1

[U-Boot] unassigned-patches/25: [PATCH] USB EHCI: reset root hub

[u-boot at bugs.denx.de]

 Some of multi-function USB controllers (e.g. ISP1562) allow root hub
resetting only via EHCI registers. So, this patch adds the corresponding
kind of reset to OHCI's hc_reset() if the newly introduced CONFIG_PCI_EHCI_DEVNO
option is set (e.g. for Socrates board).

Signed-off-by: Yuri Tikhonov <yur@emcraft.com>

---
Added to GNATS database as unassigned-patches/25
>Responsible:    patch-coord
>Message-Id:     <1218807733-26929-3-git-send-email-dzu@denx.de>
>In-Reply-To:    <1218807733-26929-2-git-send-email-dzu@denx.de>
>References:     <1218807733-26929-1-git-send-email-dzu@denx.de> <1218807733-26929-2-git-send-email-dzu@denx.de>
>Patch-Date:     Fri Aug 15 15:42:10 +0200 2008
---
 drivers/usb/usb_ohci.c     |   31 +++++++++++++++++++++++++++++++
 drivers/usb/usb_ohci.h     |    3 +++
 include/configs/socrates.h |    1 +
 3 files changed, 35 insertions(+), 0 deletions(-)

diff --git a/drivers/usb/usb_ohci.c b/drivers/usb/usb_ohci.c
index fd60edb..0f5bd06 100644
--- a/drivers/usb/usb_ohci.c
+++ b/drivers/usb/usb_ohci.c
@@ -1571,11 +1571,42 @@ int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
 
 static int hc_reset (ohci_t *ohci)
 {
+#ifdef CONFIG_PCI_EHCI_DEVNO
+	pci_dev_t pdev;
+	struct pci_device_id ehci_pci_ids[] = {
+		{0x1131, 0x1562},	/* Philips 1562 PCI EHCI module ids */
+		{0, 0}
+	};
+#endif
 	int timeout = 30;
 	int smm_timeout = 50; /* 0,5 sec */
 
 	dbg("%s\n", __FUNCTION__);
 
+#ifdef CONFIG_PCI_EHCI_DEVNO
+	/*
+	 *  Some multi-function controllers (e.g. ISP1562) allow root hub
+	 * resetting via EHCI registers only.
+	 */
+	pdev = pci_find_devices(ehci_pci_ids, CONFIG_PCI_EHCI_DEVNO);
+	if (pdev != -1) {
+		u32 base;
+		int timeout = 1000;
+
+		pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &base);
+		writel (readl(base + EHCI_USBCMD_OFF) | EHCI_USBCMD_HCRESET,
+			base + EHCI_USBCMD_OFF);
+
+		while (readl(base + EHCI_USBCMD_OFF) & EHCI_USBCMD_HCRESET) {
+			if (timeout-- <= 0) {
+				printf("USB RootHub reset timed out!");
+				break;
+			}
+			udelay(1);
+		}
+	} else
+		printf("No EHCI func@%d index!\n", CONFIG_PCI_EHCI_DEVNO);
+#endif
 	if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */
 		writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */
 		info("USB HC TakeOver from SMM");
diff --git a/drivers/usb/usb_ohci.h b/drivers/usb/usb_ohci.h
index 380cb4c..7a04bf5 100644
--- a/drivers/usb/usb_ohci.h
+++ b/drivers/usb/usb_ohci.h
@@ -195,6 +195,9 @@ struct ohci_regs {
 	} roothub;
 } __attribute((aligned(32)));
 
+/* Some EHCI controls */
+#define EHCI_USBCMD_OFF		0x20
+#define EHCI_USBCMD_HCRESET	(1 << 1)
 
 /* OHCI CONTROL AND STATUS REGISTER MASKS */
 
diff --git a/include/configs/socrates.h b/include/configs/socrates.h
index 8a64942..fdc1557 100644
--- a/include/configs/socrates.h
+++ b/include/configs/socrates.h
@@ -403,6 +403,7 @@
 #define CONFIG_USB_OHCI_NEW		1
 #define CONFIG_PCI_OHCI			1
 #define CONFIG_PCI_OHCI_DEVNO		3 /* Number in PCI list */
+#define CONFIG_PCI_EHCI_DEVNO		(CONFIG_PCI_OHCI_DEVNO / 2)
 #define CFG_USB_OHCI_MAX_ROOT_PORTS	15
 #define CFG_USB_OHCI_SLOT_NAME		"ohci_pci"
 #define CFG_OHCI_SWAP_REG_ACCESS	1
-- 
1.5.6.1

[U-Boot] unassigned-patches/25: [PATCH] USB EHCI: reset root hub

[Detlev Zundel]

Hi Markus,

>  Some of multi-function USB controllers (e.g. ISP1562) allow root hub
> resetting only via EHCI registers. So, this patch adds the corresponding
> kind of reset to OHCI's hc_reset() if the newly introduced CONFIG_PCI_EHCI_DEVNO
> option is set (e.g. for Socrates board).
>
> Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
>
> ---
> Added to GNATS database as unassigned-patches/25
>>Responsible:    patch-coord
>>Message-Id:     <1218807733-26929-3-git-send-email-dzu@denx.de>
>>In-Reply-To:    <1218807733-26929-2-git-send-email-dzu@denx.de>
>>References:     <1218807733-26929-1-git-send-email-dzu@denx.de> <1218807733-26929-2-git-send-email-dzu@denx.de>
>>Patch-Date:     Fri Aug 15 15:42:10 +0200 2008
> ---
>  drivers/usb/usb_ohci.c     |   31 +++++++++++++++++++++++++++++++
>  drivers/usb/usb_ohci.h     |    3 +++
>  include/configs/socrates.h |    1 +
>  3 files changed, 35 insertions(+), 0 deletions(-)

Any comments on this?

Thanks
  Detlev

-- 
"Oh, didn't you know, the Lord did the original programming of the universe in
COBOL." - "That's why the world is the evil work of Satan. A true divine being
would have used Scheme."  -  "And, if so, Jesus would have been crucified on a
big lambda symbol."  -- K. Chafin, K. Schilling & D. Hanley, on comp.lang.lisp
--
DENX Software Engineering GmbH,      MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich,  Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-40 Fax: (+49)-8142-66989-80 Email: dzu at denx.de

[U-Boot] unassigned-patches/25: [PATCH] USB EHCI: reset root hub

[Markus Klotzbücher]

Hi Detlev,

On Mon, Sep 01, 2008 at 05:41:48PM +0200, Detlev Zundel wrote:

> >  Some of multi-function USB controllers (e.g. ISP1562) allow root hub
> > resetting only via EHCI registers. So, this patch adds the corresponding
> > kind of reset to OHCI's hc_reset() if the newly introduced CONFIG_PCI_EHCI_DEVNO
> > option is set (e.g. for Socrates board).
> >
> > Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
> >
> > ---
> > Added to GNATS database as unassigned-patches/25
> >>Responsible:    patch-coord
> >>Message-Id:     <1218807733-26929-3-git-send-email-dzu@denx.de>
> >>In-Reply-To:    <1218807733-26929-2-git-send-email-dzu@denx.de>
> >>References:     <1218807733-26929-1-git-send-email-dzu@denx.de> <1218807733-26929-2-git-send-email-dzu@denx.de>
> >>Patch-Date:     Fri Aug 15 15:42:10 +0200 2008
> > ---
> >  drivers/usb/usb_ohci.c     |   31 +++++++++++++++++++++++++++++++
> >  drivers/usb/usb_ohci.h     |    3 +++
> >  include/configs/socrates.h |    1 +
> >  3 files changed, 35 insertions(+), 0 deletions(-)
> 
> Any comments on this?

Not yet, but I promise to look into it this week.

Best regards
Markus

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de")

[U-Boot] unassigned-patches/25: [PATCH] USB EHCI: reset root hub

[Markus Klotzbücher]

Dear Yuri,

On Fri, Aug 15, 2008 at 03:45:02PM +0200, u-boot at bugs.denx.de wrote:

>  Some of multi-function USB controllers (e.g. ISP1562) allow root hub
> resetting only via EHCI registers. So, this patch adds the corresponding
> kind of reset to OHCI's hc_reset() if the newly introduced CONFIG_PCI_EHCI_DEVNO
> option is set (e.g. for Socrates board).
> 
> Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
> 
> ---
> Added to GNATS database as unassigned-patches/25
> >Responsible:    patch-coord
> >Message-Id:     <1218807733-26929-3-git-send-email-dzu@denx.de>
> >In-Reply-To:    <1218807733-26929-2-git-send-email-dzu@denx.de>
> >References:     <1218807733-26929-1-git-send-email-dzu@denx.de> <1218807733-26929-2-git-send-email-dzu@denx.de>
> >Patch-Date:     Fri Aug 15 15:42:10 +0200 2008
> ---
>  drivers/usb/usb_ohci.c     |   31 +++++++++++++++++++++++++++++++
>  drivers/usb/usb_ohci.h     |    3 +++
>  include/configs/socrates.h |    1 +
>  3 files changed, 35 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/usb/usb_ohci.c b/drivers/usb/usb_ohci.c
> index fd60edb..0f5bd06 100644
> --- a/drivers/usb/usb_ohci.c
> +++ b/drivers/usb/usb_ohci.c
> @@ -1571,11 +1571,42 @@ int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
>  
>  static int hc_reset (ohci_t *ohci)
>  {
> +#ifdef CONFIG_PCI_EHCI_DEVNO
> +	pci_dev_t pdev;
> +	struct pci_device_id ehci_pci_ids[] = {
> +		{0x1131, 0x1562},	/* Philips 1562 PCI EHCI module ids */
> +		{0, 0}
> +	};

Please move this out of the function, preferrably next to the OHCI
device ids.

Thanks!

Best regards

Markus

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de")

[U-Boot] [PATCH v2] USB EHCI: reset root hub

[Detlev Zundel]

From: Yuri Tikhonov <yur@emcraft.com>

Some of multi-function USB controllers (e.g. ISP1562) allow root hub
resetting only via EHCI registers. So, this patch adds the corresponding
kind of reset to OHCI's hc_reset() if the newly introduced CONFIG_PCI_EHCI_DEVNO
option is set (e.g. for Socrates board).

Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
---
 drivers/usb/usb_ohci.c     |   35 +++++++++++++++++++++++++++++++++++
 drivers/usb/usb_ohci.h     |    3 +++
 include/configs/socrates.h |    1 +
 3 files changed, 39 insertions(+), 0 deletions(-)

This new version addresses Markus feedback.


diff --git a/drivers/usb/usb_ohci.c b/drivers/usb/usb_ohci.c
index fd60edb..ce13866 100644
--- a/drivers/usb/usb_ohci.c
+++ b/drivers/usb/usb_ohci.c
@@ -108,6 +108,14 @@ static struct pci_device_id ohci_pci_ids[] = {
 };
 #endif
 
+#ifdef CONFIG_PCI_EHCI_DEVNO
+static struct pci_device_id ehci_pci_ids[] = {
+	{0x1131, 0x1562},	/* Philips 1562 PCI EHCI module ids */
+	/* Please add supported PCI EHCI controller ids here */
+	{0, 0}
+};
+#endif
+
 #ifdef DEBUG
 #define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
 #else
@@ -1571,11 +1579,38 @@ int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
 
 static int hc_reset (ohci_t *ohci)
 {
+#ifdef CONFIG_PCI_EHCI_DEVNO
+	pci_dev_t pdev;
+#endif
 	int timeout = 30;
 	int smm_timeout = 50; /* 0,5 sec */
 
 	dbg("%s\n", __FUNCTION__);
 
+#ifdef CONFIG_PCI_EHCI_DEVNO
+	/*
+	 *  Some multi-function controllers (e.g. ISP1562) allow root hub
+	 * resetting via EHCI registers only.
+	 */
+	pdev = pci_find_devices(ehci_pci_ids, CONFIG_PCI_EHCI_DEVNO);
+	if (pdev != -1) {
+		u32 base;
+		int timeout = 1000;
+
+		pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &base);
+		writel (readl(base + EHCI_USBCMD_OFF) | EHCI_USBCMD_HCRESET,
+			base + EHCI_USBCMD_OFF);
+
+		while (readl(base + EHCI_USBCMD_OFF) & EHCI_USBCMD_HCRESET) {
+			if (timeout-- <= 0) {
+				printf("USB RootHub reset timed out!");
+				break;
+			}
+			udelay(1);
+		}
+	} else
+		printf("No EHCI func@%d index!\n", CONFIG_PCI_EHCI_DEVNO);
+#endif
 	if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */
 		writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */
 		info("USB HC TakeOver from SMM");
diff --git a/drivers/usb/usb_ohci.h b/drivers/usb/usb_ohci.h
index 380cb4c..7a04bf5 100644
--- a/drivers/usb/usb_ohci.h
+++ b/drivers/usb/usb_ohci.h
@@ -195,6 +195,9 @@ struct ohci_regs {
 	} roothub;
 } __attribute((aligned(32)));
 
+/* Some EHCI controls */
+#define EHCI_USBCMD_OFF		0x20
+#define EHCI_USBCMD_HCRESET	(1 << 1)
 
 /* OHCI CONTROL AND STATUS REGISTER MASKS */
 
diff --git a/include/configs/socrates.h b/include/configs/socrates.h
index 8a64942..fdc1557 100644
--- a/include/configs/socrates.h
+++ b/include/configs/socrates.h
@@ -403,6 +403,7 @@
 #define CONFIG_USB_OHCI_NEW		1
 #define CONFIG_PCI_OHCI			1
 #define CONFIG_PCI_OHCI_DEVNO		3 /* Number in PCI list */
+#define CONFIG_PCI_EHCI_DEVNO		(CONFIG_PCI_OHCI_DEVNO / 2)
 #define CFG_USB_OHCI_MAX_ROOT_PORTS	15
 #define CFG_USB_OHCI_SLOT_NAME		"ohci_pci"
 #define CFG_OHCI_SWAP_REG_ACCESS	1
-- 
1.5.6.1

[U-Boot] [PATCH v2] USB EHCI: reset root hub

[Markus Klotzbücher]

On Thu, Sep 04, 2008 at 11:19:05AM +0200, Detlev Zundel wrote:
> From: Yuri Tikhonov <yur@emcraft.com>
> 
> Some of multi-function USB controllers (e.g. ISP1562) allow root hub
> resetting only via EHCI registers. So, this patch adds the corresponding
> kind of reset to OHCI's hc_reset() if the newly introduced CONFIG_PCI_EHCI_DEVNO
> option is set (e.g. for Socrates board).
> 
> Signed-off-by: Yuri Tikhonov <yur@emcraft.com>

Acked-by: Markus Klotzbuecher <mk@denx.de>

Wolfgang, please pick up directly (I consider this a bugfix).

Best regards
Markus

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de")

[U-Boot] [PATCH v2] USB EHCI: reset root hub

[Wolfgang Denk]

Dear Detlev Zundel,

In message <1220519945-12872-1-git-send-email-dzu@denx.de> you wrote:
> From: Yuri Tikhonov <yur@emcraft.com>
> 
> Some of multi-function USB controllers (e.g. ISP1562) allow root hub
> resetting only via EHCI registers. So, this patch adds the corresponding
> kind of reset to OHCI's hc_reset() if the newly introduced CONFIG_PCI_EHCI_DEVNO
> option is set (e.g. for Socrates board).
> 
> Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
> ---
>  drivers/usb/usb_ohci.c     |   35 +++++++++++++++++++++++++++++++++++
>  drivers/usb/usb_ohci.h     |    3 +++
>  include/configs/socrates.h |    1 +
>  3 files changed, 39 insertions(+), 0 deletions(-)
> 
> This new version addresses Markus feedback.

Applied, thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
C makes it easy for you to shoot yourself in the foot. C++ makes that
harder, but when you do, it blows away your whole leg.
                                                 -- Bjarne Stroustrup